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authorJohn Crispin <john@openwrt.org>2012-03-25 08:50:09 +0000
committerJohn Crispin <john@openwrt.org>2012-03-25 08:50:09 +0000
commit0f6a9d5c7c938f40657ca30f588479893606781e (patch)
treecdf2baca2c9b0021baa2c2aa256dee52b627028c /target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch
parentc49f66675e04441b7089abb2aec1e95bda0dfe78 (diff)
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bump kernel to 3.2.12
SVN-Revision: 31060
Diffstat (limited to 'target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch')
-rw-r--r--target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch34
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch b/target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch
new file mode 100644
index 0000000000..a97259c260
--- /dev/null
+++ b/target/linux/lantiq/patches-3.2/0067-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch
@@ -0,0 +1,34 @@
+From 845d2430d74cf6e2326da95b9205258170b30c86 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 20 Mar 2012 09:44:27 +0100
+Subject: [PATCH 67/70] MIPS: lantiq: irqs were not cleared properly on boot
+
+---
+ arch/mips/lantiq/irq.c | 10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
+index 770a10c..d4e70b4 100644
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -327,12 +327,12 @@ void __init arch_init_irq(void)
+ panic("Failed to remap eiu memory\n");
+ }
+
+- /* make sure all irqs are turned off by default */
+- for (i = 0; i < 5; i++)
++ for (i = 0; i < 5; i++) {
++ /* make sure all irqs are turned off by default */
+ ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
+-
+- /* clear all possibly pending interrupts */
+- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
++ /* clear all possibly pending interrupts */
++ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
++ }
+
+ mips_cpu_irq_init();
+
+--
+1.7.7.1
+