layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch b/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch
new file mode 100644
index 0000000000..a5782ffc1a
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch
@@ -0,0 +1,63 @@
+From da44c1517526822e73642fc71b034de8fc7d2b43 Mon Sep 17 00:00:00 2001
+From: Yuan Yao <yao.yuan@freescale.com>
+Date: Tue, 17 Nov 2015 16:44:45 +0800
+Subject: [PATCH 088/113] mtd: spi-nor: fsl-quadspi: add support for ls1021a
+
+[context adjustment]
+
+LS1021a also support Freescale Quad SPI controller.
+Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
+selectable for LS1021A SOC hardwares.
+
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Acked-by: Han xu <han.xu@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/mtd/spi-nor/Kconfig       |    2 +-
+ drivers/mtd/spi-nor/fsl-quadspi.c |   10 ++++++++++
+ 2 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/Kconfig
++++ b/drivers/mtd/spi-nor/Kconfig
+@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS
+ 
+ config SPI_FSL_QUADSPI
+ 	tristate "Freescale Quad SPI controller"
+-	depends on ARCH_MXC || COMPILE_TEST
++	depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST
+ 	depends on HAS_IOMEM
+ 	help
+ 	  This enables support for the Quad SPI controller in master mode.
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -213,6 +213,7 @@ enum fsl_qspi_devtype {
+ 	FSL_QUADSPI_IMX6SX,
+ 	FSL_QUADSPI_IMX7D,
+ 	FSL_QUADSPI_IMX6UL,
++	FSL_QUADSPI_LS1021A,
+ };
+ 
+ struct fsl_qspi_devtype_data {
+@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6
+ 		       | QUADSPI_QUIRK_4X_INT_CLK,
+ };
+ 
++static struct fsl_qspi_devtype_data ls1021a_data = {
++	.devtype = FSL_QUADSPI_LS1021A,
++	.rxfifo = 128,
++	.txfifo = 64,
++	.ahb_buf_size = 1024,
++	.driver_data = 0,
++};
++
+ #define FSL_QSPI_MAX_CHIP	4
+ struct fsl_qspi {
+ 	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
+@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qsp
+ 	{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
+ 	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
+ 	{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
++	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);