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authorYutang Jiang <yutang.jiang@nxp.com>2016-10-29 00:14:32 +0800
committerJohn Crispin <john@phrozen.org>2016-10-31 17:00:10 +0100
commitc6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch)
treed92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch
parenta34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff)
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layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch')
-rw-r--r--target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch53
1 files changed, 53 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch b/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch
new file mode 100644
index 0000000000..da7f18f1f9
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch
@@ -0,0 +1,53 @@
+From 0ce5d6bd62a9f1dbaa2d39c3535a8bdb31cf7951 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav.dogra@nxp.com>
+Date: Wed, 24 Feb 2016 23:12:58 +0530
+Subject: [PATCH 47/70] drivers/memory: Fix build error for arm64
+
+Replace spin_event_timeout() with arch independent macro
+
+Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/memory/fsl_ifc.c | 16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+--- a/drivers/memory/fsl_ifc.c
++++ b/drivers/memory/fsl_ifc.c
+@@ -39,7 +39,7 @@
+ struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+ EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+ #define FSL_IFC_V1_3_0 0x01030000
+-#define IFC_TIMEOUT_MSECS 100000 /* 100ms */
++#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
+
+ /*
+ * convert_ifc_address - convert the base address
+@@ -365,7 +365,7 @@ static int fsl_ifc_resume(struct device
+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
+ struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs;
+ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
+- uint32_t ver = 0, ncfgr, status, ifc_bank, i;
++ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
+
+ /*
+ * IFC interrupts disabled
+@@ -469,12 +469,14 @@ static int fsl_ifc_resume(struct device
+ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
+ &runtime->ifc_nand.ncfgr);
+ /* wait for SRAM_INIT bit to be clear or timeout */
+- status = spin_event_timeout(
+- !(ifc_in32(&runtime->ifc_nand.ncfgr)
+- & IFC_NAND_SRAM_INIT_EN),
+- IFC_TIMEOUT_MSECS, 0);
++ timeout = 10;
++ while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
++ IFC_NAND_SRAM_INIT_EN) && timeout) {
++ mdelay(IFC_TIMEOUT_MSECS);
++ timeout--;
++ }
+
+- if (!status)
++ if (!timeout)
+ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
+ }
+