layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 217 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0017-PCI-mobiveil-Add-PCIe-Gen4-EP-driver-for-NXP-Layersc.patch b/target/linux/layerscape/patches-5.4/812-pcie-0017-PCI-mobiveil-Add-PCIe-Gen4-EP-driver-for-NXP-Layersc.patch
new file mode 100644
index 0000000000..16f9bc31b9
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/812-pcie-0017-PCI-mobiveil-Add-PCIe-Gen4-EP-driver-for-NXP-Layersc.patch
@@ -0,0 +1,217 @@
+From 9e1faafe9d650a06e212ad5a3b8ed0e7eb7f0aa2 Mon Sep 17 00:00:00 2001
+From: Xiaowei Bao <xiaowei.bao@nxp.com>
+Date: Sat, 5 Jan 2019 16:30:42 +0800
+Subject: [PATCH] PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape
+ SoCs
+
+This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
+mode if select this config opteration.
+
+Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
+[Zhiqiang: Correct the Copyright]
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+[drop maintainer change]
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/pci/controller/mobiveil/Kconfig            |  17 ++-
+ drivers/pci/controller/mobiveil/Makefile           |   1 +
+ .../controller/mobiveil/pcie-layerscape-gen4-ep.c  | 156 +++++++++++++++++++++
+ 3 files changed, 171 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
+
+--- a/drivers/pci/controller/mobiveil/Kconfig
++++ b/drivers/pci/controller/mobiveil/Kconfig
+@@ -27,13 +27,24 @@ config PCIE_MOBIVEIL_PLAT
+ 	  for address translation and it is a PCIe Gen4 IP.
+ 
+ config PCIE_LAYERSCAPE_GEN4
+-	bool "Freescale Layerscape PCIe Gen4 controller"
++	bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
+ 	depends on PCI
+ 	depends on OF && (ARM64 || ARCH_LAYERSCAPE)
+ 	depends on PCI_MSI_IRQ_DOMAIN
+ 	select PCIE_MOBIVEIL_HOST
+ 	help
+ 	  Say Y here if you want PCIe Gen4 controller support on
+-	  Layerscape SoCs. The PCIe controller can work in RC or
+-	  EP mode according to RCW[HOST_AGT_PEX] setting.
++	  Layerscape SoCs. And the PCIe controller work in RC mode
++	  by setting the RCW[HOST_AGT_PEX] to 0.
++
++config PCIE_LAYERSCAPE_GEN4_EP
++	bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
++	depends on PCI
++	depends on OF && (ARM64 || ARCH_LAYERSCAPE)
++	depends on PCI_ENDPOINT
++	select PCIE_MOBIVEIL_EP
++	help
++	  Say Y here if you want PCIe Gen4 controller support on
++	  Layerscape SoCs. And the PCIe controller work in EP mode
++	  by setting the RCW[HOST_AGT_PEX] to 1.
+ endmenu
+--- a/drivers/pci/controller/mobiveil/Makefile
++++ b/drivers/pci/controller/mobiveil/Makefile
+@@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie
+ obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
+ obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
+ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
++obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4_EP) += pcie-layerscape-gen4-ep.o
+--- /dev/null
++++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
+@@ -0,0 +1,156 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * PCIe controller EP driver for Freescale Layerscape SoCs
++ *
++ * Copyright 2019 NXP
++ *
++ * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/of_pci.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/resource.h>
++
++#include "pcie-mobiveil.h"
++
++#define PCIE_LX2_BAR_NUM	4
++
++#define to_ls_pcie_g4_ep(x)	dev_get_drvdata((x)->dev)
++
++struct ls_pcie_g4_ep {
++	struct mobiveil_pcie		*mv_pci;
++};
++
++static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
++	{ .compatible = "fsl,lx2160a-pcie-ep",},
++	{ },
++};
++
++static const struct pci_epc_features ls_pcie_g4_epc_features = {
++	.linkup_notifier = false,
++	.msi_capable = true,
++	.msix_capable = true,
++	.reserved_bar = (1 << BAR_4) | (1 << BAR_5),
++};
++
++static const struct pci_epc_features*
++ls_pcie_g4_ep_get_features(struct mobiveil_pcie_ep *ep)
++{
++	return &ls_pcie_g4_epc_features;
++}
++
++static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
++{
++	struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
++	int win_idx;
++	u8 bar;
++
++	ep->bar_num = PCIE_LX2_BAR_NUM;
++
++	for (bar = BAR_0; bar < ep->epc->max_functions * ep->bar_num; bar++)
++		mobiveil_pcie_ep_reset_bar(mv_pci, bar);
++
++	for (win_idx = 0; win_idx < ep->apio_wins; win_idx++)
++		mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
++}
++
++static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
++				   enum pci_epc_irq_type type,
++				   u16 interrupt_num)
++{
++	struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
++
++	switch (type) {
++	case PCI_EPC_IRQ_LEGACY:
++		return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
++	case PCI_EPC_IRQ_MSI:
++		return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
++						      interrupt_num);
++	case PCI_EPC_IRQ_MSIX:
++		return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
++						       interrupt_num);
++	default:
++		dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
++	}
++
++	return 0;
++}
++
++static const struct mobiveil_pcie_ep_ops pcie_ep_ops = {
++	.ep_init = ls_pcie_g4_ep_init,
++	.raise_irq = ls_pcie_g4_ep_raise_irq,
++	.get_features = ls_pcie_g4_ep_get_features,
++};
++
++static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_ep,
++					   struct platform_device *pdev)
++{
++	struct mobiveil_pcie *mv_pci = ls_ep->mv_pci;
++	struct device *dev = &pdev->dev;
++	struct mobiveil_pcie_ep *ep;
++	struct resource *res;
++	int ret;
++
++	ep = &mv_pci->ep;
++	ep->ops = &pcie_ep_ops;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
++	if (!res)
++		return -EINVAL;
++
++	ep->phys_base = res->start;
++	ep->addr_size = resource_size(res);
++
++	ret = mobiveil_pcie_ep_init(ep);
++	if (ret) {
++		dev_err(dev, "failed to initialize layerscape endpoint\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mobiveil_pcie *mv_pci;
++	struct ls_pcie_g4_ep *ls_ep;
++	struct resource *res;
++	int ret;
++
++	ls_ep = devm_kzalloc(dev, sizeof(*ls_ep), GFP_KERNEL);
++	if (!ls_ep)
++		return -ENOMEM;
++
++	mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
++	if (!mv_pci)
++		return -ENOMEM;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
++	mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
++	if (IS_ERR(mv_pci->csr_axi_slave_base))
++		return PTR_ERR(mv_pci->csr_axi_slave_base);
++
++	mv_pci->pdev = pdev;
++	ls_ep->mv_pci = mv_pci;
++
++	platform_set_drvdata(pdev, ls_ep);
++
++	ret = ls_pcie_gen4_add_pcie_ep(ls_ep, pdev);
++
++	return ret;
++}
++
++static struct platform_driver ls_pcie_g4_ep_driver = {
++	.driver = {
++		.name = "layerscape-pcie-gen4-ep",
++		.of_match_table = ls_pcie_g4_ep_of_match,
++		.suppress_bind_attrs = true,
++	},
++};
++builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);