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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-07-20 09:13:04 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2013-07-20 09:13:04 +0000 |
| commit | a5ad1e9ad7718c8bbe26ea4881fa5ea85d35844e (patch) | |
| tree | 1d144717303710c5520187297f4ea379175aebde /target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch | |
| parent | 6f53d2b696681fccecdf631336edead0c1a202f9 (diff) | |
| download | upstream-a5ad1e9ad7718c8bbe26ea4881fa5ea85d35844e.tar.gz upstream-a5ad1e9ad7718c8bbe26ea4881fa5ea85d35844e.tar.bz2 upstream-a5ad1e9ad7718c8bbe26ea4881fa5ea85d35844e.zip | |
mpc85xx: remove 3.8 support
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37474 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch')
| -rw-r--r-- | target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch b/target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch deleted file mode 100644 index 3ca1bccec0..0000000000 --- a/target/linux/mpc85xx/patches-3.8/110-fix_mpc8548_cds.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/arch/powerpc/boot/dts/mpc8548cds_32b.dts -+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts -@@ -75,6 +75,9 @@ - ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; - }; - }; -+ chosen { -+ linux,stdout-path = "/soc8548@e0000000/serial@4600"; -+ }; - }; - - /* ---- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi -+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi -@@ -131,7 +131,24 @@ - - /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" --/include/ "pq3-duart-0.dtsi" -+ -+ serial0: serial@4600 { -+ cell-index = <1>; -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550"; -+ reg = <0x4600 0x100>; -+ clock-frequency = <0>; -+ interrupts = <42 2 0 0>; -+ }; -+ -+ serial1: serial@4500 { -+ cell-index = <0>; -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550"; -+ reg = <0x4500 0x100>; -+ clock-frequency = <0>; -+ interrupts = <42 2 0 0>; -+ }; - - L2: l2-cache-controller@20000 { - compatible = "fsl,mpc8548-l2-cache-controller"; |