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author | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2019-07-03 23:22:28 +0200 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2019-07-10 17:36:29 +0200 |
commit | 7196ca1d497b6f0727a285bc3ecd41d54aff3a81 (patch) | |
tree | 7d65052647e0dacca5f1c1259b1d8a7dae99d2fd /target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi | |
parent | 48047b3a5c6aa9fff89a7a9c7ec76d8335b1a8e7 (diff) | |
download | upstream-7196ca1d497b6f0727a285bc3ecd41d54aff3a81.tar.gz upstream-7196ca1d497b6f0727a285bc3ecd41d54aff3a81.tar.bz2 upstream-7196ca1d497b6f0727a285bc3ecd41d54aff3a81.zip |
ramips/mt7621: Name DTS files based on scheme
As introduced with ath79, DTS files for ramips will now be labelled
soc_vendor_device.dts(i). With this change, DTS files can be
selected automatically without further manual links.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi')
-rw-r--r-- | target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi b/target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi new file mode 100644 index 0000000000..1d54713fe6 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_ubiquiti_edgerouterx.dtsi @@ -0,0 +1,115 @@ +#include "mt7621.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "ubiquiti,edgerouterx", "mediatek,mt7621-soc"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x22>; +}; + +&nand { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x80000 0x60000>; + read-only; + }; + + factory: partition@e0000 { + label = "factory"; + reg = <0xe0000 0x60000>; + }; + + partition@140000 { + label = "kernel1"; + reg = <0x140000 0x300000>; + }; + + partition@440000 { + label = "kernel2"; + reg = <0x440000 0x300000>; + }; + + partition@740000 { + label = "ubi"; + reg = <0x740000 0xf7c0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag"; + ralink,function = "gpio"; + }; + }; +}; + +&spi0 { + /* + * This board has 2Mb spi flash soldered in and visible + * from manufacturer's firmware. + * But this SoC shares spi and nand pins, + * and current driver doesn't handle this sharing well + */ + status = "disabled"; + + m25p80@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi"; + reg = <0x0 0x200000>; + read-only; + }; + }; + }; +}; + +&xhci { + status = "disabled"; +}; |