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| author | Michael Lee <igvtee@gmail.com> | 2016-01-07 21:50:24 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-06-20 11:45:44 +0200 |
| commit | 60ccfbbad04a23aa5d464b472df462a55cd2bb74 (patch) | |
| tree | 87b2bf840238e610fdf2d0802b3cc1ab94dd172e /target/linux/ramips/patches-4.4/0103-MIPS-OWRTDTB.patch | |
| parent | 66ffd0ddf9d06a5a72ca72ed19636d20eab95c64 (diff) | |
| download | upstream-60ccfbbad04a23aa5d464b472df462a55cd2bb74.tar.gz upstream-60ccfbbad04a23aa5d464b472df462a55cd2bb74.tar.bz2 upstream-60ccfbbad04a23aa5d464b472df462a55cd2bb74.zip | |
ramips: update i2c drivers
* add rt_i2c structure to store driver data
* rewrite read/write check function and add i2c error status check.
so we don't need to wait until time out.
* add 10 bits address support. according to the data sheet i think
it is possible. but i haven't verify it.
* the most important is start transfer only need once. otherwise
it cause I2C_STARTERR status.
* add set i2c clock speed register by dts options "clock-frequency".
not just hard code it.
* add mt7621 i2c driver. i just copy i2c-ralink.c and change register
names. and the hardware don't support error status. so i remove it.
but the logic is the same.
Signed-off-by: Michael Lee <igvtee@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0103-MIPS-OWRTDTB.patch')
0 files changed, 0 insertions, 0 deletions