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author | Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> | 2021-02-27 15:12:21 -0800 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2021-03-05 23:55:51 +0000 |
commit | b4aad29a1d7ad77d67073c1c54b28c429c64ed9b (patch) | |
tree | 54d0b355b70f9dc5c7486940954d75f3d5cb3fa0 /target/linux/ramips/patches-5.10/321-mt7621-timer.patch | |
parent | 38ba1f9b4ca4d263489a50cf078fd3c374bc4042 (diff) | |
download | upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.tar.gz upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.tar.bz2 upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.zip |
ramips: add support for kernel 5.10
Enable testing kernel.
Delete upstreamed patches:
0098-disable_cm.patch can be dropped, upstream fixed CM handling.
Fix compile errors by using new kernel APIs.
Fix fuzz by manually editing patches to ensure the code goes in the
right place.
For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit
a307593a6 to keep the OpenWrt ralink driver operational.
Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693
and #3952.
Rename patches to follow the 3-digit classification from the OpenWrt
Developer Guide.
Run automatic quilt refresh.
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-5.10/321-mt7621-timer.patch')
-rw-r--r-- | target/linux/ramips/patches-5.10/321-mt7621-timer.patch | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch new file mode 100644 index 0000000000..91e14ad63b --- /dev/null +++ b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch @@ -0,0 +1,87 @@ +--- a/arch/mips/ralink/mt7621.c ++++ b/arch/mips/ralink/mt7621.c +@@ -9,6 +9,7 @@ + #include <linux/init.h> + #include <linux/slab.h> + #include <linux/sys_soc.h> ++#include <linux/jiffies.h> + + #include <asm/mipsregs.h> + #include <asm/smp-ops.h> +@@ -16,6 +17,7 @@ + #include <asm/mach-ralink/ralink_regs.h> + #include <asm/mach-ralink/mt7621.h> + #include <asm/mips-boards/launch.h> ++#include <asm/delay.h> + + #include <pinmux.h> + +@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core) + return true; + } + ++#define LPS_PREC 8 ++/* ++* Re-calibration lpj(loop-per-jiffy). ++* (derived from kernel/calibrate.c) ++*/ ++static int udelay_recal(void) ++{ ++ unsigned int i, lpj = 0; ++ unsigned long ticks, loopbit; ++ int lps_precision = LPS_PREC; ++ ++ lpj = (1<<12); ++ ++ while ((lpj <<= 1) != 0) { ++ /* wait for "start of" clock tick */ ++ ticks = jiffies; ++ while (ticks == jiffies) ++ /* nothing */; ++ ++ /* Go .. */ ++ ticks = jiffies; ++ __delay(lpj); ++ ticks = jiffies - ticks; ++ if (ticks) ++ break; ++ } ++ ++ /* ++ * Do a binary approximation to get lpj set to ++ * equal one clock (up to lps_precision bits) ++ */ ++ lpj >>= 1; ++ loopbit = lpj; ++ while (lps_precision-- && (loopbit >>= 1)) { ++ lpj |= loopbit; ++ ticks = jiffies; ++ while (ticks == jiffies) ++ /* nothing */; ++ ticks = jiffies; ++ __delay(lpj); ++ if (jiffies != ticks) /* longer than 1 tick */ ++ lpj &= ~loopbit; ++ } ++ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj); ++ ++ for(i=0; i< NR_CPUS; i++) ++ cpu_data[i].udelay_val = lpj; ++ ++ return 0; ++} ++device_initcall(udelay_recal); ++ + void prom_soc_init(struct ralink_soc_info *soc_info) + { + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); +--- a/arch/mips/ralink/Kconfig ++++ b/arch/mips/ralink/Kconfig +@@ -63,6 +63,7 @@ choice + select HAVE_PCI if PCI_MT7621 + select SOC_BUS + select WEAK_REORDERING_BEYOND_LLSC ++ select GENERIC_CLOCKEVENTS_BROADCAST + endchoice + + choice |