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| author | Birger Koblitz <git@birger-koblitz.de> | 2021-01-21 15:12:36 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-01-26 15:06:50 +0100 |
| commit | d140b9fc23f6b58ce6be696844e216c91e62b4c5 (patch) | |
| tree | 5230746fe92f45e0088fee52187b68fbb94aec55 /target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h | |
| parent | e1bca7c77d80b3f35f5045cd8983349819165f1e (diff) | |
| download | upstream-d140b9fc23f6b58ce6be696844e216c91e62b4c5.tar.gz upstream-d140b9fc23f6b58ce6be696844e216c91e62b4c5.tar.bz2 upstream-d140b9fc23f6b58ce6be696844e216c91e62b4c5.zip | |
realtek: add internal and external SDS/PHYs of RTL9300 devices
This adds support for the internal SerDes of the RTL9300 SoC
and for the RTL8218D and RTL8226B phys found in combination
with this SoC in switches.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Diffstat (limited to 'target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h')
| -rw-r--r-- | target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h index 7af35a3583..031ec8a0e9 100644 --- a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h +++ b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h @@ -28,13 +28,33 @@ struct __attribute__ ((__packed__)) fw_header { #define PHY_ID_RTL8214C 0x001cc942 #define PHY_ID_RTL8214FC 0x001cc981 #define PHY_ID_RTL8218B_E 0x001cc981 +#define PHY_ID_RTL8218D 0x001cc983 #define PHY_ID_RTL8218B_I 0x001cca40 +#define PHY_ID_RTL8226 0x001cc838 #define PHY_ID_RTL8390_GENERIC 0x001ccab0 #define PHY_ID_RTL8393_I 0x001c8393 +#define PHY_ID_RTL9300_I 0x70d03106 -#define RTL839X_SDS12_13_XSG0 (0xB800) +// PHY MMD devices +#define MMD_AN 7 +#define MMD_VEND2 31 +/* Registers of the internal Serdes of the 8380 */ #define RTL838X_SDS_MODE_SEL (0x0028) #define RTL838X_SDS_CFG_REG (0x0034) #define RTL838X_INT_MODE_CTRL (0x005c) #define RTL838X_DMY_REG31 (0x3b28) + +#define RTL8380_SDS4_FIB_REG0 (0xF800) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880) +#define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980) + +/* Registers of the internal SerDes of the RTL8390 */ +#define RTL839X_SDS12_13_XSG0 (0xB800) + +/* Registers of the internal Serdes of the 9300 */ +#define RTL930X_SDS_INDACS_CMD (0x03B0) +#define RTL930X_SDS_INDACS_DATA (0x03B4) |