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| author | Mathias Kresin <dev@kresin.me> | 2018-05-13 13:02:30 +0200 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2018-05-17 07:40:19 +0200 |
| commit | bc04cf780e95aa292695f064dfaeea08df8c9b84 (patch) | |
| tree | 422896a0aba094a990872a2d661433308f36caf2 /target | |
| parent | f7ec385c1381db731cd5f1d22fe31149ffcbbb5e (diff) | |
| download | upstream-bc04cf780e95aa292695f064dfaeea08df8c9b84.tar.gz upstream-bc04cf780e95aa292695f064dfaeea08df8c9b84.tar.bz2 upstream-bc04cf780e95aa292695f064dfaeea08df8c9b84.zip | |
ath79: ar724x: fix pll settings
Add the syscon compatible, otherwise used functions like
syscon_regmap_lookup_by_phandle() will return an error and setting the
ethernet pll data wont work at all.
Fix the pll register width. Writing to registers out of the range via
syscon isn't possible and returns an error. On ar7242 the last pll
register - Current Audio Modulation Logic Output - is at 0x1805003c.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ath79/dts/ar724x.dtsi | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target/linux/ath79/dts/ar724x.dtsi b/target/linux/ath79/dts/ar724x.dtsi index 4108745113..fe1b4eb681 100644 --- a/target/linux/ath79/dts/ar724x.dtsi +++ b/target/linux/ath79/dts/ar724x.dtsi @@ -65,9 +65,8 @@ }; pll: pll-controller@18050000 { - compatible = "qca,ar7240-pll", - "qca,ar7240-pll"; - reg = <0x18050000 0x20>; + compatible = "qca,ar7240-pll", "syscon"; + reg = <0x18050000 0x3c>; clock-names = "ref"; /* The board must provides the ref clock */ |