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authorTim Harvey <tharvey@gateworks.com>2018-02-15 08:34:35 -0800
committerJohn Crispin <john@phrozen.org>2018-02-19 09:32:43 +0100
commit3282e7189fb95af98db48f599cd6188455da8797 (patch)
tree8ea686d9c081f3023c6333d14f2feedc73a92651 /target
parentcc8921162f4b4073328b8b1c429b6f9c9774f554 (diff)
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kernel: backport dwc pci enumeration fix
Backport of: http://patchwork.ozlabs.org/patch/860701/ Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target')
-rw-r--r--target/linux/generic/pending-4.14/812-pci-dwc-fix-enumeration.patch62
1 files changed, 62 insertions, 0 deletions
diff --git a/target/linux/generic/pending-4.14/812-pci-dwc-fix-enumeration.patch b/target/linux/generic/pending-4.14/812-pci-dwc-fix-enumeration.patch
new file mode 100644
index 0000000000..42985efdc8
--- /dev/null
+++ b/target/linux/generic/pending-4.14/812-pci-dwc-fix-enumeration.patch
@@ -0,0 +1,62 @@
+From patchwork Tue Jan 9 14:42:21 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: PCI: dwc: fix enumeration end when reaching root subordinate
+From: Koen Vandeputte <koen.vandeputte@ncentric.com>
+X-Patchwork-Id: 10152443
+Message-Id: <1515508941-20055-1-git-send-email-koen.vandeputte@ncentric.com>
+To: linux-pci@vger.kernel.org
+Cc: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
+ Joao.Pinto@synopsys.com, jingoohan1@gmail.com, niklas.cassel@axis.com,
+ Koen Vandeputte <koen.vandeputte@ncentric.com>,
+ Mika Westerberg <mika.westerberg@linux.intel.com>
+Date: Tue, 9 Jan 2018 15:42:21 +0100
+
+The subordinate value indicates the highest bus number which can be
+reached downstream though a certain device.
+
+Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
+parent")
+ensures that downstream devices cannot assign busnumbers higher than the
+upstream device subordinate number, which was indeed illogical.
+
+By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
+value of 0x01.
+
+Due to this combined with above commit, enumeration stops digging deeper
+downstream as soon as bus num 0x01 has been assigned, which is always
+the case for a bridge device.
+
+This results in all devices behind a bridge bus to remain undetected, as
+these would be connected to bus 0x02 or higher.
+
+Fix this by initializing the RC to a subordinate value of 0xff, meaning
+that all busses [0x00-0xff] are reachable through this RC.
+
+Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
+parent")
+Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
+Tested-by: Niklas Cassel <niklas.cassel@axis.com>
+Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
+---
+
+Will send separate patches to stable as this file got moved/renamed
+
+
+ drivers/pci/dwc/pcie-designware-host.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
+index bf558df5b7b3..2b5470173196 100644
+--- a/drivers/pci/dwc/pcie-designware-host.c
++++ b/drivers/pci/dwc/pcie-designware-host.c
+@@ -616,7 +616,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
+ /* setup bus numbers */
+ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
+ val &= 0xff000000;
+- val |= 0x00010100;
++ val |= 0x00ff0100;
+ dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
+
+ /* setup command register */