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authorDavid Bauer <mail@david-bauer.net>2021-04-15 00:30:24 +0200
committerDavid Bauer <mail@david-bauer.net>2021-04-15 22:40:55 +0200
commitbbff6239e2ea273388f4ca0f8586945ff5f36271 (patch)
tree851ed25ff716f314c66635511dfdd2d5ab772787 /target
parent956407292dc5fd41f2d8c7cc7e9ec77eb6444c1e (diff)
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ath79: fix 10 Mbit PLL data for TP-Link EAP2xx
Fix the PLL register value for 10 Mbit/s link modes on TP-Link EAP boards using a AR8033 SGMII PHY. Otherwise, 10 Mbit/s links do not transfer data. Reported-by: Tom Herbers <freifunk@tomherbers.de> Tested-by: Tom Herbers <freifunk@tomherbers.de> Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi b/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi
index cc9e0b7ff6..a6aefc7b55 100644
--- a/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi
@@ -112,6 +112,7 @@
phy-handle = <&phy4>;
phy-mode = "sgmii";
+ pll-data = <0x03000000 0x00000101 0x00001313>;
mtd-mac-address = <&info 0x8>;