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authorJohn Crispin <john@phrozen.org>2017-03-23 09:18:42 +0100
committerJohn Crispin <john@phrozen.org>2017-03-23 09:18:42 +0100
commitdce3b0057b986ab3278392607433b862e2865416 (patch)
treed541992573fb3e40bac6e8a9919c7f8c5b741a74 /target
parent666bfc6fb554441f1940eba84e00be10487e2463 (diff)
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ramips: fix mt7621 boot on v4.9
v4.9 CM code has a few bugs on this HW. Disable the GCR register access during boot. This caused a cpu stall. Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/patches-4.9/0098-disable_cm.patch21
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.9/0098-disable_cm.patch b/target/linux/ramips/patches-4.9/0098-disable_cm.patch
new file mode 100644
index 0000000000..6ea4909851
--- /dev/null
+++ b/target/linux/ramips/patches-4.9/0098-disable_cm.patch
@@ -0,0 +1,21 @@
+Index: linux-4.9.14/arch/mips/kernel/mips-cm.c
+===================================================================
+--- linux-4.9.14.orig/arch/mips/kernel/mips-cm.c
++++ linux-4.9.14/arch/mips/kernel/mips-cm.c
+@@ -239,6 +239,7 @@ int mips_cm_probe(void)
+
+ /* disable CM regions */
+ write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
++ /*
+ write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+ write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+ write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+@@ -246,7 +247,7 @@ int mips_cm_probe(void)
+ write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+ write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+ write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+-
++*/
+ /* probe for an L2-only sync region */
+ mips_cm_probe_l2sync();
+