diff options
Diffstat (limited to 'target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch b/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch new file mode 100644 index 0000000000..fa05b1970b --- /dev/null +++ b/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch @@ -0,0 +1,63 @@ +From 502af2ba683831fb4c05bd887374053d17376c87 Mon Sep 17 00:00:00 2001 +From: P33M <p33m@github.com> +Date: Fri, 21 Sep 2018 14:05:09 +0100 +Subject: [PATCH 420/454] dwc_otg: fiq_fsm: fix incorrect DMA register offset + calculation + +Rationalise the offset and update all call sites. + +Fixes https://github.com/raspberrypi/linux/issues/2408 +--- + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 8 ++++---- + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 +- + 2 files changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +@@ -250,7 +250,7 @@ static int notrace fiq_increment_dma_buf + BUG(); + + hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; +- FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32); + st->channel[n].dma_info.index = i; + return 0; + } +@@ -302,7 +302,7 @@ static int notrace fiq_iso_out_advance(s + + /* New DMA address - address of bounce buffer referred to in index */ + hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; +- //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); ++ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA); + //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; + fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); + fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); +@@ -317,7 +317,7 @@ static int notrace fiq_iso_out_advance(s + st->channel[n].dma_info.index++; + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); +- FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32); + return last; + } + +@@ -564,7 +564,7 @@ static int notrace noinline fiq_fsm_upda + + /* grab the next DMA address offset from the array */ + hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; +- FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32); + + /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as + * the core needs to be told to send the correct number. Caution: for IN transfers, +--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +@@ -94,7 +94,7 @@ do { \ + #define HC_START 0x500 + #define HC_OFFSET 0x020 + +-#define HC_DMA 0x514 ++#define HC_DMA 0x14 + + #define HCCHAR 0x00 + #define HCSPLT 0x04 |