diff options
Diffstat (limited to 'target/linux/generic/patches-4.1/090-m25p80_spi-nor_update_to_4.4rc1.patch')
| -rw-r--r-- | target/linux/generic/patches-4.1/090-m25p80_spi-nor_update_to_4.4rc1.patch | 1129 |
1 files changed, 0 insertions, 1129 deletions
diff --git a/target/linux/generic/patches-4.1/090-m25p80_spi-nor_update_to_4.4rc1.patch b/target/linux/generic/patches-4.1/090-m25p80_spi-nor_update_to_4.4rc1.patch deleted file mode 100644 index b640706587..0000000000 --- a/target/linux/generic/patches-4.1/090-m25p80_spi-nor_update_to_4.4rc1.patch +++ /dev/null @@ -1,1129 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -31,7 +31,6 @@ - struct m25p { - struct spi_device *spi; - struct spi_nor spi_nor; -- struct mtd_info mtd; - u8 command[MAX_CMD_SIZE]; - }; - -@@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no - return 1 + nor->addr_width; - } - --static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len, -- int wr_en) -+static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) - { - struct m25p *flash = nor->priv; - struct spi_device *spi = flash->spi; -@@ -159,7 +157,7 @@ static int m25p80_erase(struct spi_nor * - struct m25p *flash = nor->priv; - - dev_dbg(nor->dev, "%dKiB at 0x%08x\n", -- flash->mtd.erasesize / 1024, (u32)offset); -+ flash->spi_nor.mtd.erasesize / 1024, (u32)offset); - - /* Set up command buffer. */ - flash->command[0] = nor->erase_opcode; -@@ -201,11 +199,10 @@ static int m25p_probe(struct spi_device - nor->read_reg = m25p80_read_reg; - - nor->dev = &spi->dev; -- nor->mtd = &flash->mtd; -+ nor->flash_node = spi->dev.of_node; - nor->priv = flash; - - spi_set_drvdata(spi, flash); -- flash->mtd.priv = nor; - flash->spi = spi; - - if (spi->mode & SPI_RX_QUAD) -@@ -214,7 +211,7 @@ static int m25p_probe(struct spi_device - mode = SPI_NOR_DUAL; - - if (data && data->name) -- flash->mtd.name = data->name; -+ nor->mtd.name = data->name; - - /* For some (historical?) reason many platforms provide two different - * names in flash_platform_data: "name" and "type". Quite often name is -@@ -223,8 +220,6 @@ static int m25p_probe(struct spi_device - */ - if (data && data->type) - flash_name = data->type; -- else if (!strcmp(spi->modalias, "spi-nor")) -- flash_name = NULL; /* auto-detect */ - else - flash_name = spi->modalias; - -@@ -234,7 +229,7 @@ static int m25p_probe(struct spi_device - - ppdata.of_node = spi->dev.of_node; - -- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, -+ return mtd_device_parse_register(&nor->mtd, NULL, &ppdata, - data ? data->parts : NULL, - data ? data->nr_parts : 0); - } -@@ -245,7 +240,7 @@ static int m25p_remove(struct spi_device - struct m25p *flash = spi_get_drvdata(spi); - - /* Clean up MTD stuff. */ -- return mtd_device_unregister(&flash->mtd); -+ return mtd_device_unregister(&flash->spi_nor.mtd); - } - - /* -@@ -261,59 +256,52 @@ static int m25p_remove(struct spi_device - * keep them available as module aliases for existing platforms. - */ - static const struct spi_device_id m25p_ids[] = { -- {"at25fs010"}, {"at25fs040"}, {"at25df041a"}, {"at25df321a"}, -- {"at25df641"}, {"at26f004"}, {"at26df081a"}, {"at26df161a"}, -- {"at26df321"}, {"at45db081d"}, -- {"en25f32"}, {"en25p32"}, {"en25q32b"}, {"en25p64"}, -- {"en25q64"}, {"en25qh128"}, {"en25qh256"}, -- {"f25l32pa"}, -- {"mr25h256"}, {"mr25h10"}, -- {"gd25q32"}, {"gd25q64"}, -- {"160s33b"}, {"320s33b"}, {"640s33b"}, -- {"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"}, -- {"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"}, -- {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"}, -- {"mx66l1g55g"}, -- {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"}, -- {"n25q512a"}, {"n25q512ax3"}, {"n25q00"}, -- {"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"}, -- {"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"}, -- {"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"}, -- {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"}, -- {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"}, -- {"s25fl016k"}, {"s25fl064k"}, {"s25fl132k"}, -- {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"}, -- {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"}, -- {"sst25wf040"}, -- {"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"}, -- {"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"}, -- {"m25p128"}, {"n25q032"}, -+ /* -+ * Entries not used in DTs that should be safe to drop after replacing -+ * them with "nor-jedec" in platform data. -+ */ -+ {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, -+ -+ /* -+ * Entries that were used in DTs without "nor-jedec" fallback and should -+ * be kept for backward compatibility. -+ */ -+ {"at25df321a"}, {"at25df641"}, {"at26df081a"}, -+ {"mr25h256"}, -+ {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, -+ {"mx25l25635e"},{"mx66l51235l"}, -+ {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, -+ {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, -+ {"s25fl064k"}, -+ {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, -+ {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, -+ {"m25p64"}, {"m25p128"}, -+ {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, -+ {"w25q80bl"}, {"w25q128"}, {"w25q256"}, -+ -+ /* Flashes that can't be detected using JEDEC */ - {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, - {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, - {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, -- {"m45pe10"}, {"m45pe80"}, {"m45pe16"}, -- {"m25pe20"}, {"m25pe80"}, {"m25pe16"}, -- {"m25px16"}, {"m25px32"}, {"m25px32-s0"}, {"m25px32-s1"}, -- {"m25px64"}, {"m25px80"}, -- {"w25x10"}, {"w25x20"}, {"w25x40"}, {"w25x80"}, -- {"w25x16"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, -- {"w25x64"}, {"w25q64"}, {"w25q80"}, {"w25q80bl"}, -- {"w25q128"}, {"w25q256"}, {"cat25c11"}, -- {"cat25c03"}, {"cat25c09"}, {"cat25c17"}, {"cat25128"}, - -- /* -- * Generic support for SPI NOR that can be identified by the JEDEC READ -- * ID opcode (0x9F). Use this, if possible. -- */ -- {"spi-nor"}, - { }, - }; - MODULE_DEVICE_TABLE(spi, m25p_ids); - -+static const struct of_device_id m25p_of_table[] = { -+ /* -+ * Generic compatibility for SPI NOR that can be identified by the -+ * JEDEC READ ID opcode (0x9F). Use this, if possible. -+ */ -+ { .compatible = "jedec,spi-nor" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, m25p_of_table); -+ - static struct spi_driver m25p80_driver = { - .driver = { - .name = "m25p80", -- .owner = THIS_MODULE, -+ .of_match_table = m25p_of_table, - }, - .id_table = m25p_ids, - .probe = m25p_probe, ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -16,19 +16,32 @@ - #include <linux/device.h> - #include <linux/mutex.h> - #include <linux/math64.h> -+#include <linux/sizes.h> - --#include <linux/mtd/cfi.h> - #include <linux/mtd/mtd.h> - #include <linux/of_platform.h> - #include <linux/spi/flash.h> - #include <linux/mtd/spi-nor.h> - - /* Define max times to check status register before we give up. */ --#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ -+ -+/* -+ * For everything but full-chip erase; probably could be much smaller, but kept -+ * around for safety for now -+ */ -+#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) -+ -+/* -+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up -+ * for larger flash -+ */ -+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) - - #define SPI_NOR_MAX_ID_LEN 6 - - struct flash_info { -+ char *name; -+ - /* - * This array stores the ID bytes. - * The first three bytes are the JEDIC ID. -@@ -59,7 +72,7 @@ struct flash_info { - - #define JEDEC_MFR(info) ((info)->id[0]) - --static const struct spi_device_id *spi_nor_match_id(const char *name); -+static const struct flash_info *spi_nor_match_id(const char *name); - - /* - * Read the status register, returning its value in the location -@@ -143,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc - static inline int write_sr(struct spi_nor *nor, u8 val) - { - nor->cmd_buf[0] = val; -- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); -+ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); - } - - /* -@@ -152,7 +165,7 @@ static inline int write_sr(struct spi_no - */ - static inline int write_enable(struct spi_nor *nor) - { -- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); -+ return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); - } - - /* -@@ -160,7 +173,7 @@ static inline int write_enable(struct sp - */ - static inline int write_disable(struct spi_nor *nor) - { -- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); -+ return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); - } - - static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) -@@ -169,7 +182,7 @@ static inline struct spi_nor *mtd_to_spi - } - - /* Enable/disable 4-byte addressing mode. */ --static inline int set_4byte(struct spi_nor *nor, struct flash_info *info, -+static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, - int enable) - { - int status; -@@ -177,16 +190,16 @@ static inline int set_4byte(struct spi_n - u8 cmd; - - switch (JEDEC_MFR(info)) { -- case CFI_MFR_ST: /* Micron, actually */ -+ case SNOR_MFR_MICRON: - /* Some Micron need WREN command; all will accept it */ - need_wren = true; -- case CFI_MFR_MACRONIX: -- case 0xEF /* winbond */: -+ case SNOR_MFR_MACRONIX: -+ case SNOR_MFR_WINBOND: - if (need_wren) - write_enable(nor); - - cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; -- status = nor->write_reg(nor, cmd, NULL, 0, 0); -+ status = nor->write_reg(nor, cmd, NULL, 0); - if (need_wren) - write_disable(nor); - -@@ -194,7 +207,7 @@ static inline int set_4byte(struct spi_n - default: - /* Spansion style */ - nor->cmd_buf[0] = enable << 7; -- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); -+ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); - } - } - static inline int spi_nor_sr_ready(struct spi_nor *nor) -@@ -231,12 +244,13 @@ static int spi_nor_ready(struct spi_nor - * Service routine to read status register until ready, or timeout occurs. - * Returns non-zero if error. - */ --static int spi_nor_wait_till_ready(struct spi_nor *nor) -+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, -+ unsigned long timeout_jiffies) - { - unsigned long deadline; - int timeout = 0, ret; - -- deadline = jiffies + MAX_READY_WAIT_JIFFIES; -+ deadline = jiffies + timeout_jiffies; - - while (!timeout) { - if (time_after_eq(jiffies, deadline)) -@@ -256,6 +270,12 @@ static int spi_nor_wait_till_ready(struc - return -ETIMEDOUT; - } - -+static int spi_nor_wait_till_ready(struct spi_nor *nor) -+{ -+ return spi_nor_wait_till_ready_with_timeout(nor, -+ DEFAULT_READY_WAIT_JIFFIES); -+} -+ - /* - * Erase the whole flash memory - * -@@ -263,9 +283,9 @@ static int spi_nor_wait_till_ready(struc - */ - static int erase_chip(struct spi_nor *nor) - { -- dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10)); -+ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); - -- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); -+ return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); - } - - static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) -@@ -319,6 +339,8 @@ static int spi_nor_erase(struct mtd_info - - /* whole-chip erase? */ - if (len == mtd->size) { -+ unsigned long timeout; -+ - write_enable(nor); - - if (erase_chip(nor)) { -@@ -326,7 +348,16 @@ static int spi_nor_erase(struct mtd_info - goto erase_err; - } - -- ret = spi_nor_wait_till_ready(nor); -+ /* -+ * Scale the timeout linearly with the size of the flash, with -+ * a minimum calibrated to an old 2MB flash. We could try to -+ * pull these from CFI/SFDP, but these values should be good -+ * enough for now. -+ */ -+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, -+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES * -+ (unsigned long)(mtd->size / SZ_2M)); -+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); - if (ret) - goto erase_err; - -@@ -369,72 +400,171 @@ erase_err: - return ret; - } - -+static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, -+ uint64_t *len) -+{ -+ struct mtd_info *mtd = &nor->mtd; -+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0; -+ int shift = ffs(mask) - 1; -+ int pow; -+ -+ if (!(sr & mask)) { -+ /* No protection */ -+ *ofs = 0; -+ *len = 0; -+ } else { -+ pow = ((sr & mask) ^ mask) >> shift; -+ *len = mtd->size >> pow; -+ *ofs = mtd->size - *len; -+ } -+} -+ -+/* -+ * Return 1 if the entire region is locked, 0 otherwise -+ */ -+static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr) -+{ -+ loff_t lock_offs; -+ uint64_t lock_len; -+ -+ stm_get_locked_range(nor, sr, &lock_offs, &lock_len); -+ -+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); -+} -+ -+/* -+ * Lock a region of the flash. Compatible with ST Micro and similar flash. -+ * Supports only the block protection bits BP{0,1,2} in the status register -+ * (SR). Does not support these features found in newer SR bitfields: -+ * - TB: top/bottom protect - only handle TB=0 (top protect) -+ * - SEC: sector/block protect - only handle SEC=0 (block protect) -+ * - CMP: complement protect - only support CMP=0 (range is not complemented) -+ * -+ * Sample table portion for 8MB flash (Winbond w25q64fw): -+ * -+ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion -+ * -------------------------------------------------------------------------- -+ * X | X | 0 | 0 | 0 | NONE | NONE -+ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 -+ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 -+ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 -+ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 -+ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 -+ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 -+ * X | X | 1 | 1 | 1 | 8 MB | ALL -+ * -+ * Returns negative on errors, 0 on success. -+ */ - static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { -- struct mtd_info *mtd = nor->mtd; -- uint32_t offset = ofs; -- uint8_t status_old, status_new; -- int ret = 0; -+ struct mtd_info *mtd = &nor->mtd; -+ u8 status_old, status_new; -+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0; -+ u8 shift = ffs(mask) - 1, pow, val; - - status_old = read_sr(nor); - -- if (offset < mtd->size - (mtd->size / 2)) -- status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; -- else if (offset < mtd->size - (mtd->size / 4)) -- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; -- else if (offset < mtd->size - (mtd->size / 8)) -- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; -- else if (offset < mtd->size - (mtd->size / 16)) -- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; -- else if (offset < mtd->size - (mtd->size / 32)) -- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; -- else if (offset < mtd->size - (mtd->size / 64)) -- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; -- else -- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; -+ /* SPI NOR always locks to the end */ -+ if (ofs + len != mtd->size) { -+ /* Does combined region extend to end? */ -+ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len, -+ status_old)) -+ return -EINVAL; -+ len = mtd->size - ofs; -+ } -+ -+ /* -+ * Need smallest pow such that: -+ * -+ * 1 / (2^pow) <= (len / size) -+ * -+ * so (assuming power-of-2 size) we do: -+ * -+ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) -+ */ -+ pow = ilog2(mtd->size) - ilog2(len); -+ val = mask - (pow << shift); -+ if (val & ~mask) -+ return -EINVAL; -+ /* Don't "lock" with no region! */ -+ if (!(val & mask)) -+ return -EINVAL; -+ -+ status_new = (status_old & ~mask) | val; - - /* Only modify protection if it will not unlock other areas */ -- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) > -- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { -- write_enable(nor); -- ret = write_sr(nor, status_new); -- } -+ if ((status_new & mask) <= (status_old & mask)) -+ return -EINVAL; - -- return ret; -+ write_enable(nor); -+ return write_sr(nor, status_new); - } - -+/* -+ * Unlock a region of the flash. See stm_lock() for more info -+ * -+ * Returns negative on errors, 0 on success. -+ */ - static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { -- struct mtd_info *mtd = nor->mtd; -- uint32_t offset = ofs; -+ struct mtd_info *mtd = &nor->mtd; - uint8_t status_old, status_new; -- int ret = 0; -+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0; -+ u8 shift = ffs(mask) - 1, pow, val; - - status_old = read_sr(nor); - -- if (offset+len > mtd->size - (mtd->size / 64)) -- status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0); -- else if (offset+len > mtd->size - (mtd->size / 32)) -- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; -- else if (offset+len > mtd->size - (mtd->size / 16)) -- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; -- else if (offset+len > mtd->size - (mtd->size / 8)) -- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; -- else if (offset+len > mtd->size - (mtd->size / 4)) -- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; -- else if (offset+len > mtd->size - (mtd->size / 2)) -- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; -- else -- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; -+ /* Cannot unlock; would unlock larger region than requested */ -+ if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize, -+ mtd->erasesize)) -+ return -EINVAL; - -- /* Only modify protection if it will not lock other areas */ -- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) < -- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { -- write_enable(nor); -- ret = write_sr(nor, status_new); -+ /* -+ * Need largest pow such that: -+ * -+ * 1 / (2^pow) >= (len / size) -+ * -+ * so (assuming power-of-2 size) we do: -+ * -+ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) -+ */ -+ pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len)); -+ if (ofs + len == mtd->size) { -+ val = 0; /* fully unlocked */ -+ } else { -+ val = mask - (pow << shift); -+ /* Some power-of-two sizes are not supported */ -+ if (val & ~mask) -+ return -EINVAL; - } - -- return ret; -+ status_new = (status_old & ~mask) | val; -+ -+ /* Only modify protection if it will not lock other areas */ -+ if ((status_new & mask) >= (status_old & mask)) -+ return -EINVAL; -+ -+ write_enable(nor); -+ return write_sr(nor, status_new); -+} -+ -+/* -+ * Check if a region of the flash is (completely) locked. See stm_lock() for -+ * more info. -+ * -+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and -+ * negative on errors. -+ */ -+static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) -+{ -+ int status; -+ -+ status = read_sr(nor); -+ if (status < 0) -+ return status; -+ -+ return stm_is_locked_sr(nor, ofs, len, status); - } - - static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) -@@ -467,9 +597,23 @@ static int spi_nor_unlock(struct mtd_inf - return ret; - } - -+static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) -+{ -+ struct spi_nor *nor = mtd_to_spi_nor(mtd); -+ int ret; -+ -+ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); -+ if (ret) -+ return ret; -+ -+ ret = nor->flash_is_locked(nor, ofs, len); -+ -+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); -+ return ret; -+} -+ - /* Used when the "_ext_id" is two bytes at most */ - #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ -- ((kernel_ulong_t)&(struct flash_info) { \ - .id = { \ - ((_jedec_id) >> 16) & 0xff, \ - ((_jedec_id) >> 8) & 0xff, \ -@@ -481,11 +625,9 @@ static int spi_nor_unlock(struct mtd_inf - .sector_size = (_sector_size), \ - .n_sectors = (_n_sectors), \ - .page_size = 256, \ -- .flags = (_flags), \ -- }) -+ .flags = (_flags), - - #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ -- ((kernel_ulong_t)&(struct flash_info) { \ - .id = { \ - ((_jedec_id) >> 16) & 0xff, \ - ((_jedec_id) >> 8) & 0xff, \ -@@ -498,23 +640,27 @@ static int spi_nor_unlock(struct mtd_inf - .sector_size = (_sector_size), \ - .n_sectors = (_n_sectors), \ - .page_size = 256, \ -- .flags = (_flags), \ -- }) -+ .flags = (_flags), - - #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ -- ((kernel_ulong_t)&(struct flash_info) { \ - .sector_size = (_sector_size), \ - .n_sectors = (_n_sectors), \ - .page_size = (_page_size), \ - .addr_width = (_addr_width), \ -- .flags = (_flags), \ -- }) -+ .flags = (_flags), - - /* NOTE: double check command sets and memory organization when you add - * more nor chips. This current list focusses on newer chips, which - * have been converging on command sets which including JEDEC ID. -+ * -+ * All newly added entries should describe *hardware* and should use SECT_4K -+ * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage -+ * scenarios excluding small sectors there is config option that can be -+ * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. -+ * For historical (and compatibility) reasons (before we got above config) some -+ * old entries may be missing 4K flag. - */ --static const struct spi_device_id spi_nor_ids[] = { -+static const struct flash_info spi_nor_ids[] = { - /* Atmel -- some are (confusingly) marketed as "DataFlash" */ - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, -@@ -538,7 +684,7 @@ static const struct spi_device_id spi_no - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, - { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, - { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, -- { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, 0) }, -+ { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, - - /* ESMT */ - { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, -@@ -560,7 +706,11 @@ static const struct spi_device_id spi_no - { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, - -+ /* ISSI */ -+ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, -+ - /* Macronix */ -+ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, -@@ -578,7 +728,9 @@ static const struct spi_device_id spi_no - - /* Micron */ - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, -- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) }, -+ { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, -+ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, -+ { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, -@@ -595,25 +747,28 @@ static const struct spi_device_id spi_no - * for the chips listed here (without boot sectors). - */ - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, -+ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, -- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, -- { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, -- { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, -+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, -+ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, - { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, - { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, - { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, - { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, -- { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, -- { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, -+ { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -- { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, -+ { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, -+ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, - - /* SST -- large erase sizes are "overlays", "sectors" are 4K */ - { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, -@@ -624,6 +779,8 @@ static const struct spi_device_id spi_no - { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, - { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, - { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, -+ { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, -+ { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, - { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, - { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, - -@@ -672,10 +829,11 @@ static const struct spi_device_id spi_no - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, -- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, -+ { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -- { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, -@@ -690,11 +848,11 @@ static const struct spi_device_id spi_no - { }, - }; - --static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) -+static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) - { - int tmp; - u8 id[SPI_NOR_MAX_ID_LEN]; -- struct flash_info *info; -+ const struct flash_info *info; - - tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); - if (tmp < 0) { -@@ -703,7 +861,7 @@ static const struct spi_device_id *spi_n - } - - for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { -- info = (void *)spi_nor_ids[tmp].driver_data; -+ info = &spi_nor_ids[tmp]; - if (info->id_len) { - if (!memcmp(info->id, id, info->id_len)) - return &spi_nor_ids[tmp]; -@@ -857,8 +1015,7 @@ static int macronix_quad_enable(struct s - val = read_sr(nor); - write_enable(nor); - -- nor->cmd_buf[0] = val | SR_QUAD_EN_MX; -- nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); -+ write_sr(nor, val | SR_QUAD_EN_MX); - - if (spi_nor_wait_till_ready(nor)) - return 1; -@@ -883,7 +1040,7 @@ static int write_sr_cr(struct spi_nor *n - nor->cmd_buf[0] = val & 0xff; - nor->cmd_buf[1] = (val >> 8); - -- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); -+ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); - } - - static int spansion_quad_enable(struct spi_nor *nor) -@@ -925,7 +1082,7 @@ static int micron_quad_enable(struct spi - - /* set EVCR, enable quad I/O */ - nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON; -- ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0); -+ ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1); - if (ret < 0) { - dev_err(nor->dev, "error while writing EVCR register\n"); - return ret; -@@ -949,19 +1106,19 @@ static int micron_quad_enable(struct spi - return 0; - } - --static int set_quad_mode(struct spi_nor *nor, struct flash_info *info) -+static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) - { - int status; - - switch (JEDEC_MFR(info)) { -- case CFI_MFR_MACRONIX: -+ case SNOR_MFR_MACRONIX: - status = macronix_quad_enable(nor); - if (status) { - dev_err(nor->dev, "Macronix quad-read not enabled\n"); - return -EINVAL; - } - return status; -- case CFI_MFR_ST: -+ case SNOR_MFR_MICRON: - status = micron_quad_enable(nor); - if (status) { - dev_err(nor->dev, "Micron quad-read not enabled\n"); -@@ -991,11 +1148,10 @@ static int spi_nor_check(struct spi_nor - - int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) - { -- const struct spi_device_id *id = NULL; -- struct flash_info *info; -+ const struct flash_info *info = NULL; - struct device *dev = nor->dev; -- struct mtd_info *mtd = nor->mtd; -- struct device_node *np = dev->of_node; -+ struct mtd_info *mtd = &nor->mtd; -+ struct device_node *np = nor->flash_node; - int ret; - int i; - -@@ -1003,27 +1159,25 @@ int spi_nor_scan(struct spi_nor *nor, co - if (ret) - return ret; - -- /* Try to auto-detect if chip name wasn't specified */ -- if (!name) -- id = spi_nor_read_id(nor); -- else -- id = spi_nor_match_id(name); -- if (IS_ERR_OR_NULL(id)) -+ if (name) -+ info = spi_nor_match_id(name); -+ /* Try to auto-detect if chip name wasn't specified or not found */ -+ if (!info) -+ info = spi_nor_read_id(nor); -+ if (IS_ERR_OR_NULL(info)) - return -ENOENT; - -- info = (void *)id->driver_data; -- - /* - * If caller has specified name of flash model that can normally be - * detected using JEDEC, let's verify it. - */ - if (name && info->id_len) { -- const struct spi_device_id *jid; -+ const struct flash_info *jinfo; - -- jid = spi_nor_read_id(nor); -- if (IS_ERR(jid)) { -- return PTR_ERR(jid); -- } else if (jid != id) { -+ jinfo = spi_nor_read_id(nor); -+ if (IS_ERR(jinfo)) { -+ return PTR_ERR(jinfo); -+ } else if (jinfo != info) { - /* - * JEDEC knows better, so overwrite platform ID. We - * can't trust partitions any longer, but we'll let -@@ -1032,28 +1186,29 @@ int spi_nor_scan(struct spi_nor *nor, co - * information, even if it's not 100% accurate. - */ - dev_warn(dev, "found %s, expected %s\n", -- jid->name, id->name); -- id = jid; -- info = (void *)jid->driver_data; -+ jinfo->name, info->name); -+ info = jinfo; - } - } - - mutex_init(&nor->lock); - - /* -- * Atmel, SST and Intel/Numonyx serial nor tend to power -- * up with the software protection bits set -+ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up -+ * with the software protection bits set - */ - -- if (JEDEC_MFR(info) == CFI_MFR_ATMEL || -- JEDEC_MFR(info) == CFI_MFR_INTEL || -- JEDEC_MFR(info) == CFI_MFR_SST) { -+ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || -+ JEDEC_MFR(info) == SNOR_MFR_INTEL || -+ JEDEC_MFR(info) == SNOR_MFR_SST || -+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) { - write_enable(nor); - write_sr(nor, 0); - } - - if (!mtd->name) - mtd->name = dev_name(dev); -+ mtd->priv = nor; - mtd->type = MTD_NORFLASH; - mtd->writesize = 1; - mtd->flags = MTD_CAP_NORFLASH; -@@ -1061,15 +1216,18 @@ int spi_nor_scan(struct spi_nor *nor, co - mtd->_erase = spi_nor_erase; - mtd->_read = spi_nor_read; - -- /* nor protection support for STmicro chips */ -- if (JEDEC_MFR(info) == CFI_MFR_ST) { -+ /* NOR protection support for STmicro/Micron chips and similar */ -+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON || -+ JEDEC_MFR(info) == SNOR_MFR_WINBOND) { - nor->flash_lock = stm_lock; - nor->flash_unlock = stm_unlock; -+ nor->flash_is_locked = stm_is_locked; - } - -- if (nor->flash_lock && nor->flash_unlock) { -+ if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { - mtd->_lock = spi_nor_lock; - mtd->_unlock = spi_nor_unlock; -+ mtd->_is_locked = spi_nor_is_locked; - } - - /* sst nor chips use AAI word program */ -@@ -1156,7 +1314,7 @@ int spi_nor_scan(struct spi_nor *nor, co - else if (mtd->size > 0x1000000) { - /* enable 4-byte addressing if the device exceeds 16MiB */ - nor->addr_width = 4; -- if (JEDEC_MFR(info) == CFI_MFR_AMD) { -+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { - /* Dedicated 4-byte command set */ - switch (nor->flash_read) { - case SPI_NOR_QUAD: -@@ -1184,7 +1342,7 @@ int spi_nor_scan(struct spi_nor *nor, co - - nor->read_dummy = spi_nor_read_dummy_cycles(nor); - -- dev_info(dev, "%s (%lld Kbytes)\n", id->name, -+ dev_info(dev, "%s (%lld Kbytes)\n", info->name, - (long long)mtd->size >> 10); - - dev_dbg(dev, -@@ -1207,11 +1365,11 @@ int spi_nor_scan(struct spi_nor *nor, co - } - EXPORT_SYMBOL_GPL(spi_nor_scan); - --static const struct spi_device_id *spi_nor_match_id(const char *name) -+static const struct flash_info *spi_nor_match_id(const char *name) - { -- const struct spi_device_id *id = spi_nor_ids; -+ const struct flash_info *id = spi_nor_ids; - -- while (id->name[0]) { -+ while (id->name) { - if (!strcmp(name, id->name)) - return id; - id++; ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -10,6 +10,23 @@ - #ifndef __LINUX_MTD_SPI_NOR_H - #define __LINUX_MTD_SPI_NOR_H - -+#include <linux/bitops.h> -+#include <linux/mtd/cfi.h> -+ -+/* -+ * Manufacturer IDs -+ * -+ * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. -+ * Sometimes these are the same as CFI IDs, but sometimes they aren't. -+ */ -+#define SNOR_MFR_ATMEL CFI_MFR_ATMEL -+#define SNOR_MFR_INTEL CFI_MFR_INTEL -+#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ -+#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX -+#define SNOR_MFR_SPANSION CFI_MFR_AMD -+#define SNOR_MFR_SST CFI_MFR_SST -+#define SNOR_MFR_WINBOND 0xef -+ - /* - * Note on opcode nomenclature: some opcodes have a format like - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number -@@ -61,24 +78,24 @@ - #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ - - /* Status Register bits. */ --#define SR_WIP 1 /* Write in progress */ --#define SR_WEL 2 /* Write enable latch */ -+#define SR_WIP BIT(0) /* Write in progress */ -+#define SR_WEL BIT(1) /* Write enable latch */ - /* meaning of other SR_* bits may differ between vendors */ --#define SR_BP0 4 /* Block protect 0 */ --#define SR_BP1 8 /* Block protect 1 */ --#define SR_BP2 0x10 /* Block protect 2 */ --#define SR_SRWD 0x80 /* SR write protect */ -+#define SR_BP0 BIT(2) /* Block protect 0 */ -+#define SR_BP1 BIT(3) /* Block protect 1 */ -+#define SR_BP2 BIT(4) /* Block protect 2 */ -+#define SR_SRWD BIT(7) /* SR write protect */ - --#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ -+#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ - - /* Enhanced Volatile Configuration Register bits */ --#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */ -+#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ - - /* Flag Status Register bits */ --#define FSR_READY 0x80 -+#define FSR_READY BIT(7) - - /* Configuration Register bits. */ --#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */ -+#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ - - enum read_mode { - SPI_NOR_NORMAL = 0, -@@ -87,33 +104,6 @@ enum read_mode { - SPI_NOR_QUAD, - }; - --/** -- * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer -- * @wren: command for "Write Enable", or 0x00 for not required -- * @cmd: command for operation -- * @cmd_pins: number of pins to send @cmd (1, 2, 4) -- * @addr: address for operation -- * @addr_pins: number of pins to send @addr (1, 2, 4) -- * @addr_width: number of address bytes -- * (3,4, or 0 for address not required) -- * @mode: mode data -- * @mode_pins: number of pins to send @mode (1, 2, 4) -- * @mode_cycles: number of mode cycles (0 for mode not required) -- * @dummy_cycles: number of dummy cycles (0 for dummy not required) -- */ --struct spi_nor_xfer_cfg { -- u8 wren; -- u8 cmd; -- u8 cmd_pins; -- u32 addr; -- u8 addr_pins; -- u8 addr_width; -- u8 mode; -- u8 mode_pins; -- u8 mode_cycles; -- u8 dummy_cycles; --}; -- - #define SPI_NOR_MAX_CMD_SIZE 8 - enum spi_nor_ops { - SPI_NOR_OPS_READ = 0, -@@ -127,11 +117,14 @@ enum spi_nor_option_flags { - SNOR_F_USE_FSR = BIT(0), - }; - -+struct mtd_info; -+ - /** - * struct spi_nor - Structure for defining a the SPI NOR layer - * @mtd: point to a mtd_info structure - * @lock: the lock for the read/write/erase/lock/unlock operations - * @dev: point to a spi device, or a spi nor controller device. -+ * @flash_node: point to a device node describing this flash instance. - * @page_size: the page size of the SPI NOR - * @addr_width: number of address bytes - * @erase_opcode: the opcode for erasing a sector -@@ -141,28 +134,28 @@ enum spi_nor_option_flags { - * @flash_read: the mode of the read - * @sst_write_second: used by the SST write operation - * @flags: flag options for the current SPI-NOR (SNOR_F_*) -- * @cfg: used by the read_xfer/write_xfer - * @cmd_buf: used by the write_reg - * @prepare: [OPTIONAL] do some preparations for the - * read/write/erase/lock/unlock operations - * @unprepare: [OPTIONAL] do some post work after the - * read/write/erase/lock/unlock operations -- * @read_xfer: [OPTIONAL] the read fundamental primitive -- * @write_xfer: [OPTIONAL] the writefundamental primitive - * @read_reg: [DRIVER-SPECIFIC] read out the register - * @write_reg: [DRIVER-SPECIFIC] write data to the register - * @read: [DRIVER-SPECIFIC] read data from the SPI NOR - * @write: [DRIVER-SPECIFIC] write data to the SPI NOR - * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR - * at the offset @offs -- * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR -- * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR -+ * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR -+ * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR -+ * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is -+ * completely locked - * @priv: the private data - */ - struct spi_nor { -- struct mtd_info *mtd; -+ struct mtd_info mtd; - struct mutex lock; - struct device *dev; -+ struct device_node *flash_node; - u32 page_size; - u8 addr_width; - u8 erase_opcode; -@@ -172,18 +165,12 @@ struct spi_nor { - enum read_mode flash_read; - bool sst_write_second; - u32 flags; -- struct spi_nor_xfer_cfg cfg; - u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; - - int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); - void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); -- int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, -- u8 *buf, size_t len); -- int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg, -- u8 *buf, size_t len); - int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); -- int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, -- int write_enable); -+ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); - - int (*read)(struct spi_nor *nor, loff_t from, - size_t len, size_t *retlen, u_char *read_buf); -@@ -193,6 +180,7 @@ struct spi_nor { - - int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); -+ int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); - - void *priv; - }; |