diff options
Diffstat (limited to 'target/linux/generic')
| -rw-r--r-- | target/linux/generic/patches-3.8/020-ssb_update.patch | 1127 | ||||
| -rw-r--r-- | target/linux/generic/patches-3.8/025-bcma_backport.patch | 416 | ||||
| -rw-r--r-- | target/linux/generic/patches-3.9/020-ssb_backport.patch | 62 | ||||
| -rw-r--r-- | target/linux/generic/patches-3.9/020-ssb_update.patch | 1075 | ||||
| -rw-r--r-- | target/linux/generic/patches-3.9/021-bcma_backport.patch | 140 | ||||
| -rw-r--r-- | target/linux/generic/patches-3.9/025-bcma_backport.patch | 329 |
6 files changed, 2795 insertions, 354 deletions
diff --git a/target/linux/generic/patches-3.8/020-ssb_update.patch b/target/linux/generic/patches-3.8/020-ssb_update.patch index e4d699370d..a1b4a1fef2 100644 --- a/target/linux/generic/patches-3.8/020-ssb_update.patch +++ b/target/linux/generic/patches-3.8/020-ssb_update.patch @@ -22,6 +22,156 @@ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o +--- a/drivers/ssb/driver_chipcommon.c ++++ b/drivers/ssb/driver_chipcommon.c +@@ -354,7 +354,7 @@ void ssb_chipcommon_init(struct ssb_chip + + if (cc->dev->id.revision >= 11) + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); +- ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); ++ ssb_dbg("chipcommon status is 0x%x\n", cc->status); + + if (cc->dev->id.revision >= 20) { + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); +--- a/drivers/ssb/driver_chipcommon_pmu.c ++++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s + return; + } + +- ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", +- (crystalfreq / 1000), (crystalfreq % 1000)); ++ ssb_info("Programming PLL to %u.%03u MHz\n", ++ crystalfreq / 1000, crystalfreq % 1000); + + /* First turn the PLL off. */ + switch (bus->chip_id) { +@@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s + } + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) +- ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ++ ssb_emerg("Failed to turn the PLL off!\n"); + + /* Set PDIV in PLL control 0. */ + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); +@@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s + return; + } + +- ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", +- (crystalfreq / 1000), (crystalfreq % 1000)); ++ ssb_info("Programming PLL to %u.%03u MHz\n", ++ crystalfreq / 1000, crystalfreq % 1000); + + /* First turn the PLL off. */ + switch (bus->chip_id) { +@@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s + } + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) +- ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ++ ssb_emerg("Failed to turn the PLL off!\n"); + + /* Set p1div and p2div. */ + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); +@@ -349,9 +349,8 @@ static void ssb_pmu_pll_init(struct ssb_ + case 43222: + break; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PLL init unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PLL init unknown for device %04X\n", ++ bus->chip_id); + } + } + +@@ -472,9 +471,8 @@ static void ssb_pmu_resources_init(struc + max_msk = 0xFFFFF; + break; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU resource config unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU resource config unknown for device %04X\n", ++ bus->chip_id); + } + + if (updown_tab) { +@@ -526,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); + +- ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", +- cc->pmu.rev, pmucap); ++ ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n", ++ cc->pmu.rev, pmucap); + + if (cc->pmu.rev == 1) + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, +@@ -638,9 +636,8 @@ u32 ssb_pmu_get_alp_clock(struct ssb_chi + case 0x5354: + ssb_pmu_get_alp_clock_clk0(cc); + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU alp clock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU alp clock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -654,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi + /* 5354 chip uses a non programmable PLL of frequency 240MHz */ + return 240000000; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU cpu clock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU cpu clock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -669,9 +665,8 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + case 0x5354: + return 120000000; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU controlclock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU controlclock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -692,8 +687,23 @@ void ssb_pmu_spuravoid_pllupdate(struct + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; + break; + case 43222: +- /* TODO: BCM43222 requires updating PLLs too */ +- return; ++ if (spuravoid == 1) { ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815); ++ } else { ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855); ++ } ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; + default: + ssb_printk(KERN_ERR PFX + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", --- /dev/null +++ b/drivers/ssb/driver_chipcommon_sflash.c @@ -0,0 +1,140 @@ @@ -253,7 +403,40 @@ static inline u32 mips_read32(struct ssb_mipscore *mcore, u16 offset) -@@ -189,34 +209,43 @@ static void ssb_mips_serial_init(struct +@@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d + irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]); + ssb_write32(mdev, SSB_IPSFLAG, irqflag); + } +- ssb_dprintk(KERN_INFO PFX +- "set_irq: core 0x%04x, irq %d => %d\n", +- dev->id.coreid, oldirq+2, irq+2); ++ ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.coreid, oldirq+2, irq+2); + } + + static void print_irq(struct ssb_device *dev, unsigned int irq) + { +- int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- ssb_dprintk(KERN_INFO PFX +- "core 0x%04x, irq :", dev->id.coreid); +- for (i = 0; i <= 6; i++) { +- ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" "); +- } +- ssb_dprintk("\n"); ++ ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n", ++ dev->id.coreid, ++ irq_name[0], irq == 0 ? "*" : " ", ++ irq_name[1], irq == 1 ? "*" : " ", ++ irq_name[2], irq == 2 ? "*" : " ", ++ irq_name[3], irq == 3 ? "*" : " ", ++ irq_name[4], irq == 4 ? "*" : " ", ++ irq_name[5], irq == 5 ? "*" : " ", ++ irq_name[6], irq == 6 ? "*" : " "); + } + + static void dump_irq(struct ssb_bus *bus) +@@ -189,34 +210,43 @@ static void ssb_mips_serial_init(struct static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) { struct ssb_bus *bus = mcore->dev->bus; @@ -308,9 +491,142 @@ } u32 ssb_cpu_clock(struct ssb_mipscore *mcore) +@@ -257,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco + if (!mcore->dev) + return; /* We don't have a MIPS core */ + +- ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); ++ ssb_dbg("Initializing MIPS core...\n"); + + bus = mcore->dev->bus; + hz = ssb_clockspeed(bus); +@@ -305,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco + break; + } + } +- ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); ++ ssb_dbg("after irq reconfiguration\n"); + dump_irq(bus); + + ssb_mips_serial_init(mcore); +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci + return -ENODEV; + } + +- ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", +- pci_name(d)); ++ ssb_info("PCI: Fixing up device %s\n", pci_name(d)); + + /* Fix up interrupt lines */ + d->irq = ssb_mips_irq(extpci_core->dev) + 2; +@@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge( + if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) + return; + +- ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); ++ ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev)); + + /* Enable PCI bridge bus mastering and memory space */ + pci_set_master(dev); + if (pcibios_enable_device(dev, ~0) < 0) { +- ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); ++ ssb_err("PCI: SSB bridge enable failed\n"); + return; + } + +@@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge( + + /* Make sure our latency is high enough to handle the devices behind us */ + lat = 168; +- ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", +- pci_name(dev), lat); ++ ssb_info("PCI: Fixing latency timer of device %s to %u\n", ++ pci_name(dev), lat); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); + } + DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); +@@ -323,7 +322,7 @@ static void ssb_pcicore_init_hostmode(st + return; + extpci_core = pc; + +- ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); ++ ssb_dbg("PCIcore in host mode found\n"); + /* Reset devices on the external PCI bus */ + val = SSB_PCICORE_CTL_RST_OE; + val |= SSB_PCICORE_CTL_CLK_OE; +@@ -338,7 +337,7 @@ static void ssb_pcicore_init_hostmode(st + udelay(1); /* Assertion time demanded by the PCI standard */ + + if (pc->dev->bus->has_cardbus_slot) { +- ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); ++ ssb_dbg("CardBus slot detected\n"); + pc->cardbusmode = 1; + /* GPIO 1 resets the bridge */ + ssb_gpio_out(pc->dev->bus, 1, 1); +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -57,9 +57,8 @@ int ssb_watchdog_register(struct ssb_bus + bus->busnumber, &wdt, + sizeof(wdt)); + if (IS_ERR(pdev)) { +- ssb_dprintk(KERN_INFO PFX +- "can not register watchdog device, err: %li\n", +- PTR_ERR(pdev)); ++ ssb_dbg("can not register watchdog device, err: %li\n", ++ PTR_ERR(pdev)); + return PTR_ERR(pdev); + } + --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c -@@ -549,6 +549,14 @@ static int ssb_devices_register(struct s +@@ -275,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c + + err = sdrv->probe(sdev, &sdev->id); + if (err) { +- ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", +- dev_name(sdev->dev)); ++ ssb_err("Failed to thaw device %s\n", ++ dev_name(sdev->dev)); + result = err; + } + ssb_device_put(sdev); +@@ -447,10 +447,9 @@ void ssb_bus_unregister(struct ssb_bus * + + err = ssb_gpio_unregister(bus); + if (err == -EBUSY) +- ssb_dprintk(KERN_ERR PFX "Some GPIOs are still in use.\n"); ++ ssb_dbg("Some GPIOs are still in use\n"); + else if (err) +- ssb_dprintk(KERN_ERR PFX +- "Can not unregister GPIO driver: %i\n", err); ++ ssb_dbg("Can not unregister GPIO driver: %i\n", err); + + ssb_buses_lock(); + ssb_devices_unregister(bus); +@@ -497,8 +496,7 @@ static int ssb_devices_register(struct s + + devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); + if (!devwrap) { +- ssb_printk(KERN_ERR PFX +- "Could not allocate device\n"); ++ ssb_err("Could not allocate device\n"); + err = -ENOMEM; + goto error; + } +@@ -537,9 +535,7 @@ static int ssb_devices_register(struct s + sdev->dev = dev; + err = device_register(dev); + if (err) { +- ssb_printk(KERN_ERR PFX +- "Could not register %s\n", +- dev_name(dev)); ++ ssb_err("Could not register %s\n", dev_name(dev)); + /* Set dev to NULL to not unregister + * dev on error unwinding. */ + sdev->dev = NULL; +@@ -549,6 +545,14 @@ static int ssb_devices_register(struct s dev_idx++; } @@ -325,47 +641,194 @@ return 0; error: /* Unwind the already registered devices. */ ---- a/drivers/ssb/ssb_private.h -+++ b/drivers/ssb/ssb_private.h -@@ -217,6 +217,21 @@ extern u32 ssb_chipco_watchdog_timer_set - u32 ticks); - extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); +@@ -817,10 +821,9 @@ static int ssb_bus_register(struct ssb_b + ssb_mipscore_init(&bus->mipscore); + err = ssb_gpio_init(bus); + if (err == -ENOTSUPP) +- ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n"); ++ ssb_dbg("GPIO driver not activated\n"); + else if (err) +- ssb_dprintk(KERN_ERR PFX +- "Error registering GPIO driver: %i\n", err); ++ ssb_dbg("Error registering GPIO driver: %i\n", err); + err = ssb_fetch_invariants(bus, get_invariants); + if (err) { + ssb_bus_may_powerdown(bus); +@@ -870,11 +873,11 @@ int ssb_bus_pcibus_register(struct ssb_b -+/* driver_chipcommon_sflash.c */ -+#ifdef CONFIG_SSB_SFLASH -+int ssb_sflash_init(struct ssb_chipcommon *cc); -+#else -+static inline int ssb_sflash_init(struct ssb_chipcommon *cc) -+{ -+ pr_err("Serial flash not supported\n"); -+ return 0; -+} -+#endif /* CONFIG_SSB_SFLASH */ -+ -+#ifdef CONFIG_SSB_DRIVER_MIPS -+extern struct platform_device ssb_pflash_dev; -+#endif -+ - #ifdef CONFIG_SSB_DRIVER_EXTIF - extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); - extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); ---- a/include/linux/ssb/ssb_driver_mips.h -+++ b/include/linux/ssb/ssb_driver_mips.h -@@ -45,6 +45,11 @@ void ssb_mipscore_init(struct ssb_mipsco - { + err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "PCI device %s\n", dev_name(&host_pci->dev)); ++ ssb_info("Sonics Silicon Backplane found on PCI device %s\n", ++ dev_name(&host_pci->dev)); + } else { +- ssb_printk(KERN_ERR PFX "Failed to register PCI version" +- " of SSB with error %d\n", err); ++ ssb_err("Failed to register PCI version of SSB with error %d\n", ++ err); + } + + return err; +@@ -895,8 +898,8 @@ int ssb_bus_pcmciabus_register(struct ss + + err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "PCMCIA device %s\n", pcmcia_dev->devname); ++ ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", ++ pcmcia_dev->devname); + } + + return err; +@@ -917,8 +920,8 @@ int ssb_bus_sdiobus_register(struct ssb_ + + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "SDIO device %s\n", sdio_func_id(func)); ++ ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", ++ sdio_func_id(func)); + } + + return err; +@@ -936,8 +939,8 @@ int ssb_bus_ssbbus_register(struct ssb_b + + err = ssb_bus_register(bus, get_invariants, baseaddr); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " +- "address 0x%08lX\n", baseaddr); ++ ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", ++ baseaddr); + } + + return err; +@@ -1331,7 +1334,7 @@ out: + #endif + return err; + error: +- ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); ++ ssb_err("Bus powerdown failed\n"); + goto out; } + EXPORT_SYMBOL(ssb_bus_may_powerdown); +@@ -1354,7 +1357,7 @@ int ssb_bus_powerup(struct ssb_bus *bus, -+static inline unsigned int ssb_mips_irq(struct ssb_device *dev) + return 0; + error: +- ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); ++ ssb_err("Bus powerup failed\n"); + return err; + } + EXPORT_SYMBOL(ssb_bus_powerup); +@@ -1462,15 +1465,13 @@ static int __init ssb_modinit(void) + + err = b43_pci_ssb_bridge_init(); + if (err) { +- ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " +- "initialization failed\n"); ++ ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); + /* don't fail SSB init because of this */ + err = 0; + } + err = ssb_gige_init(); + if (err) { +- ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet " +- "driver initialization failed\n"); ++ ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); + /* don't fail SSB init because of this */ + err = 0; + } +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu + } + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); ++ ssb_err("Failed to switch to core %u\n", coreidx); + return -ENODEV; + } + +@@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus * + unsigned long flags; + + #if SSB_VERBOSE_PCICORESWITCH_DEBUG +- ssb_printk(KERN_INFO PFX +- "Switching to %s core, index %d\n", +- ssb_core_name(dev->id.coreid), +- dev->core_index); ++ ssb_info("Switching to %s core, index %d\n", ++ ssb_core_name(dev->id.coreid), ++ dev->core_index); + #endif + + spin_lock_irqsave(&bus->bar_lock, flags); +@@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat + return t[crc ^ data]; + } + ++static void sprom_get_mac(char *mac, const u16 *in) +{ -+ return 0; ++ int i; ++ for (i = 0; i < 3; i++) { ++ *mac++ = in[i] >> 8; ++ *mac++ = in[i]; ++ } +} + - #endif /* CONFIG_SSB_DRIVER_MIPS */ + static u8 ssb_sprom_crc(const u16 *sprom, u16 size) + { + int word; +@@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus + u32 spromctl; + u16 size = bus->sprom_size; - #endif /* LINUX_SSB_MIPSCORE_H_ */ ---- a/drivers/ssb/pci.c -+++ b/drivers/ssb/pci.c -@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ +- ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n"); ++ ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n"); + err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); + if (err) + goto err_ctlreg; +@@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus + err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); + if (err) + goto err_ctlreg; +- ssb_printk(KERN_NOTICE PFX "[ 0%%"); ++ ssb_notice("[ 0%%"); + msleep(500); + for (i = 0; i < size; i++) { + if (i == size / 4) +- ssb_printk("25%%"); ++ ssb_cont("25%%"); + else if (i == size / 2) +- ssb_printk("50%%"); ++ ssb_cont("50%%"); + else if (i == (size * 3) / 4) +- ssb_printk("75%%"); ++ ssb_cont("75%%"); + else if (i % 2) +- ssb_printk("."); ++ ssb_cont("."); + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); + mmiowb(); + msleep(20); +@@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus + if (err) + goto err_ctlreg; + msleep(500); +- ssb_printk("100%% ]\n"); +- ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); ++ ssb_cont("100%% ]\n"); ++ ssb_notice("SPROM written\n"); + + return 0; + err_ctlreg: +- ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n"); ++ ssb_err("Could not access SPROM control register.\n"); + return err; + } + +@@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_ return (s8)gain; } @@ -386,8 +849,43 @@ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) { - int i; -@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss +- int i; +- u16 v; + u16 loc[3]; + + if (out->revision == 3) /* rev 3 moved MAC */ +@@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss + loc[1] = SSB_SPROM1_ET0MAC; + loc[2] = SSB_SPROM1_ET1MAC; + } +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[0]) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]); + if (out->revision < 3) { /* only rev 1-2 have et0, et1 */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[1]) + i]; +- *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v); +- } +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[2]) + i]; +- *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]); ++ sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]); + } + SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); + SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, +@@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss + SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); + SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); + SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + if (out->revision == 1) + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, + SSB_SPROM1_BINF_CCODE_SHIFT); +@@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss SSB_SPROM1_ITSSI_A_SHIFT); SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); @@ -397,7 +895,7 @@ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); -@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss +@@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, SSB_SPROM1_AGAIN_A, SSB_SPROM1_AGAIN_A_SHIFT); @@ -406,6 +904,557 @@ } /* Revs 4 5 and 8 have partially shared layout */ +@@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss + + static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) + { +- int i; +- u16 v; + u16 il0mac_offset; + + if (out->revision == 4) + il0mac_offset = SSB_SPROM4_IL0MAC; + else + il0mac_offset = SSB_SPROM5_IL0MAC; +- /* extract the MAC address */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(il0mac_offset) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ ++ sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]); ++ + SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); + SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, + SSB_SPROM4_ETHPHY_ET1A_SHIFT); + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + if (out->revision == 4) { + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0); +@@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb + static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) + { + int i; +- u16 v, o; ++ u16 o; + u16 pwr_info_offset[] = { + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 +@@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_ + ARRAY_SIZE(out->core_pwr_info)); + + /* extract the MAC address */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(SSB_SPROM8_IL0MAC) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]); ++ + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0); + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0); +@@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus + memset(out, 0, sizeof(*out)); + + out->revision = in[size - 1] & 0x00FF; +- ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); ++ ssb_dbg("SPROM revision %d detected\n", out->revision); + memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ + memset(out->et1mac, 0xFF, 6); + +@@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus + * number stored in the SPROM. + * Always extract r1. */ + out->revision = 1; +- ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); ++ ssb_dbg("SPROM treated as revision %d\n", out->revision); + } + + switch (out->revision) { +@@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus + sprom_extract_r8(out, in); + break; + default: +- ssb_printk(KERN_WARNING PFX "Unsupported SPROM" +- " revision %d detected. Will extract" +- " v1\n", out->revision); ++ ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n", ++ out->revision); + out->revision = 1; + sprom_extract_r123(out, in); + } +@@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_ + u16 *buf; + + if (!ssb_is_sprom_available(bus)) { +- ssb_printk(KERN_ERR PFX "No SPROM available!\n"); ++ ssb_err("No SPROM available!\n"); + return -ENODEV; + } + if (bus->chipco.dev) { /* can be unavailable! */ +@@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_ + } else { + bus->sprom_offset = SSB_SPROM_BASE1; + } +- ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset); ++ ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset); + + buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); + if (!buf) +@@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_ + * available for this device in some other storage */ + err = ssb_fill_sprom_with_fallback(bus, sprom); + if (err) { +- ssb_printk(KERN_WARNING PFX "WARNING: Using" +- " fallback SPROM failed (err %d)\n", +- err); ++ ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n", ++ err); + } else { +- ssb_dprintk(KERN_DEBUG PFX "Using SPROM" +- " revision %d provided by" +- " platform.\n", sprom->revision); ++ ssb_dbg("Using SPROM revision %d provided by platform\n", ++ sprom->revision); + err = 0; + goto out_free; + } +- ssb_printk(KERN_WARNING PFX "WARNING: Invalid" +- " SPROM CRC (corrupt SPROM)\n"); ++ ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n"); + } + } + err = sprom_extract(bus, sprom, buf, bus->sprom_size); +--- a/drivers/ssb/pcmcia.c ++++ b/drivers/ssb/pcmcia.c +@@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); ++ ssb_err("Failed to switch to core %u\n", coreidx); + return err; + } + +@@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu + int err; + + #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG +- ssb_printk(KERN_INFO PFX +- "Switching to %s core, index %d\n", +- ssb_core_name(dev->id.coreid), +- dev->core_index); ++ ssb_info("Switching to %s core, index %d\n", ++ ssb_core_name(dev->id.coreid), ++ dev->core_index); + #endif + + err = ssb_pcmcia_switch_coreidx(bus, dev->core_index); +@@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n"); ++ ssb_err("Failed to switch pcmcia segment\n"); + return err; + } + +@@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st + bool failed = 0; + size_t size = SSB_PCMCIA_SPROM_SIZE; + +- ssb_printk(KERN_NOTICE PFX +- "Writing SPROM. Do NOT turn off the power! " +- "Please stand by...\n"); ++ ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n"); + err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Could not enable SPROM write access.\n"); ++ ssb_notice("Could not enable SPROM write access\n"); + return -EBUSY; + } +- ssb_printk(KERN_NOTICE PFX "[ 0%%"); ++ ssb_notice("[ 0%%"); + msleep(500); + for (i = 0; i < size; i++) { + if (i == size / 4) +- ssb_printk("25%%"); ++ ssb_cont("25%%"); + else if (i == size / 2) +- ssb_printk("50%%"); ++ ssb_cont("50%%"); + else if (i == (size * 3) / 4) +- ssb_printk("75%%"); ++ ssb_cont("75%%"); + else if (i % 2) +- ssb_printk("."); ++ ssb_cont("."); + err = ssb_pcmcia_sprom_write(bus, i, sprom[i]); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Failed to write to SPROM.\n"); ++ ssb_notice("Failed to write to SPROM\n"); + failed = 1; + break; + } + } + err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Could not disable SPROM write access.\n"); ++ ssb_notice("Could not disable SPROM write access\n"); + failed = 1; + } + msleep(500); + if (!failed) { +- ssb_printk("100%% ]\n"); +- ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); ++ ssb_cont("100%% ]\n"); ++ ssb_notice("SPROM written\n"); + } + + return failed ? -EBUSY : 0; +@@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants( + return -ENOSPC; /* continue with next entry */ + + error: +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch device invariants: %s\n", + error_description); + return -ENODEV; +@@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE, + ssb_pcmcia_get_mac, sprom); + if (res != 0) { +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch MAC address\n"); + return -ENODEV; + } +@@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb + if ((res == 0) || (res == -ENOSPC)) + return 0; + +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch device invariants\n"); + return -ENODEV; + } +@@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus) + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n"); ++ ssb_err("Failed to initialize PCMCIA host device\n"); + return err; + } +--- a/drivers/ssb/scan.c ++++ b/drivers/ssb/scan.c +@@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d + chipid_fallback = 0x4401; + break; + default: +- ssb_printk(KERN_ERR PFX +- "PCI-ID not in fallback list\n"); ++ ssb_err("PCI-ID not in fallback list\n"); + } + + return chipid_fallback; +@@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid) + case 0x4704: + return 9; + default: +- ssb_printk(KERN_ERR PFX +- "CHIPID not in nrcores fallback list\n"); ++ ssb_err("CHIPID not in nrcores fallback list\n"); + } + + return 1; +@@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus, + bus->chip_package = 0; + } + } +- ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and " +- "package 0x%02X\n", bus->chip_id, bus->chip_rev, +- bus->chip_package); ++ ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n", ++ bus->chip_id, bus->chip_rev, bus->chip_package); + if (!bus->nr_devices) + bus->nr_devices = chipid_to_nrcores(bus->chip_id); + if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { +- ssb_printk(KERN_ERR PFX +- "More than %d ssb cores found (%d)\n", +- SSB_MAX_NR_CORES, bus->nr_devices); ++ ssb_err("More than %d ssb cores found (%d)\n", ++ SSB_MAX_NR_CORES, bus->nr_devices); + goto err_unmap; + } + if (bus->bustype == SSB_BUSTYPE_SSB) { +@@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + nr_80211_cores++; + if (nr_80211_cores > 1) { + if (!we_support_multiple_80211_cores(bus)) { +- ssb_dprintk(KERN_INFO PFX "Ignoring additional " +- "802.11 core\n"); ++ ssb_dbg("Ignoring additional 802.11 core\n"); + continue; + } + } +@@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + case SSB_DEV_EXTIF: + #ifdef CONFIG_SSB_DRIVER_EXTIF + if (bus->extif.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple EXTIFs found\n"); ++ ssb_warn("WARNING: Multiple EXTIFs found\n"); + break; + } + bus->extif.dev = dev; +@@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + break; + case SSB_DEV_CHIPCOMMON: + if (bus->chipco.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple ChipCommon found\n"); ++ ssb_warn("WARNING: Multiple ChipCommon found\n"); + break; + } + bus->chipco.dev = dev; +@@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + case SSB_DEV_MIPS_3302: + #ifdef CONFIG_SSB_DRIVER_MIPS + if (bus->mipscore.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple MIPS cores found\n"); ++ ssb_warn("WARNING: Multiple MIPS cores found\n"); + break; + } + bus->mipscore.dev = dev; +@@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + } + } + if (bus->pcicore.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple PCI(E) cores found\n"); ++ ssb_warn("WARNING: Multiple PCI(E) cores found\n"); + break; + } + bus->pcicore.dev = dev; +--- a/drivers/ssb/sprom.c ++++ b/drivers/ssb/sprom.c +@@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_ + goto out_kfree; + err = ssb_devices_freeze(bus, &freeze); + if (err) { +- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); ++ ssb_err("SPROM write: Could not freeze all devices\n"); + goto out_unlock; + } + res = sprom_write(bus, sprom); + err = ssb_devices_thaw(&freeze); + if (err) +- ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); ++ ssb_err("SPROM write: Could not thaw all devices\n"); + out_unlock: + mutex_unlock(&bus->sprom_mutex); + out_kfree: +--- a/drivers/ssb/ssb_private.h ++++ b/drivers/ssb/ssb_private.h +@@ -9,16 +9,27 @@ + #define PFX "ssb: " + + #ifdef CONFIG_SSB_SILENT +-# define ssb_printk(fmt, x...) do { /* nothing */ } while (0) ++# define ssb_printk(fmt, ...) \ ++ do { if (0) printk(fmt, ##__VA_ARGS__); } while (0) + #else +-# define ssb_printk printk ++# define ssb_printk(fmt, ...) \ ++ printk(fmt, ##__VA_ARGS__) + #endif /* CONFIG_SSB_SILENT */ + ++#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__) ++#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__) ++#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__) ++#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__) ++#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__) ++#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__) ++ + /* dprintk: Debugging printk; vanishes for non-debug compilation */ + #ifdef CONFIG_SSB_DEBUG +-# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x) ++# define ssb_dbg(fmt, ...) \ ++ ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__) + #else +-# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0) ++# define ssb_dbg(fmt, ...) \ ++ do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0) + #endif + + #ifdef CONFIG_SSB_DEBUG +@@ -217,6 +228,21 @@ extern u32 ssb_chipco_watchdog_timer_set + u32 ticks); + extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); + ++/* driver_chipcommon_sflash.c */ ++#ifdef CONFIG_SSB_SFLASH ++int ssb_sflash_init(struct ssb_chipcommon *cc); ++#else ++static inline int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_SSB_SFLASH */ ++ ++#ifdef CONFIG_SSB_DRIVER_MIPS ++extern struct platform_device ssb_pflash_dev; ++#endif ++ + #ifdef CONFIG_SSB_DRIVER_EXTIF + extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); + extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -26,9 +26,9 @@ struct ssb_sprom_core_pwr_info { + + struct ssb_sprom { + u8 revision; +- u8 il0mac[6]; /* MAC address for 802.11b/g */ +- u8 et0mac[6]; /* MAC address for Ethernet */ +- u8 et1mac[6]; /* MAC address for 802.11a */ ++ u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ ++ u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ ++ u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ + u8 et0phyaddr; /* MII address for enet0 */ + u8 et1phyaddr; /* MII address for enet1 */ + u8 et0mdcport; /* MDIO for enet0 */ +@@ -340,13 +340,61 @@ enum ssb_bustype { + #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */ + #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */ + /* board_type */ ++#define SSB_BOARD_BCM94301CB 0x0406 ++#define SSB_BOARD_BCM94301MP 0x0407 ++#define SSB_BOARD_BU4309 0x040A ++#define SSB_BOARD_BCM94309CB 0x040B ++#define SSB_BOARD_BCM4309MP 0x040C ++#define SSB_BOARD_BU4306 0x0416 + #define SSB_BOARD_BCM94306MP 0x0418 + #define SSB_BOARD_BCM4309G 0x0421 + #define SSB_BOARD_BCM4306CB 0x0417 +-#define SSB_BOARD_BCM4309MP 0x040C ++#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ ++#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */ ++#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */ ++#define SSB_BOARD_BU4704SD 0x042E /* with sdram */ ++#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */ ++#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */ ++#define SSB_BOARD_BU4318 0x0447 ++#define SSB_BOARD_CB4318 0x0448 ++#define SSB_BOARD_MPG4318 0x0449 + #define SSB_BOARD_MP4318 0x044A +-#define SSB_BOARD_BU4306 0x0416 +-#define SSB_BOARD_BU4309 0x040A ++#define SSB_BOARD_SD4318 0x044B ++#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */ ++#define SSB_BOARD_BCM94303MP 0x044E ++#define SSB_BOARD_BCM94306MPM 0x0450 ++#define SSB_BOARD_BCM94306MPL 0x0453 ++#define SSB_BOARD_PC4303 0x0454 /* pcmcia */ ++#define SSB_BOARD_BCM94306MPLNA 0x0457 ++#define SSB_BOARD_BCM94306MPH 0x045B ++#define SSB_BOARD_BCM94306PCIV 0x045C ++#define SSB_BOARD_BCM94318MPGH 0x0463 ++#define SSB_BOARD_BU4311 0x0464 ++#define SSB_BOARD_BCM94311MC 0x0465 ++#define SSB_BOARD_BCM94311MCAG 0x0466 ++/* 4321 boards */ ++#define SSB_BOARD_BU4321 0x046B ++#define SSB_BOARD_BU4321E 0x047C ++#define SSB_BOARD_MP4321 0x046C ++#define SSB_BOARD_CB2_4321 0x046D ++#define SSB_BOARD_CB2_4321_AG 0x0066 ++#define SSB_BOARD_MC4321 0x046E ++/* 4325 boards */ ++#define SSB_BOARD_BCM94325DEVBU 0x0490 ++#define SSB_BOARD_BCM94325BGABU 0x0491 ++#define SSB_BOARD_BCM94325SDGWB 0x0492 ++#define SSB_BOARD_BCM94325SDGMDL 0x04AA ++#define SSB_BOARD_BCM94325SDGMDL2 0x04C6 ++#define SSB_BOARD_BCM94325SDGMDL3 0x04C9 ++#define SSB_BOARD_BCM94325SDABGWBA 0x04E1 ++/* 4322 boards */ ++#define SSB_BOARD_BCM94322MC 0x04A4 ++#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */ ++#define SSB_BOARD_BCM94322HM 0x04B0 ++#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */ ++/* 4312 boards */ ++#define SSB_BOARD_BU4312 0x048A ++#define SSB_BOARD_BCM4312MCGSG 0x04B5 + /* chip_package */ + #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ + #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */ +--- a/include/linux/ssb/ssb_driver_gige.h ++++ b/include/linux/ssb/ssb_driver_gige.h +@@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p + return 0; + } + +-#ifdef CONFIG_BCM47XX +-#include <asm/mach-bcm47xx/nvram.h> + /* Get the device MAC address */ +-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) +-{ +- char buf[20]; +- if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0) +- return; +- nvram_parse_macaddr(buf, macaddr); +-} +-#else +-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) ++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) + { ++ struct ssb_gige *dev = pdev_to_ssb_gige(pdev); ++ if (!dev) ++ return -ENODEV; ++ ++ memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6); ++ return 0; + } +-#endif + + extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev, + struct pci_dev *pdev); +@@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p + { + return 0; + } ++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) ++{ ++ return -ENODEV; ++} + + #endif /* CONFIG_SSB_DRIVER_GIGE */ + #endif /* LINUX_SSB_DRIVER_GIGE_H_ */ +--- a/include/linux/ssb/ssb_driver_mips.h ++++ b/include/linux/ssb/ssb_driver_mips.h +@@ -45,6 +45,11 @@ void ssb_mipscore_init(struct ssb_mipsco + { + } + ++static inline unsigned int ssb_mips_irq(struct ssb_device *dev) ++{ ++ return 0; ++} ++ + #endif /* CONFIG_SSB_DRIVER_MIPS */ + + #endif /* LINUX_SSB_MIPSCORE_H_ */ --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h @@ -289,11 +289,11 @@ diff --git a/target/linux/generic/patches-3.8/025-bcma_backport.patch b/target/linux/generic/patches-3.8/025-bcma_backport.patch index c80275b951..360ee718c4 100644 --- a/target/linux/generic/patches-3.8/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.8/025-bcma_backport.patch @@ -28,6 +28,23 @@ #endif /* CONFIG_BCMA_DRIVER_MIPS */ /* driver_chipcommon_pmu.c */ +--- a/drivers/bcma/core.c ++++ b/drivers/bcma/core.c +@@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_devic + if (i) + bcma_err(core->bus, "PLL enable timeout\n"); + } else { +- bcma_warn(core->bus, "Disabling PLL not supported yet!\n"); ++ /* ++ * Mask the PLL but don't wait for it to be disabled. PLL may be ++ * shared between cores and will be still up if there is another ++ * core using it. ++ */ ++ bcma_mask32(core, BCMA_CLKCTLST, ~req); ++ bcma_read32(core, BCMA_CLKCTLST); + } + } + EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked @@ -87,6 +104,110 @@ struct platform_device bcma_nflash_dev = { .name = "bcma_nflash", .num_resources = 0, +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -264,7 +280,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st + } + + /* query bus clock frequency for PMU-enabled chipcommon */ +-static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) ++u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) + { + struct bcma_bus *bus = cc->core->bus; + +@@ -293,6 +309,7 @@ static u32 bcma_pmu_get_bus_clock(struct + } + return BCMA_CC_PMU_HT_CLOCK; + } ++EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock); + + /* query cpu clock frequency for PMU-enabled chipcommon */ + u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) +@@ -372,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -393,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -426,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -460,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -496,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", --- a/drivers/bcma/driver_chipcommon_sflash.c +++ b/drivers/bcma/driver_chipcommon_sflash.c @@ -5,11 +5,11 @@ @@ -558,7 +679,16 @@ return cap_ptr; /* check if the capability pointer field exists */ -@@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct +@@ -401,6 +404,8 @@ void bcma_core_pci_hostmode_init(struct + return; + } + ++ spin_lock_init(&pc_host->cfgspace_lock); ++ + pc->host_controller = pc_host; + pc_host->pci_controller.io_resource = &pc_host->io_resource; + pc_host->pci_controller.mem_resource = &pc_host->mem_resource; +@@ -426,7 +431,7 @@ void bcma_core_pci_hostmode_init(struct /* Reset RC */ usleep_range(3000, 5000); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); @@ -567,7 +697,7 @@ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | BCMA_CORE_PCI_CTL_RST_OE); -@@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct +@@ -488,6 +493,17 @@ void bcma_core_pci_hostmode_init(struct bcma_core_pci_enable_crs(pc); @@ -585,7 +715,7 @@ /* Enable PCI bridge BAR0 memory & master access */ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); -@@ -576,7 +590,7 @@ int bcma_core_pci_plat_dev_init(struct p +@@ -576,7 +592,7 @@ int bcma_core_pci_plat_dev_init(struct p pr_info("PCI: Fixing up device %s\n", pci_name(dev)); /* Fix up interrupt lines */ @@ -594,7 +724,7 @@ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); return 0; -@@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const +@@ -595,6 +611,6 @@ int bcma_core_pci_pcibios_map_irq(const pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, pci_ops); @@ -615,7 +745,19 @@ { struct bcma_device *core; -@@ -149,6 +149,14 @@ static int bcma_register_cores(struct bc +@@ -120,6 +120,11 @@ static int bcma_register_cores(struct bc + continue; + } + ++ /* Only first GMAC core on BCM4706 is connected and working */ ++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT && ++ core->core_unit > 0) ++ continue; ++ + core->dev.release = bcma_release_core_dev; + core->dev.bus = &bcma_bus_type; + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); +@@ -149,6 +154,14 @@ static int bcma_register_cores(struct bc dev_id++; } @@ -630,6 +772,156 @@ #ifdef CONFIG_BCMA_SFLASH if (bus->drv_cc.sflash.present) { err = platform_device_register(&bcma_sflash_dev); +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct + addr); + } + +-static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr) ++static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = readl(*eromptr); + (*eromptr)++; + return ent; + } + +-static void bcma_erom_push_ent(u32 **eromptr) ++static void bcma_erom_push_ent(u32 __iomem **eromptr) + { + (*eromptr)--; + } + +-static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr) ++static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + if (!(ent & SCAN_ER_VALID)) +@@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_ + return ent; + } + +-static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr) ++static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + bcma_erom_push_ent(eromptr); + return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)); + } + +-static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr) ++static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + bcma_erom_push_ent(eromptr); +@@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct b + ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE)); + } + +-static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr) ++static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent; + while (1) { +@@ -189,7 +189,7 @@ static void bcma_erom_skip_component(str + bcma_erom_push_ent(eromptr); + } + +-static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr) ++static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + if (!(ent & SCAN_ER_VALID)) +@@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct + return ent; + } + +-static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr, ++static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, + u32 type, u8 port) + { + u32 addrl, addrh, sizel, sizeh = 0; +--- a/drivers/bcma/sprom.c ++++ b/drivers/bcma/sprom.c +@@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct + } + + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, ~0, 0); + + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0, + SSB_SPROM4_TXPID2G0_SHIFT); +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -134,6 +134,7 @@ struct bcma_host_ops { + #define BCMA_CORE_I2S 0x834 + #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */ + #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */ ++#define BCMA_CORE_ARM_CR4 0x83e + #define BCMA_CORE_DEFAULT 0xFFF + + #define BCMA_MAX_NR_CORES 16 +@@ -173,6 +174,60 @@ struct bcma_host_ops { + #define BCMA_CHIP_ID_BCM53572 53572 + #define BCMA_PKG_ID_BCM47188 9 + ++/* Board types (on PCI usually equals to the subsystem dev id) */ ++/* BCM4313 */ ++#define BCMA_BOARD_TYPE_BCM94313BU 0X050F ++#define BCMA_BOARD_TYPE_BCM94313HM 0X0510 ++#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511 ++#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C ++/* BCM4716 */ ++#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD ++/* BCM43224 */ ++#define BCMA_BOARD_TYPE_BCM943224X21 0X056E ++#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1 ++#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9 ++#define BCMA_BOARD_TYPE_BCM943224M93 0X008B ++#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090 ++#define BCMA_BOARD_TYPE_BCM943224X16 0X0093 ++#define BCMA_BOARD_TYPE_BCM94322X9 0X008D ++#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E ++/* BCM43228 */ ++#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540 ++#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541 ++#define BCMA_BOARD_TYPE_BCM943228BU 0X0542 ++#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543 ++#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544 ++#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545 ++#define BCMA_BOARD_TYPE_BCM943228SD 0X0573 ++/* BCM4331 */ ++#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6 ++#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4 ++#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E ++#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4 ++#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC ++#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED ++#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF ++#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF ++#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5 ++#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4 ++#define BCMA_BOARD_TYPE_BCM94331BU 0X0523 ++#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524 ++#define BCMA_BOARD_TYPE_BCM94331MC 0X0525 ++#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526 ++#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527 ++#define BCMA_BOARD_TYPE_BCM94331HM 0X0574 ++#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B ++#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9 ++#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6 ++#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA ++/* BCM53572 */ ++#define BCMA_BOARD_TYPE_BCM953572BU 0X058D ++#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E ++#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F ++#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590 ++/* BCM43142 */ ++#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0 ++ + struct bcma_device { + struct bcma_bus *bus; + struct bcma_device_id id; --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h @@ -27,7 +27,7 @@ @@ -659,7 +951,15 @@ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ -@@ -606,6 +610,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct +@@ -528,6 +532,7 @@ struct bcma_sflash { + u32 size; + + struct mtd_info *mtd; ++ void *priv; + }; + #endif + +@@ -606,6 +611,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); @@ -668,6 +968,13 @@ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); +@@ -634,4 +641,6 @@ extern void bcma_chipco_regctl_maskset(s + u32 offset, u32 mask, u32 set); + extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); + ++extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); ++ + #endif /* LINUX_BCMA_DRIVER_CC_H_ */ --- a/include/linux/bcma/bcma_driver_mips.h +++ b/include/linux/bcma/bcma_driver_mips.h @@ -28,6 +28,7 @@ @@ -716,103 +1023,6 @@ /* PCIE Root Capability Register bits (Host mode only) */ #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 ---- a/drivers/bcma/driver_chipcommon_pmu.c -+++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d - struct bcma_bus *bus = cc->core->bus; - - switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM4313: -+ case BCMA_CHIP_ID_BCM43224: -+ case BCMA_CHIP_ID_BCM43225: -+ case BCMA_CHIP_ID_BCM43227: -+ case BCMA_CHIP_ID_BCM43228: -+ case BCMA_CHIP_ID_BCM4331: -+ case BCMA_CHIP_ID_BCM43421: -+ case BCMA_CHIP_ID_BCM43428: -+ case BCMA_CHIP_ID_BCM43431: - case BCMA_CHIP_ID_BCM4716: -- case BCMA_CHIP_ID_BCM4748: - case BCMA_CHIP_ID_BCM47162: -- case BCMA_CHIP_ID_BCM4313: -- case BCMA_CHIP_ID_BCM5357: -+ case BCMA_CHIP_ID_BCM4748: - case BCMA_CHIP_ID_BCM4749: -+ case BCMA_CHIP_ID_BCM5357: - case BCMA_CHIP_ID_BCM53572: -+ case BCMA_CHIP_ID_BCM6362: - /* always 20Mhz */ - return 20000 * 1000; -- case BCMA_CHIP_ID_BCM5356: - case BCMA_CHIP_ID_BCM4706: -+ case BCMA_CHIP_ID_BCM5356: - /* always 25Mhz */ - return 25000 * 1000; -+ case BCMA_CHIP_ID_BCM43460: -+ case BCMA_CHIP_ID_BCM4352: -+ case BCMA_CHIP_ID_BCM4360: -+ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) -+ return 40000 * 1000; -+ else -+ return 20000 * 1000; - default: - bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); -@@ -372,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); - -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM4331: -@@ -393,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, - 0x03000a08); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM43224: -@@ -426,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, - 0x88888815); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM4716: -@@ -460,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - 0x88888815); - } - -- tmp = 3 << 9; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; - break; - - case BCMA_CHIP_ID_BCM43227: -@@ -496,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, - 0x88888815); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - default: - bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ---- a/include/linux/bcma/bcma.h -+++ b/include/linux/bcma/bcma.h -@@ -134,6 +134,7 @@ struct bcma_host_ops { - #define BCMA_CORE_I2S 0x834 - #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */ - #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */ -+#define BCMA_CORE_ARM_CR4 0x83e - #define BCMA_CORE_DEFAULT 0xFFF - - #define BCMA_MAX_NR_CORES 16 --- a/include/linux/bcma/bcma_regs.h +++ b/include/linux/bcma/bcma_regs.h @@ -37,6 +37,7 @@ diff --git a/target/linux/generic/patches-3.9/020-ssb_backport.patch b/target/linux/generic/patches-3.9/020-ssb_backport.patch deleted file mode 100644 index d7dcbe8dbf..0000000000 --- a/target/linux/generic/patches-3.9/020-ssb_backport.patch +++ /dev/null @@ -1,62 +0,0 @@ ---- a/drivers/ssb/pci.c -+++ b/drivers/ssb/pci.c -@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_ - return (s8)gain; - } - -+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) -+{ -+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); -+ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); -+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); -+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); -+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); -+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); -+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); -+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); -+ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); -+ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, -+ SSB_SPROM2_MAXP_A_LO_SHIFT); -+} -+ - static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) - { - int i; -@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss - SSB_SPROM1_ITSSI_A_SHIFT); - SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); - SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); -- if (out->revision >= 2) -- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); -+ - SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); - SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); - -@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss - out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, - SSB_SPROM1_AGAIN_A, - SSB_SPROM1_AGAIN_A_SHIFT); -+ if (out->revision >= 2) -+ sprom_extract_r23(out, in); - } - - /* Revs 4 5 and 8 have partially shared layout */ ---- a/include/linux/ssb/ssb_regs.h -+++ b/include/linux/ssb/ssb_regs.h -@@ -289,11 +289,11 @@ - #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 - #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ - #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ --#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ --#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ --#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 --#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ --#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 -+#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ -+#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ -+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 -+#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ -+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 - #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ - #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ - #define SSB_SPROM4_AGAIN0_SHIFT 0 diff --git a/target/linux/generic/patches-3.9/020-ssb_update.patch b/target/linux/generic/patches-3.9/020-ssb_update.patch new file mode 100644 index 0000000000..c87c2f6abe --- /dev/null +++ b/target/linux/generic/patches-3.9/020-ssb_update.patch @@ -0,0 +1,1075 @@ +--- a/drivers/ssb/driver_chipcommon.c ++++ b/drivers/ssb/driver_chipcommon.c +@@ -354,7 +354,7 @@ void ssb_chipcommon_init(struct ssb_chip + + if (cc->dev->id.revision >= 11) + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); +- ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); ++ ssb_dbg("chipcommon status is 0x%x\n", cc->status); + + if (cc->dev->id.revision >= 20) { + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); +--- a/drivers/ssb/driver_chipcommon_pmu.c ++++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s + return; + } + +- ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", +- (crystalfreq / 1000), (crystalfreq % 1000)); ++ ssb_info("Programming PLL to %u.%03u MHz\n", ++ crystalfreq / 1000, crystalfreq % 1000); + + /* First turn the PLL off. */ + switch (bus->chip_id) { +@@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s + } + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) +- ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ++ ssb_emerg("Failed to turn the PLL off!\n"); + + /* Set PDIV in PLL control 0. */ + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); +@@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s + return; + } + +- ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", +- (crystalfreq / 1000), (crystalfreq % 1000)); ++ ssb_info("Programming PLL to %u.%03u MHz\n", ++ crystalfreq / 1000, crystalfreq % 1000); + + /* First turn the PLL off. */ + switch (bus->chip_id) { +@@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s + } + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) +- ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ++ ssb_emerg("Failed to turn the PLL off!\n"); + + /* Set p1div and p2div. */ + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); +@@ -349,9 +349,8 @@ static void ssb_pmu_pll_init(struct ssb_ + case 43222: + break; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PLL init unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PLL init unknown for device %04X\n", ++ bus->chip_id); + } + } + +@@ -472,9 +471,8 @@ static void ssb_pmu_resources_init(struc + max_msk = 0xFFFFF; + break; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU resource config unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU resource config unknown for device %04X\n", ++ bus->chip_id); + } + + if (updown_tab) { +@@ -526,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); + +- ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", +- cc->pmu.rev, pmucap); ++ ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n", ++ cc->pmu.rev, pmucap); + + if (cc->pmu.rev == 1) + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, +@@ -638,9 +636,8 @@ u32 ssb_pmu_get_alp_clock(struct ssb_chi + case 0x5354: + ssb_pmu_get_alp_clock_clk0(cc); + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU alp clock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU alp clock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -654,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi + /* 5354 chip uses a non programmable PLL of frequency 240MHz */ + return 240000000; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU cpu clock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU cpu clock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -669,9 +665,8 @@ u32 ssb_pmu_get_controlclock(struct ssb_ + case 0x5354: + return 120000000; + default: +- ssb_printk(KERN_ERR PFX +- "ERROR: PMU controlclock unknown for device %04X\n", +- bus->chip_id); ++ ssb_err("ERROR: PMU controlclock unknown for device %04X\n", ++ bus->chip_id); + return 0; + } + } +@@ -692,8 +687,23 @@ void ssb_pmu_spuravoid_pllupdate(struct + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; + break; + case 43222: +- /* TODO: BCM43222 requires updating PLLs too */ +- return; ++ if (spuravoid == 1) { ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815); ++ } else { ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0); ++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855); ++ } ++ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; ++ break; + default: + ssb_printk(KERN_ERR PFX + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", +--- a/drivers/ssb/driver_mipscore.c ++++ b/drivers/ssb/driver_mipscore.c +@@ -167,21 +167,22 @@ static void set_irq(struct ssb_device *d + irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]); + ssb_write32(mdev, SSB_IPSFLAG, irqflag); + } +- ssb_dprintk(KERN_INFO PFX +- "set_irq: core 0x%04x, irq %d => %d\n", +- dev->id.coreid, oldirq+2, irq+2); ++ ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.coreid, oldirq+2, irq+2); + } + + static void print_irq(struct ssb_device *dev, unsigned int irq) + { +- int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- ssb_dprintk(KERN_INFO PFX +- "core 0x%04x, irq :", dev->id.coreid); +- for (i = 0; i <= 6; i++) { +- ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" "); +- } +- ssb_dprintk("\n"); ++ ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n", ++ dev->id.coreid, ++ irq_name[0], irq == 0 ? "*" : " ", ++ irq_name[1], irq == 1 ? "*" : " ", ++ irq_name[2], irq == 2 ? "*" : " ", ++ irq_name[3], irq == 3 ? "*" : " ", ++ irq_name[4], irq == 4 ? "*" : " ", ++ irq_name[5], irq == 5 ? "*" : " ", ++ irq_name[6], irq == 6 ? "*" : " "); + } + + static void dump_irq(struct ssb_bus *bus) +@@ -286,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco + if (!mcore->dev) + return; /* We don't have a MIPS core */ + +- ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); ++ ssb_dbg("Initializing MIPS core...\n"); + + bus = mcore->dev->bus; + hz = ssb_clockspeed(bus); +@@ -334,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco + break; + } + } +- ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); ++ ssb_dbg("after irq reconfiguration\n"); + dump_irq(bus); + + ssb_mips_serial_init(mcore); +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci + return -ENODEV; + } + +- ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", +- pci_name(d)); ++ ssb_info("PCI: Fixing up device %s\n", pci_name(d)); + + /* Fix up interrupt lines */ + d->irq = ssb_mips_irq(extpci_core->dev) + 2; +@@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge( + if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) + return; + +- ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); ++ ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev)); + + /* Enable PCI bridge bus mastering and memory space */ + pci_set_master(dev); + if (pcibios_enable_device(dev, ~0) < 0) { +- ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); ++ ssb_err("PCI: SSB bridge enable failed\n"); + return; + } + +@@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge( + + /* Make sure our latency is high enough to handle the devices behind us */ + lat = 168; +- ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", +- pci_name(dev), lat); ++ ssb_info("PCI: Fixing latency timer of device %s to %u\n", ++ pci_name(dev), lat); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); + } + DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); +@@ -323,7 +322,7 @@ static void ssb_pcicore_init_hostmode(st + return; + extpci_core = pc; + +- ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); ++ ssb_dbg("PCIcore in host mode found\n"); + /* Reset devices on the external PCI bus */ + val = SSB_PCICORE_CTL_RST_OE; + val |= SSB_PCICORE_CTL_CLK_OE; +@@ -338,7 +337,7 @@ static void ssb_pcicore_init_hostmode(st + udelay(1); /* Assertion time demanded by the PCI standard */ + + if (pc->dev->bus->has_cardbus_slot) { +- ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); ++ ssb_dbg("CardBus slot detected\n"); + pc->cardbusmode = 1; + /* GPIO 1 resets the bridge */ + ssb_gpio_out(pc->dev->bus, 1, 1); +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -57,9 +57,8 @@ int ssb_watchdog_register(struct ssb_bus + bus->busnumber, &wdt, + sizeof(wdt)); + if (IS_ERR(pdev)) { +- ssb_dprintk(KERN_INFO PFX +- "can not register watchdog device, err: %li\n", +- PTR_ERR(pdev)); ++ ssb_dbg("can not register watchdog device, err: %li\n", ++ PTR_ERR(pdev)); + return PTR_ERR(pdev); + } + +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -275,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c + + err = sdrv->probe(sdev, &sdev->id); + if (err) { +- ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", +- dev_name(sdev->dev)); ++ ssb_err("Failed to thaw device %s\n", ++ dev_name(sdev->dev)); + result = err; + } + ssb_device_put(sdev); +@@ -447,10 +447,9 @@ void ssb_bus_unregister(struct ssb_bus * + + err = ssb_gpio_unregister(bus); + if (err == -EBUSY) +- ssb_dprintk(KERN_ERR PFX "Some GPIOs are still in use.\n"); ++ ssb_dbg("Some GPIOs are still in use\n"); + else if (err) +- ssb_dprintk(KERN_ERR PFX +- "Can not unregister GPIO driver: %i\n", err); ++ ssb_dbg("Can not unregister GPIO driver: %i\n", err); + + ssb_buses_lock(); + ssb_devices_unregister(bus); +@@ -497,8 +496,7 @@ static int ssb_devices_register(struct s + + devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); + if (!devwrap) { +- ssb_printk(KERN_ERR PFX +- "Could not allocate device\n"); ++ ssb_err("Could not allocate device\n"); + err = -ENOMEM; + goto error; + } +@@ -537,9 +535,7 @@ static int ssb_devices_register(struct s + sdev->dev = dev; + err = device_register(dev); + if (err) { +- ssb_printk(KERN_ERR PFX +- "Could not register %s\n", +- dev_name(dev)); ++ ssb_err("Could not register %s\n", dev_name(dev)); + /* Set dev to NULL to not unregister + * dev on error unwinding. */ + sdev->dev = NULL; +@@ -825,10 +821,9 @@ static int ssb_bus_register(struct ssb_b + ssb_mipscore_init(&bus->mipscore); + err = ssb_gpio_init(bus); + if (err == -ENOTSUPP) +- ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n"); ++ ssb_dbg("GPIO driver not activated\n"); + else if (err) +- ssb_dprintk(KERN_ERR PFX +- "Error registering GPIO driver: %i\n", err); ++ ssb_dbg("Error registering GPIO driver: %i\n", err); + err = ssb_fetch_invariants(bus, get_invariants); + if (err) { + ssb_bus_may_powerdown(bus); +@@ -878,11 +873,11 @@ int ssb_bus_pcibus_register(struct ssb_b + + err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "PCI device %s\n", dev_name(&host_pci->dev)); ++ ssb_info("Sonics Silicon Backplane found on PCI device %s\n", ++ dev_name(&host_pci->dev)); + } else { +- ssb_printk(KERN_ERR PFX "Failed to register PCI version" +- " of SSB with error %d\n", err); ++ ssb_err("Failed to register PCI version of SSB with error %d\n", ++ err); + } + + return err; +@@ -903,8 +898,8 @@ int ssb_bus_pcmciabus_register(struct ss + + err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "PCMCIA device %s\n", pcmcia_dev->devname); ++ ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", ++ pcmcia_dev->devname); + } + + return err; +@@ -925,8 +920,8 @@ int ssb_bus_sdiobus_register(struct ssb_ + + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " +- "SDIO device %s\n", sdio_func_id(func)); ++ ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", ++ sdio_func_id(func)); + } + + return err; +@@ -944,8 +939,8 @@ int ssb_bus_ssbbus_register(struct ssb_b + + err = ssb_bus_register(bus, get_invariants, baseaddr); + if (!err) { +- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " +- "address 0x%08lX\n", baseaddr); ++ ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", ++ baseaddr); + } + + return err; +@@ -1339,7 +1334,7 @@ out: + #endif + return err; + error: +- ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); ++ ssb_err("Bus powerdown failed\n"); + goto out; + } + EXPORT_SYMBOL(ssb_bus_may_powerdown); +@@ -1362,7 +1357,7 @@ int ssb_bus_powerup(struct ssb_bus *bus, + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); ++ ssb_err("Bus powerup failed\n"); + return err; + } + EXPORT_SYMBOL(ssb_bus_powerup); +@@ -1470,15 +1465,13 @@ static int __init ssb_modinit(void) + + err = b43_pci_ssb_bridge_init(); + if (err) { +- ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " +- "initialization failed\n"); ++ ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); + /* don't fail SSB init because of this */ + err = 0; + } + err = ssb_gige_init(); + if (err) { +- ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet " +- "driver initialization failed\n"); ++ ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); + /* don't fail SSB init because of this */ + err = 0; + } +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu + } + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); ++ ssb_err("Failed to switch to core %u\n", coreidx); + return -ENODEV; + } + +@@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus * + unsigned long flags; + + #if SSB_VERBOSE_PCICORESWITCH_DEBUG +- ssb_printk(KERN_INFO PFX +- "Switching to %s core, index %d\n", +- ssb_core_name(dev->id.coreid), +- dev->core_index); ++ ssb_info("Switching to %s core, index %d\n", ++ ssb_core_name(dev->id.coreid), ++ dev->core_index); + #endif + + spin_lock_irqsave(&bus->bar_lock, flags); +@@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat + return t[crc ^ data]; + } + ++static void sprom_get_mac(char *mac, const u16 *in) ++{ ++ int i; ++ for (i = 0; i < 3; i++) { ++ *mac++ = in[i] >> 8; ++ *mac++ = in[i]; ++ } ++} ++ + static u8 ssb_sprom_crc(const u16 *sprom, u16 size) + { + int word; +@@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus + u32 spromctl; + u16 size = bus->sprom_size; + +- ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n"); ++ ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n"); + err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl); + if (err) + goto err_ctlreg; +@@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus + err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl); + if (err) + goto err_ctlreg; +- ssb_printk(KERN_NOTICE PFX "[ 0%%"); ++ ssb_notice("[ 0%%"); + msleep(500); + for (i = 0; i < size; i++) { + if (i == size / 4) +- ssb_printk("25%%"); ++ ssb_cont("25%%"); + else if (i == size / 2) +- ssb_printk("50%%"); ++ ssb_cont("50%%"); + else if (i == (size * 3) / 4) +- ssb_printk("75%%"); ++ ssb_cont("75%%"); + else if (i % 2) +- ssb_printk("."); ++ ssb_cont("."); + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); + mmiowb(); + msleep(20); +@@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus + if (err) + goto err_ctlreg; + msleep(500); +- ssb_printk("100%% ]\n"); +- ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); ++ ssb_cont("100%% ]\n"); ++ ssb_notice("SPROM written\n"); + + return 0; + err_ctlreg: +- ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n"); ++ ssb_err("Could not access SPROM control register.\n"); + return err; + } + +@@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_ + return (s8)gain; + } + ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ + static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) + { +- int i; +- u16 v; + u16 loc[3]; + + if (out->revision == 3) /* rev 3 moved MAC */ +@@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss + loc[1] = SSB_SPROM1_ET0MAC; + loc[2] = SSB_SPROM1_ET1MAC; + } +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[0]) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]); + if (out->revision < 3) { /* only rev 1-2 have et0, et1 */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[1]) + i]; +- *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v); +- } +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(loc[2]) + i]; +- *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]); ++ sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]); + } + SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); + SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, +@@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss + SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); + SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); + SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + if (out->revision == 1) + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, + SSB_SPROM1_BINF_CCODE_SHIFT); +@@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss + SSB_SPROM1_ITSSI_A_SHIFT); + SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); + SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); +- if (out->revision >= 2) +- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); + +@@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, + SSB_SPROM1_AGAIN_A, + SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); + } + + /* Revs 4 5 and 8 have partially shared layout */ +@@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss + + static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) + { +- int i; +- u16 v; + u16 il0mac_offset; + + if (out->revision == 4) + il0mac_offset = SSB_SPROM4_IL0MAC; + else + il0mac_offset = SSB_SPROM5_IL0MAC; +- /* extract the MAC address */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(il0mac_offset) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ ++ sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]); ++ + SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); + SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, + SSB_SPROM4_ETHPHY_ET1A_SHIFT); + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + if (out->revision == 4) { + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0); +@@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb + static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) + { + int i; +- u16 v, o; ++ u16 o; + u16 pwr_info_offset[] = { + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 +@@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_ + ARRAY_SIZE(out->core_pwr_info)); + + /* extract the MAC address */ +- for (i = 0; i < 3; i++) { +- v = in[SPOFF(SSB_SPROM8_IL0MAC) + i]; +- *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v); +- } ++ sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]); ++ + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8); + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0); + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0); +@@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus + memset(out, 0, sizeof(*out)); + + out->revision = in[size - 1] & 0x00FF; +- ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); ++ ssb_dbg("SPROM revision %d detected\n", out->revision); + memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ + memset(out->et1mac, 0xFF, 6); + +@@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus + * number stored in the SPROM. + * Always extract r1. */ + out->revision = 1; +- ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); ++ ssb_dbg("SPROM treated as revision %d\n", out->revision); + } + + switch (out->revision) { +@@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus + sprom_extract_r8(out, in); + break; + default: +- ssb_printk(KERN_WARNING PFX "Unsupported SPROM" +- " revision %d detected. Will extract" +- " v1\n", out->revision); ++ ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n", ++ out->revision); + out->revision = 1; + sprom_extract_r123(out, in); + } +@@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_ + u16 *buf; + + if (!ssb_is_sprom_available(bus)) { +- ssb_printk(KERN_ERR PFX "No SPROM available!\n"); ++ ssb_err("No SPROM available!\n"); + return -ENODEV; + } + if (bus->chipco.dev) { /* can be unavailable! */ +@@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_ + } else { + bus->sprom_offset = SSB_SPROM_BASE1; + } +- ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset); ++ ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset); + + buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); + if (!buf) +@@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_ + * available for this device in some other storage */ + err = ssb_fill_sprom_with_fallback(bus, sprom); + if (err) { +- ssb_printk(KERN_WARNING PFX "WARNING: Using" +- " fallback SPROM failed (err %d)\n", +- err); ++ ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n", ++ err); + } else { +- ssb_dprintk(KERN_DEBUG PFX "Using SPROM" +- " revision %d provided by" +- " platform.\n", sprom->revision); ++ ssb_dbg("Using SPROM revision %d provided by platform\n", ++ sprom->revision); + err = 0; + goto out_free; + } +- ssb_printk(KERN_WARNING PFX "WARNING: Invalid" +- " SPROM CRC (corrupt SPROM)\n"); ++ ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n"); + } + } + err = sprom_extract(bus, sprom, buf, bus->sprom_size); +--- a/drivers/ssb/pcmcia.c ++++ b/drivers/ssb/pcmcia.c +@@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); ++ ssb_err("Failed to switch to core %u\n", coreidx); + return err; + } + +@@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu + int err; + + #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG +- ssb_printk(KERN_INFO PFX +- "Switching to %s core, index %d\n", +- ssb_core_name(dev->id.coreid), +- dev->core_index); ++ ssb_info("Switching to %s core, index %d\n", ++ ssb_core_name(dev->id.coreid), ++ dev->core_index); + #endif + + err = ssb_pcmcia_switch_coreidx(bus, dev->core_index); +@@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n"); ++ ssb_err("Failed to switch pcmcia segment\n"); + return err; + } + +@@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st + bool failed = 0; + size_t size = SSB_PCMCIA_SPROM_SIZE; + +- ssb_printk(KERN_NOTICE PFX +- "Writing SPROM. Do NOT turn off the power! " +- "Please stand by...\n"); ++ ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n"); + err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Could not enable SPROM write access.\n"); ++ ssb_notice("Could not enable SPROM write access\n"); + return -EBUSY; + } +- ssb_printk(KERN_NOTICE PFX "[ 0%%"); ++ ssb_notice("[ 0%%"); + msleep(500); + for (i = 0; i < size; i++) { + if (i == size / 4) +- ssb_printk("25%%"); ++ ssb_cont("25%%"); + else if (i == size / 2) +- ssb_printk("50%%"); ++ ssb_cont("50%%"); + else if (i == (size * 3) / 4) +- ssb_printk("75%%"); ++ ssb_cont("75%%"); + else if (i % 2) +- ssb_printk("."); ++ ssb_cont("."); + err = ssb_pcmcia_sprom_write(bus, i, sprom[i]); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Failed to write to SPROM.\n"); ++ ssb_notice("Failed to write to SPROM\n"); + failed = 1; + break; + } + } + err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS); + if (err) { +- ssb_printk(KERN_NOTICE PFX +- "Could not disable SPROM write access.\n"); ++ ssb_notice("Could not disable SPROM write access\n"); + failed = 1; + } + msleep(500); + if (!failed) { +- ssb_printk("100%% ]\n"); +- ssb_printk(KERN_NOTICE PFX "SPROM written.\n"); ++ ssb_cont("100%% ]\n"); ++ ssb_notice("SPROM written\n"); + } + + return failed ? -EBUSY : 0; +@@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants( + return -ENOSPC; /* continue with next entry */ + + error: +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch device invariants: %s\n", + error_description); + return -ENODEV; +@@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE, + ssb_pcmcia_get_mac, sprom); + if (res != 0) { +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch MAC address\n"); + return -ENODEV; + } +@@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb + if ((res == 0) || (res == -ENOSPC)) + return 0; + +- ssb_printk(KERN_ERR PFX ++ ssb_err( + "PCMCIA: Failed to fetch device invariants\n"); + return -ENODEV; + } +@@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus) + + return 0; + error: +- ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n"); ++ ssb_err("Failed to initialize PCMCIA host device\n"); + return err; + } +--- a/drivers/ssb/scan.c ++++ b/drivers/ssb/scan.c +@@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d + chipid_fallback = 0x4401; + break; + default: +- ssb_printk(KERN_ERR PFX +- "PCI-ID not in fallback list\n"); ++ ssb_err("PCI-ID not in fallback list\n"); + } + + return chipid_fallback; +@@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid) + case 0x4704: + return 9; + default: +- ssb_printk(KERN_ERR PFX +- "CHIPID not in nrcores fallback list\n"); ++ ssb_err("CHIPID not in nrcores fallback list\n"); + } + + return 1; +@@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus, + bus->chip_package = 0; + } + } +- ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and " +- "package 0x%02X\n", bus->chip_id, bus->chip_rev, +- bus->chip_package); ++ ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n", ++ bus->chip_id, bus->chip_rev, bus->chip_package); + if (!bus->nr_devices) + bus->nr_devices = chipid_to_nrcores(bus->chip_id); + if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { +- ssb_printk(KERN_ERR PFX +- "More than %d ssb cores found (%d)\n", +- SSB_MAX_NR_CORES, bus->nr_devices); ++ ssb_err("More than %d ssb cores found (%d)\n", ++ SSB_MAX_NR_CORES, bus->nr_devices); + goto err_unmap; + } + if (bus->bustype == SSB_BUSTYPE_SSB) { +@@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + nr_80211_cores++; + if (nr_80211_cores > 1) { + if (!we_support_multiple_80211_cores(bus)) { +- ssb_dprintk(KERN_INFO PFX "Ignoring additional " +- "802.11 core\n"); ++ ssb_dbg("Ignoring additional 802.11 core\n"); + continue; + } + } +@@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + case SSB_DEV_EXTIF: + #ifdef CONFIG_SSB_DRIVER_EXTIF + if (bus->extif.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple EXTIFs found\n"); ++ ssb_warn("WARNING: Multiple EXTIFs found\n"); + break; + } + bus->extif.dev = dev; +@@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + break; + case SSB_DEV_CHIPCOMMON: + if (bus->chipco.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple ChipCommon found\n"); ++ ssb_warn("WARNING: Multiple ChipCommon found\n"); + break; + } + bus->chipco.dev = dev; +@@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + case SSB_DEV_MIPS_3302: + #ifdef CONFIG_SSB_DRIVER_MIPS + if (bus->mipscore.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple MIPS cores found\n"); ++ ssb_warn("WARNING: Multiple MIPS cores found\n"); + break; + } + bus->mipscore.dev = dev; +@@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus, + } + } + if (bus->pcicore.dev) { +- ssb_printk(KERN_WARNING PFX +- "WARNING: Multiple PCI(E) cores found\n"); ++ ssb_warn("WARNING: Multiple PCI(E) cores found\n"); + break; + } + bus->pcicore.dev = dev; +--- a/drivers/ssb/sprom.c ++++ b/drivers/ssb/sprom.c +@@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_ + goto out_kfree; + err = ssb_devices_freeze(bus, &freeze); + if (err) { +- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); ++ ssb_err("SPROM write: Could not freeze all devices\n"); + goto out_unlock; + } + res = sprom_write(bus, sprom); + err = ssb_devices_thaw(&freeze); + if (err) +- ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); ++ ssb_err("SPROM write: Could not thaw all devices\n"); + out_unlock: + mutex_unlock(&bus->sprom_mutex); + out_kfree: +--- a/drivers/ssb/ssb_private.h ++++ b/drivers/ssb/ssb_private.h +@@ -9,16 +9,27 @@ + #define PFX "ssb: " + + #ifdef CONFIG_SSB_SILENT +-# define ssb_printk(fmt, x...) do { /* nothing */ } while (0) ++# define ssb_printk(fmt, ...) \ ++ do { if (0) printk(fmt, ##__VA_ARGS__); } while (0) + #else +-# define ssb_printk printk ++# define ssb_printk(fmt, ...) \ ++ printk(fmt, ##__VA_ARGS__) + #endif /* CONFIG_SSB_SILENT */ + ++#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__) ++#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__) ++#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__) ++#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__) ++#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__) ++#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__) ++ + /* dprintk: Debugging printk; vanishes for non-debug compilation */ + #ifdef CONFIG_SSB_DEBUG +-# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x) ++# define ssb_dbg(fmt, ...) \ ++ ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__) + #else +-# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0) ++# define ssb_dbg(fmt, ...) \ ++ do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0) + #endif + + #ifdef CONFIG_SSB_DEBUG +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -26,9 +26,9 @@ struct ssb_sprom_core_pwr_info { + + struct ssb_sprom { + u8 revision; +- u8 il0mac[6]; /* MAC address for 802.11b/g */ +- u8 et0mac[6]; /* MAC address for Ethernet */ +- u8 et1mac[6]; /* MAC address for 802.11a */ ++ u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ ++ u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ ++ u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ + u8 et0phyaddr; /* MII address for enet0 */ + u8 et1phyaddr; /* MII address for enet1 */ + u8 et0mdcport; /* MDIO for enet0 */ +@@ -340,13 +340,61 @@ enum ssb_bustype { + #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */ + #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */ + /* board_type */ ++#define SSB_BOARD_BCM94301CB 0x0406 ++#define SSB_BOARD_BCM94301MP 0x0407 ++#define SSB_BOARD_BU4309 0x040A ++#define SSB_BOARD_BCM94309CB 0x040B ++#define SSB_BOARD_BCM4309MP 0x040C ++#define SSB_BOARD_BU4306 0x0416 + #define SSB_BOARD_BCM94306MP 0x0418 + #define SSB_BOARD_BCM4309G 0x0421 + #define SSB_BOARD_BCM4306CB 0x0417 +-#define SSB_BOARD_BCM4309MP 0x040C ++#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ ++#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */ ++#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */ ++#define SSB_BOARD_BU4704SD 0x042E /* with sdram */ ++#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */ ++#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */ ++#define SSB_BOARD_BU4318 0x0447 ++#define SSB_BOARD_CB4318 0x0448 ++#define SSB_BOARD_MPG4318 0x0449 + #define SSB_BOARD_MP4318 0x044A +-#define SSB_BOARD_BU4306 0x0416 +-#define SSB_BOARD_BU4309 0x040A ++#define SSB_BOARD_SD4318 0x044B ++#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */ ++#define SSB_BOARD_BCM94303MP 0x044E ++#define SSB_BOARD_BCM94306MPM 0x0450 ++#define SSB_BOARD_BCM94306MPL 0x0453 ++#define SSB_BOARD_PC4303 0x0454 /* pcmcia */ ++#define SSB_BOARD_BCM94306MPLNA 0x0457 ++#define SSB_BOARD_BCM94306MPH 0x045B ++#define SSB_BOARD_BCM94306PCIV 0x045C ++#define SSB_BOARD_BCM94318MPGH 0x0463 ++#define SSB_BOARD_BU4311 0x0464 ++#define SSB_BOARD_BCM94311MC 0x0465 ++#define SSB_BOARD_BCM94311MCAG 0x0466 ++/* 4321 boards */ ++#define SSB_BOARD_BU4321 0x046B ++#define SSB_BOARD_BU4321E 0x047C ++#define SSB_BOARD_MP4321 0x046C ++#define SSB_BOARD_CB2_4321 0x046D ++#define SSB_BOARD_CB2_4321_AG 0x0066 ++#define SSB_BOARD_MC4321 0x046E ++/* 4325 boards */ ++#define SSB_BOARD_BCM94325DEVBU 0x0490 ++#define SSB_BOARD_BCM94325BGABU 0x0491 ++#define SSB_BOARD_BCM94325SDGWB 0x0492 ++#define SSB_BOARD_BCM94325SDGMDL 0x04AA ++#define SSB_BOARD_BCM94325SDGMDL2 0x04C6 ++#define SSB_BOARD_BCM94325SDGMDL3 0x04C9 ++#define SSB_BOARD_BCM94325SDABGWBA 0x04E1 ++/* 4322 boards */ ++#define SSB_BOARD_BCM94322MC 0x04A4 ++#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */ ++#define SSB_BOARD_BCM94322HM 0x04B0 ++#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */ ++/* 4312 boards */ ++#define SSB_BOARD_BU4312 0x048A ++#define SSB_BOARD_BCM4312MCGSG 0x04B5 + /* chip_package */ + #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ + #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */ +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -289,11 +289,11 @@ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8 + #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 diff --git a/target/linux/generic/patches-3.9/021-bcma_backport.patch b/target/linux/generic/patches-3.9/021-bcma_backport.patch deleted file mode 100644 index 2885aea389..0000000000 --- a/target/linux/generic/patches-3.9/021-bcma_backport.patch +++ /dev/null @@ -1,140 +0,0 @@ ---- a/drivers/bcma/driver_chipcommon.c -+++ b/drivers/bcma/driver_chipcommon.c -@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked - return value; - } - --static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) -+u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) - { - if (cc->capabilities & BCMA_CC_CAP_PMU) - return bcma_pmu_get_alp_clock(cc); - - return 20000000; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); - - static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) - { -@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv - - return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); - - u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d - - return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); - - /* - * If the bit is set to 0, chipcommon controlls this GPIO, ---- a/drivers/bcma/driver_chipcommon_pmu.c -+++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d - struct bcma_bus *bus = cc->core->bus; - - switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM4313: -+ case BCMA_CHIP_ID_BCM43224: -+ case BCMA_CHIP_ID_BCM43225: -+ case BCMA_CHIP_ID_BCM43227: -+ case BCMA_CHIP_ID_BCM43228: -+ case BCMA_CHIP_ID_BCM4331: -+ case BCMA_CHIP_ID_BCM43421: -+ case BCMA_CHIP_ID_BCM43428: -+ case BCMA_CHIP_ID_BCM43431: - case BCMA_CHIP_ID_BCM4716: -- case BCMA_CHIP_ID_BCM4748: - case BCMA_CHIP_ID_BCM47162: -- case BCMA_CHIP_ID_BCM4313: -- case BCMA_CHIP_ID_BCM5357: -+ case BCMA_CHIP_ID_BCM4748: - case BCMA_CHIP_ID_BCM4749: -+ case BCMA_CHIP_ID_BCM5357: - case BCMA_CHIP_ID_BCM53572: -+ case BCMA_CHIP_ID_BCM6362: - /* always 20Mhz */ - return 20000 * 1000; -- case BCMA_CHIP_ID_BCM5356: - case BCMA_CHIP_ID_BCM4706: -+ case BCMA_CHIP_ID_BCM5356: - /* always 25Mhz */ - return 25000 * 1000; -+ case BCMA_CHIP_ID_BCM43460: -+ case BCMA_CHIP_ID_BCM4352: -+ case BCMA_CHIP_ID_BCM4360: -+ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) -+ return 40000 * 1000; -+ else -+ return 20000 * 1000; - default: - bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); -@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); - -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM4331: -@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, - 0x03000a08); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM43224: -@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, - 0x88888815); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - - case BCMA_CHIP_ID_BCM4716: -@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - 0x88888815); - } - -- tmp = 3 << 9; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; - break; - - case BCMA_CHIP_ID_BCM43227: -@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct - bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, - 0x88888815); - } -- tmp = 1 << 10; -+ tmp = BCMA_CC_PMU_CTL_PLL_UPD; - break; - default: - bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", ---- a/include/linux/bcma/bcma_driver_chipcommon.h -+++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -104,6 +104,7 @@ - #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ - #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ - #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ -+#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 - #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ - #define BCMA_CC_JCMD_START 0x80000000 - #define BCMA_CC_JCMD_BUSY 0x80000000 -@@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct - - extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); - -+extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); -+ - void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); - - u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); diff --git a/target/linux/generic/patches-3.9/025-bcma_backport.patch b/target/linux/generic/patches-3.9/025-bcma_backport.patch index 489dc20188..a1a1ebc0f5 100644 --- a/target/linux/generic/patches-3.9/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.9/025-bcma_backport.patch @@ -1,3 +1,234 @@ +--- a/drivers/bcma/core.c ++++ b/drivers/bcma/core.c +@@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_devic + if (i) + bcma_err(core->bus, "PLL enable timeout\n"); + } else { +- bcma_warn(core->bus, "Disabling PLL not supported yet!\n"); ++ /* ++ * Mask the PLL but don't wait for it to be disabled. PLL may be ++ * shared between cores and will be still up if there is another ++ * core using it. ++ */ ++ bcma_mask32(core, BCMA_CLKCTLST, ~req); ++ bcma_read32(core, BCMA_CLKCTLST); + } + } + EXPORT_SYMBOL_GPL(bcma_core_pll_ctl); +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked + return value; + } + +-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) ++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) + { + if (cc->capabilities & BCMA_CC_CAP_PMU) + return bcma_pmu_get_alp_clock(cc); + + return 20000000; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); + + static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) + { +@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + + return res; + } ++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); + + /* + * If the bit is set to 0, chipcommon controlls this GPIO, +--- a/drivers/bcma/driver_chipcommon_pmu.c ++++ b/drivers/bcma/driver_chipcommon_pmu.c +@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d + struct bcma_bus *bus = cc->core->bus; + + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4313: ++ case BCMA_CHIP_ID_BCM43224: ++ case BCMA_CHIP_ID_BCM43225: ++ case BCMA_CHIP_ID_BCM43227: ++ case BCMA_CHIP_ID_BCM43228: ++ case BCMA_CHIP_ID_BCM4331: ++ case BCMA_CHIP_ID_BCM43421: ++ case BCMA_CHIP_ID_BCM43428: ++ case BCMA_CHIP_ID_BCM43431: + case BCMA_CHIP_ID_BCM4716: +- case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM47162: +- case BCMA_CHIP_ID_BCM4313: +- case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4748: + case BCMA_CHIP_ID_BCM4749: ++ case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: ++ case BCMA_CHIP_ID_BCM6362: + /* always 20Mhz */ + return 20000 * 1000; +- case BCMA_CHIP_ID_BCM5356: + case BCMA_CHIP_ID_BCM4706: ++ case BCMA_CHIP_ID_BCM5356: + /* always 25Mhz */ + return 25000 * 1000; ++ case BCMA_CHIP_ID_BCM43460: ++ case BCMA_CHIP_ID_BCM4352: ++ case BCMA_CHIP_ID_BCM4360: ++ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ) ++ return 40000 * 1000; ++ else ++ return 20000 * 1000; + default: + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); +@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); + +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4331: +@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, + 0x03000a08); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM43224: +@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + + case BCMA_CHIP_ID_BCM4716: +@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + 0x88888815); + } + +- tmp = 3 << 9; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; + break; + + case BCMA_CHIP_ID_BCM43227: +@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, + 0x88888815); + } +- tmp = 1 << 10; ++ tmp = BCMA_CC_PMU_CTL_PLL_UPD; + break; + default: + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -120,6 +120,11 @@ static int bcma_register_cores(struct bc + continue; + } + ++ /* Only first GMAC core on BCM4706 is connected and working */ ++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT && ++ core->core_unit > 0) ++ continue; ++ + core->dev.release = bcma_release_core_dev; + core->dev.bus = &bcma_bus_type; + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id); +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct + addr); + } + +-static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr) ++static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = readl(*eromptr); + (*eromptr)++; + return ent; + } + +-static void bcma_erom_push_ent(u32 **eromptr) ++static void bcma_erom_push_ent(u32 __iomem **eromptr) + { + (*eromptr)--; + } + +-static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr) ++static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + if (!(ent & SCAN_ER_VALID)) +@@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_ + return ent; + } + +-static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr) ++static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + bcma_erom_push_ent(eromptr); + return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)); + } + +-static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr) ++static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + bcma_erom_push_ent(eromptr); +@@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct b + ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE)); + } + +-static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr) ++static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent; + while (1) { +@@ -189,7 +189,7 @@ static void bcma_erom_skip_component(str + bcma_erom_push_ent(eromptr); + } + +-static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr) ++static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr) + { + u32 ent = bcma_erom_get_ent(bus, eromptr); + if (!(ent & SCAN_ER_VALID)) +@@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct + return ent; + } + +-static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr, ++static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, + u32 type, u8 port) + { + u32 addrl, addrh, sizel, sizeh = 0; +--- a/drivers/bcma/sprom.c ++++ b/drivers/bcma/sprom.c +@@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct + } + + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, ~0, 0); + + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0, + SSB_SPROM4_TXPID2G0_SHIFT); --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h @@ -134,6 +134,7 @@ struct bcma_host_ops { @@ -8,19 +239,78 @@ #define BCMA_CORE_DEFAULT 0xFFF #define BCMA_MAX_NR_CORES 16 ---- a/include/linux/bcma/bcma_regs.h -+++ b/include/linux/bcma/bcma_regs.h -@@ -37,6 +37,7 @@ - #define BCMA_IOST_BIST_DONE 0x8000 - #define BCMA_RESET_CTL 0x0800 - #define BCMA_RESET_CTL_RESET 0x0001 -+#define BCMA_RESET_ST 0x0804 +@@ -173,6 +174,60 @@ struct bcma_host_ops { + #define BCMA_CHIP_ID_BCM53572 53572 + #define BCMA_PKG_ID_BCM47188 9 - /* BCMA PCI config space registers. */ - #define BCMA_PCI_PMCSR 0x44 ++/* Board types (on PCI usually equals to the subsystem dev id) */ ++/* BCM4313 */ ++#define BCMA_BOARD_TYPE_BCM94313BU 0X050F ++#define BCMA_BOARD_TYPE_BCM94313HM 0X0510 ++#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511 ++#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C ++/* BCM4716 */ ++#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD ++/* BCM43224 */ ++#define BCMA_BOARD_TYPE_BCM943224X21 0X056E ++#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1 ++#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9 ++#define BCMA_BOARD_TYPE_BCM943224M93 0X008B ++#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090 ++#define BCMA_BOARD_TYPE_BCM943224X16 0X0093 ++#define BCMA_BOARD_TYPE_BCM94322X9 0X008D ++#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E ++/* BCM43228 */ ++#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540 ++#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541 ++#define BCMA_BOARD_TYPE_BCM943228BU 0X0542 ++#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543 ++#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544 ++#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545 ++#define BCMA_BOARD_TYPE_BCM943228SD 0X0573 ++/* BCM4331 */ ++#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6 ++#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4 ++#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E ++#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4 ++#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC ++#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED ++#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF ++#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF ++#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5 ++#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4 ++#define BCMA_BOARD_TYPE_BCM94331BU 0X0523 ++#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524 ++#define BCMA_BOARD_TYPE_BCM94331MC 0X0525 ++#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526 ++#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527 ++#define BCMA_BOARD_TYPE_BCM94331HM 0X0574 ++#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B ++#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9 ++#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6 ++#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA ++/* BCM53572 */ ++#define BCMA_BOARD_TYPE_BCM953572BU 0X058D ++#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E ++#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F ++#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590 ++/* BCM43142 */ ++#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0 ++ + struct bcma_device { + struct bcma_bus *bus; + struct bcma_device_id id; --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -316,6 +316,9 @@ +@@ -104,6 +104,7 @@ + #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ + #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ + #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ ++#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 + #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ + #define BCMA_CC_JCMD_START 0x80000000 + #define BCMA_CC_JCMD_BUSY 0x80000000 +@@ -315,6 +316,9 @@ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 @@ -30,3 +320,22 @@ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ +@@ -607,6 +611,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct + + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + ++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); ++ + void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); + + u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -37,6 +37,7 @@ + #define BCMA_IOST_BIST_DONE 0x8000 + #define BCMA_RESET_CTL 0x0800 + #define BCMA_RESET_CTL_RESET 0x0001 ++#define BCMA_RESET_ST 0x0804 + + /* BCMA PCI config space registers. */ + #define BCMA_PCI_PMCSR 0x44 |