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-rw-r--r--target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch846
1 files changed, 846 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch
new file mode 100644
index 0000000000..2667bd636e
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch
@@ -0,0 +1,846 @@
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -8,6 +8,8 @@
+ #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/mfd/qcom-rpm.h>
++#include <dt-bindings/clock/qcom,rpmcc.h>
+
+ / {
+ #address-cells = <1>;
+@@ -28,6 +30,16 @@
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
++ clocks = <&kraitcc 0>, <&kraitcc 4>;
++ clock-names = "cpu", "l2";
++ clock-latency = <100000>;
++ cpu-supply = <&smb208_s2a>;
++ operating-points-v2 = <&opp_table0>;
++ voltage-tolerance = <5>;
++ cooling-min-state = <0>;
++ cooling-max-state = <10>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ cpu1: cpu@1 {
+@@ -38,14 +50,350 @@
+ next-level-cache = <&L2>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
++ clocks = <&kraitcc 1>, <&kraitcc 4>;
++ clock-names = "cpu", "l2";
++ clock-latency = <100000>;
++ cpu-supply = <&smb208_s2b>;
++ operating-points-v2 = <&opp_table0>;
++ voltage-tolerance = <5>;
++ cooling-min-state = <0>;
++ cooling-max-state = <10>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SPC>;
++ };
++
++ idle-states {
++ CPU_SPC: spc {
++ compatible = "qcom,idle-state-spc";
++ status = "disabled";
++ entry-latency-us = <400>;
++ exit-latency-us = <900>;
++ min-residency-us = <3000>;
++ };
+ };
++ };
+
+- L2: l2-cache {
+- compatible = "cache";
+- cache-level = <2>;
++ opp_table_l2: opp_table_l2 {
++ compatible = "operating-points-v2";
++
++ opp-384000000 {
++ opp-hz = /bits/ 64 <384000000>;
++ opp-microvolt = <1100000>;
++ clock-latency-ns = <100000>;
++ opp-level = <0>;
++ };
++
++ opp-1000000000 {
++ opp-hz = /bits/ 64 <1000000000>;
++ opp-microvolt = <1100000>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <1150000>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
++ };
++ };
++
++ opp_table0: opp_table0 {
++ compatible = "operating-points-v2-kryo-cpu";
++ nvmem-cells = <&speedbin_efuse>;
++
++ /*
++ * Voltage thresholds are <target min max>
++ */
++ opp-384000000 {
++ opp-hz = /bits/ 64 <384000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
++ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
++ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <0>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
++ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-800000000 {
++ opp-hz = /bits/ 64 <800000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
++ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-1000000000 {
++ opp-hz = /bits/ 64 <1000000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
++ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
++ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
++ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
++ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
++ };
++
++ opp-1400000000 {
++ opp-hz = /bits/ 64 <1400000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
++ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
++ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
+ };
+ };
+
++ thermal-zones {
++ tsens_tz_sensor0 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 0>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor1 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 1>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor2 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 2>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor3 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 3>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor4 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 4>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor5 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 5>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor6 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 6>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor7 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 7>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor8 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 8>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor9 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 9>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++
++ tsens_tz_sensor10 {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsens 10>;
++
++ trips {
++ cpu-critical {
++ temperature = <105000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++
++ cpu-hot {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "hot";
++ };
++ };
++ };
++ };
++
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>;
+@@ -93,6 +441,15 @@
+ };
+ };
+
++ fab-scaling {
++ compatible = "qcom,fab-scaling";
++ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
++ clock-names = "apps-fab-clk", "ddr-fab-clk";
++ fab_freq_high = <533000000>;
++ fab_freq_nominal = <400000000>;
++ cpu_freq_threshold = <1000000000>;
++ };
++
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
+@@ -120,6 +477,78 @@
+ reg-names = "lpass-lpaif";
+ };
+
++ L2: l2-cache {
++ compatible = "qcom,krait-cache", "cache";
++ cache-level = <2>;
++ qcom,saw = <&saw_l2>;
++
++ clocks = <&kraitcc 4>;
++ clock-names = "l2";
++ l2-supply = <&smb208_s1a>;
++ operating-points-v2 = <&opp_table_l2>;
++ };
++
++ rpm: rpm@108000 {
++ compatible = "qcom,rpm-ipq8064";
++ reg = <0x108000 0x1000>;
++ qcom,ipc = <&l2cc 0x8 2>;
++
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "ack", "err", "wakeup";
++
++ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
++ clock-names = "ram";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rpmcc: clock-controller {
++ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
++ #clock-cells = <1>;
++ };
++
++ regulators {
++ compatible = "qcom,rpm-smb208-regulators";
++
++ smb208_s1a: s1a {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s1b: s1b {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2a: s2a {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2b: s2b {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++ };
++ };
++
++ rng@1a500000 {
++ compatible = "qcom,prng";
++ reg = <0x1a500000 0x200>;
++ clocks = <&gcc PRNG_CLK>;
++ clock-names = "core";
++ };
++
+ qcom_pinmux: pinmux@800000 {
+ compatible = "qcom,ipq8064-pinctrl";
+ reg = <0x800000 0x4000>;
+@@ -160,6 +589,15 @@
+ };
+ };
+
++ i2c4_pins: i2c4_pinmux {
++ mux {
++ pins = "gpio12", "gpio13";
++ function = "gsbi4";
++ drive-strength = <12>;
++ bias-disable;
++ };
++ };
++
+ spi_pins: spi_pins {
+ mux {
+ pins = "gpio18", "gpio19", "gpio21";
+@@ -169,6 +607,53 @@
+ };
+ };
+
++ nand_pins: nand_pins {
++ disable {
++ pins = "gpio34", "gpio35", "gpio36",
++ "gpio37", "gpio38";
++ function = "nand";
++ drive-strength = <10>;
++ bias-disable;
++ };
++
++ pullups {
++ pins = "gpio39";
++ function = "nand";
++ drive-strength = <10>;
++ bias-pull-up;
++ };
++
++ hold {
++ pins = "gpio40", "gpio41", "gpio42",
++ "gpio43", "gpio44", "gpio45",
++ "gpio46", "gpio47";
++ function = "nand";
++ drive-strength = <10>;
++ bias-bus-hold;
++ };
++ };
++
++ mdio0_pins: mdio0_pins {
++ mux {
++ pins = "gpio0", "gpio1";
++ function = "mdio";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ rgmii2_pins: rgmii2_pins {
++ mux {
++ pins = "gpio27", "gpio28", "gpio29",
++ "gpio30", "gpio31", "gpio32",
++ "gpio51", "gpio52", "gpio59",
++ "gpio60", "gpio61", "gpio62";
++ function = "rgmii2";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
+ leds_pins: leds_pins {
+ mux {
+ pins = "gpio7", "gpio8", "gpio9",
+@@ -231,6 +716,17 @@
+ clock-output-names = "acpu1_aux";
+ };
+
++ l2cc: clock-controller@2011000 {
++ compatible = "qcom,kpss-gcc", "syscon";
++ reg = <0x2011000 0x1000>;
++ clock-output-names = "acpu_l2_aux";
++ };
++
++ kraitcc: clock-controller {
++ compatible = "qcom,krait-cc-v1";
++ #clock-cells = <1>;
++ };
++
+ saw0: regulator@2089000 {
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+@@ -243,6 +739,52 @@
+ regulator;
+ };
+
++ saw_l2: regulator@02012000 {
++ compatible = "qcom,saw2", "syscon";
++ reg = <0x02012000 0x1000>;
++ regulator;
++ };
++
++ sic_non_secure: sic-non-secure@12100000 {
++ compatible = "syscon";
++ reg = <0x12100000 0x10000>;
++ };
++
++ gsbi1: gsbi@12440000 {
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <1>;
++ reg = <0x12440000 0x100>;
++ clocks = <&gcc GSBI1_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ status = "disabled";
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi1_serial: serial@12450000 {
++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++ reg = <0x12450000 0x100>,
++ <0x12400000 0x03>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++ };
++
++ gsbi1_i2c: i2c@12460000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x12460000 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
+ gsbi2: gsbi@12480000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
+@@ -368,6 +910,33 @@
+ };
+ };
+
++ gsbi6: gsbi@16500000 {
++ status = "disabled";
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <6>;
++ reg = <0x16500000 0x100>;
++ clocks = <&gcc GSBI6_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi6_i2c: i2c@16580000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16580000 0x1000>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+@@ -389,6 +958,19 @@
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
++
++ gsbi7_i2c: i2c@16680000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16680000 0x1000>;
++ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
+ };
+
+ sata_phy: sata-phy@1b400000 {
+@@ -478,6 +1060,95 @@
+ #reset-cells = <1>;
+ };
+
++ sfpb_mutex_block: syscon@1200600 {
++ compatible = "syscon";
++ reg = <0x01200600 0x100>;
++ };
++
++ hs_phy_0: hs_phy_0 {
++ compatible = "qcom,ipq806x-usb-phy-hs";
++ reg = <0x110f8800 0x30>;
++ clocks = <&gcc USB30_0_UTMI_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ ss_phy_0: ss_phy_0 {
++ compatible = "qcom,ipq806x-usb-phy-ss";
++ reg = <0x110f8830 0x30>;
++ clocks = <&gcc USB30_0_MASTER_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ usb3_0: usb3@110f8800 {
++ compatible = "qcom,dwc3", "syscon";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x110f8800 0x8000>;
++ clocks = <&gcc USB30_0_MASTER_CLK>;
++ clock-names = "core";
++
++ ranges;
++
++ resets = <&gcc USB30_0_MASTER_RESET>;
++ reset-names = "master";
++
++ status = "disabled";
++
++ dwc3_0: dwc3@11000000 {
++ compatible = "snps,dwc3";
++ reg = <0x11000000 0xcd00>;
++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&hs_phy_0>, <&ss_phy_0>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ snps,dis_u3_susphy_quirk;
++ };
++ };
++
++ hs_phy_1: hs_phy_1 {
++ compatible = "qcom,ipq806x-usb-phy-hs";
++ reg = <0x100f8800 0x30>;
++ clocks = <&gcc USB30_1_UTMI_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ ss_phy_1: ss_phy_1 {
++ compatible = "qcom,ipq806x-usb-phy-ss";
++ reg = <0x100f8830 0x30>;
++ clocks = <&gcc USB30_1_MASTER_CLK>;
++ clock-names = "ref";
++ #phy-cells = <0>;
++ };
++
++ usb3_1: usb3@100f8800 {
++ compatible = "qcom,dwc3", "syscon";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x100f8800 0x8000>;
++ clocks = <&gcc USB30_1_MASTER_CLK>;
++ clock-names = "core";
++
++ ranges;
++
++ resets = <&gcc USB30_1_MASTER_RESET>;
++ reset-names = "master";
++
++ status = "disabled";
++
++ dwc3_1: dwc3@10000000 {
++ compatible = "snps,dwc3";
++ reg = <0x10000000 0xcd00>;
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&hs_phy_1>, <&ss_phy_1>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ snps,dis_u3_susphy_quirk;
++ };
++ };
++
+ pcie0: pci@1b500000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b500000 0x1000
+@@ -739,6 +1410,59 @@
+ status = "disabled";
+ };
+
++ adm_dma: dma@18300000 {
++ compatible = "qcom,adm";
++ reg = <0x18300000 0x100000>;
++ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++
++ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
++ clock-names = "core", "iface";
++
++ resets = <&gcc ADM0_RESET>,
++ <&gcc ADM0_PBUS_RESET>,
++ <&gcc ADM0_C0_RESET>,
++ <&gcc ADM0_C1_RESET>,
++ <&gcc ADM0_C2_RESET>;
++ reset-names = "clk", "pbus", "c0", "c1", "c2";
++ qcom,ee = <0>;
++
++ status = "disabled";
++ };
++
++ nand_controller: nand-controller@1ac00000 {
++ compatible = "qcom,ipq806x-nand";
++ reg = <0x1ac00000 0x800>;
++
++ clocks = <&gcc EBI2_CLK>,
++ <&gcc EBI2_AON_CLK>;
++ clock-names = "core", "aon";
++
++ dmas = <&adm_dma 3>;
++ dma-names = "rxtx";
++ qcom,cmd-crci = <15>;
++ qcom,data-crci = <3>;
++
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ mdio0: mdio@37000000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ compatible = "qcom,ipq8064-mdio", "syscon";
++ reg = <0x37000000 0x200000>;
++ resets = <&gcc GMAC_CORE1_RESET>;
++ reset-names = "stmmaceth";
++ clocks = <&gcc GMAC_CORE1_CLK>;
++ clock-names = "stmmaceth";
++
++ status = "disabled";
++ };
++
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+@@ -814,4 +1538,17 @@
+ };
+ };
+ };
++
++ sfpb_mutex: sfpb-mutex {
++ compatible = "qcom,sfpb-mutex";
++ syscon = <&sfpb_mutex_block 4 4>;
++
++ #hwlock-cells = <1>;
++ };
++
++ smem {
++ compatible = "qcom,smem";
++ memory-region = <&smem>;
++ hwlocks = <&sfpb_mutex 3>;
++ };
+ };
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-04 20:09:18 +0000