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Diffstat (limited to 'target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch')
-rw-r--r--target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch372
1 files changed, 372 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
new file mode 100644
index 0000000000..d1e047cabf
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
@@ -0,0 +1,372 @@
+From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:23:38 +0100
+Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
+
+Add missing clk and reset needed for nss additional core and crypto
+engine.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++
+ include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
+ include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
+ 3 files changed, 259 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
+
+ static struct pll_freq_tbl pll18_freq_tbl[] = {
+ NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
++ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
+ NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
++ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
+ };
+
+ static struct clk_pll pll18 = {
+@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
+ },
+ };
+
++static struct clk_pll pll11 = {
++ .l_reg = 0x3184,
++ .m_reg = 0x3188,
++ .n_reg = 0x318c,
++ .config_reg = 0x3194,
++ .mode_reg = 0x3180,
++ .status_reg = 0x3198,
++ .status_bit = 16,
++ .clkr.hw.init = &(struct clk_init_data){
++ .name = "pll11",
++ .parent_names = (const char *[]){ "pxo" },
++ .num_parents = 1,
++ .ops = &clk_pll_ops,
++ },
++};
++
+ enum {
+ P_PXO,
+ P_PLL8,
+@@ -253,6 +271,7 @@ enum {
+ P_CXO,
+ P_PLL14,
+ P_PLL18,
++ P_PLL11,
+ };
+
+ static const struct parent_map gcc_pxo_pll8_map[] = {
+@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
+ "pll18",
+ };
+
++static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
++ { P_PXO, 0 },
++ { P_PLL8, 4 },
++ { P_PLL0, 2 },
++ { P_PLL14, 5 },
++ { P_PLL18, 1 },
++ { P_PLL11, 3 },
++};
++
++static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
++ "pxo",
++ "pll8_vote",
++ "pll0_vote",
++ "pll14",
++ "pll18",
++ "pll11"
++};
++
++static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
++ { P_PXO, 0 },
++ { P_PLL3, 6 },
++ { P_PLL0, 2 },
++ { P_PLL14, 5 },
++ { P_PLL18, 1 },
++ { P_PLL11, 3 },
++};
++
++static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
++ "pxo",
++ "pll3",
++ "pll0_vote",
++ "pll14",
++ "pll18",
++ "pll11"
++};
++
+ static struct freq_tbl clk_tbl_gsbi_uart[] = {
+ { 1843200, P_PLL8, 2, 6, 625 },
+ { 3686400, P_PLL8, 2, 12, 625 },
+@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
+ { 20210000, P_PLL8, 1, 1, 19 },
+ { 24000000, P_PLL8, 4, 1, 4 },
+ { 48000000, P_PLL8, 4, 1, 2 },
++ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
+ { 64000000, P_PLL8, 3, 1, 2 },
+ { 96000000, P_PLL8, 4, 0, 0 },
+ { 192000000, P_PLL8, 2, 0, 0 },
+@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss
+ { 110000000, P_PLL18, 1, 1, 5 },
+ { 275000000, P_PLL18, 2, 0, 0 },
+ { 550000000, P_PLL18, 1, 0, 0 },
++ { 600000000, P_PLL18, 1, 0, 0 },
+ { 733000000, P_PLL18, 1, 0, 0 },
++ { 800000000, P_PLL18, 1, 0, 0 },
+ { }
+ };
+
+@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
+ },
+ };
+
++static const struct freq_tbl clk_tbl_ce5_core[] = {
++ { 150000000, P_PLL3, 8, 1, 1 },
++ { 213200000, P_PLL11, 5, 1, 1 },
++ { }
++};
++
++static struct clk_dyn_rcg ce5_core_src = {
++ .ns_reg[0] = 0x36C4,
++ .ns_reg[1] = 0x36C8,
++ .bank_reg = 0x36C0,
++ .s[0] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
++ },
++ .s[1] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
++ },
++ .p[0] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .p[1] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .mux_sel_bit = 0,
++ .freq_tbl = clk_tbl_ce5_core,
++ .clkr = {
++ .enable_reg = 0x36C0,
++ .enable_mask = BIT(1),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_core_src",
++ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
++ .num_parents = 6,
++ .ops = &clk_dyn_rcg_ops,
++ },
++ },
++};
++
++static struct clk_branch ce5_core_clk = {
++ .halt_reg = 0x2FDC,
++ .halt_bit = 5,
++ .hwcg_reg = 0x36CC,
++ .hwcg_bit = 6,
++ .clkr = {
++ .enable_reg = 0x36CC,
++ .enable_mask = BIT(4),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_core_clk",
++ .parent_names = (const char *[]){
++ "ce5_core_src",
++ },
++ .num_parents = 1,
++ .ops = &clk_branch_ops,
++ .flags = CLK_SET_RATE_PARENT,
++ },
++ },
++};
++
++static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
++ { 160000000, P_PLL0, 5, 1, 1 },
++ { 213200000, P_PLL11, 5, 1, 1 },
++ { }
++};
++
++static struct clk_dyn_rcg ce5_a_clk_src = {
++ .ns_reg[0] = 0x3d84,
++ .ns_reg[1] = 0x3d88,
++ .bank_reg = 0x3d80,
++ .s[0] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++ },
++ .s[1] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++ },
++ .p[0] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .p[1] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .mux_sel_bit = 0,
++ .freq_tbl = clk_tbl_ce5_a_clk,
++ .clkr = {
++ .enable_reg = 0x3d80,
++ .enable_mask = BIT(1),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_a_clk_src",
++ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
++ .num_parents = 6,
++ .ops = &clk_dyn_rcg_ops,
++ },
++ },
++};
++
++static struct clk_branch ce5_a_clk = {
++ .halt_reg = 0x3c20,
++ .halt_bit = 12,
++ .hwcg_reg = 0x3d8c,
++ .hwcg_bit = 6,
++ .clkr = {
++ .enable_reg = 0x3d8c,
++ .enable_mask = BIT(4),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_a_clk",
++ .parent_names = (const char *[]){
++ "ce5_a_clk_src",
++ },
++ .num_parents = 1,
++ .ops = &clk_branch_ops,
++ .flags = CLK_SET_RATE_PARENT,
++ },
++ },
++};
++
++static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
++ { 160000000, P_PLL0, 5, 1, 1 },
++ { 213200000, P_PLL11, 5, 1, 1 },
++ { }
++};
++
++static struct clk_dyn_rcg ce5_h_clk_src = {
++ .ns_reg[0] = 0x3c64,
++ .ns_reg[1] = 0x3c68,
++ .bank_reg = 0x3c60,
++ .s[0] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++ },
++ .s[1] = {
++ .src_sel_shift = 0,
++ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++ },
++ .p[0] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .p[1] = {
++ .pre_div_shift = 3,
++ .pre_div_width = 4,
++ },
++ .mux_sel_bit = 0,
++ .freq_tbl = clk_tbl_ce5_h_clk,
++ .clkr = {
++ .enable_reg = 0x3c60,
++ .enable_mask = BIT(1),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_h_clk_src",
++ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
++ .num_parents = 6,
++ .ops = &clk_dyn_rcg_ops,
++ },
++ },
++};
++
++static struct clk_branch ce5_h_clk = {
++ .halt_reg = 0x3c20,
++ .halt_bit = 11,
++ .hwcg_reg = 0x3c6c,
++ .hwcg_bit = 6,
++ .clkr = {
++ .enable_reg = 0x3c6c,
++ .enable_mask = BIT(4),
++ .hw.init = &(struct clk_init_data){
++ .name = "ce5_h_clk",
++ .parent_names = (const char *[]){
++ "ce5_h_clk_src",
++ },
++ .num_parents = 1,
++ .ops = &clk_branch_ops,
++ .flags = CLK_SET_RATE_PARENT,
++ },
++ },
++};
++
+ static struct clk_regmap *gcc_ipq806x_clks[] = {
+ [PLL0] = &pll0.clkr,
+ [PLL0_VOTE] = &pll0_vote,
+@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl
+ [PLL4_VOTE] = &pll4_vote,
+ [PLL8] = &pll8.clkr,
+ [PLL8_VOTE] = &pll8_vote,
++ [PLL11] = &pll11.clkr,
+ [PLL14] = &pll14.clkr,
+ [PLL14_VOTE] = &pll14_vote,
+ [PLL18] = &pll18.clkr,
+@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl
+ [PLL9] = &hfpll0.clkr,
+ [PLL10] = &hfpll1.clkr,
+ [PLL12] = &hfpll_l2.clkr,
++ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
++ [CE5_A_CLK] = &ce5_a_clk.clkr,
++ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
++ [CE5_H_CLK] = &ce5_h_clk.clkr,
++ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
++ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
+ };
+
+ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
+@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i
+ [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
+ [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
+ [GMAC_AHB_RESET] = { 0x3e24, 0 },
++ [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
++ [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
++ [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
++ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
++ [CRYPTO_AHB_RESET] = { 0x3e10, 0},
+ [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
+ [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
+ [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
+--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+@@ -240,7 +240,7 @@
+ #define PLL14 232
+ #define PLL14_VOTE 233
+ #define PLL18 234
+-#define CE5_SRC 235
++#define CE5_A_CLK 235
+ #define CE5_H_CLK 236
+ #define CE5_CORE_CLK 237
+ #define CE3_SLEEP_CLK 238
+@@ -283,5 +283,8 @@
+ #define EBI2_AON_CLK 281
+ #define NSSTCM_CLK_SRC 282
+ #define NSSTCM_CLK 283
++#define CE5_A_CLK_SRC 285
++#define CE5_H_CLK_SRC 286
++#define CE5_CORE_CLK_SRC 287
+
+ #endif
+--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+@@ -163,5 +163,10 @@
+ #define NSS_CAL_PRBS_RST_N_RESET 154
+ #define NSS_LCKDT_RST_N_RESET 155
+ #define NSS_SRDS_N_RESET 156
++#define CRYPTO_ENG1_RESET 157
++#define CRYPTO_ENG2_RESET 158
++#define CRYPTO_ENG3_RESET 159
++#define CRYPTO_ENG4_RESET 160
++#define CRYPTO_AHB_RESET 161
+
+ #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-04 17:11:56 +0000