diff options
Diffstat (limited to 'target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch b/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch new file mode 100644 index 0000000000..911c18e69d --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch @@ -0,0 +1,55 @@ +From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Mon, 15 Jun 2020 23:06:04 +0200 +Subject: PCI: qcom: Add support for tx term offset for rev 2.1.0 + +Add tx term offset support to pcie qcom driver need in some revision of +the ipq806x SoC. Ipq8064 needs tx term offset set to 7. + +Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> +Cc: stable@vger.kernel.org # v4.5+ +--- + drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -45,7 +45,13 @@ + #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 + + #define PCIE20_PARF_PHY_CTRL 0x40 ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) ++ + #define PCIE20_PARF_PHY_REFCLK 0x4C ++#define PHY_REFCLK_SSP_EN BIT(16) ++#define PHY_REFCLK_USE_PAD BIT(12) ++ + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 + #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C + #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +@@ -360,9 +366,18 @@ static int qcom_pcie_init_2_1_0(struct q + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + } + ++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { ++ /* set TX termination offset */ ++ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); ++ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; ++ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); ++ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); ++ } ++ + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); +- val |= BIT(16); ++ val &= ~PHY_REFCLK_USE_PAD; ++ val |= PHY_REFCLK_SSP_EN; + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + + /* wait for clock acquisition */ |