diff options
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch b/target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch deleted file mode 100644 index a44757a2e3..0000000000 --- a/target/linux/ipq807x/patches-5.15/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6f49bc0ee169c90b5c26a1e3d27a4728142f0ddb Mon Sep 17 00:00:00 2001 -From: Robert Marko <robimarko@gmail.com> -Date: Wed, 16 Nov 2022 22:48:34 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY - -IPQ8074 comes in 2 silicon versions: -* v1 with 2x Gen2 PCIe ports and QMP PHY-s -* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s - -v2 is the final and production version that is actually supported by the -kernel, however it looks like PCIe related nodes were added for the v1 SoC. - -Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support -by fixing the Gen3 QMP PHY node first. - -Change the compatible to the Gen3 QMP PHY, correct the register space start -and size, add the missing misc PCS register space. - -Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") -Signed-off-by: Robert Marko <robimarko@gmail.com> ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++------- - 1 file changed, 8 insertions(+), 7 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -232,9 +232,9 @@ - status = "disabled"; - }; - -- pcie_qmp0: phy@86000 { -- compatible = "qcom,ipq8074-qmp-pcie-phy"; -- reg = <0x00086000 0x1c4>; -+ pcie_qmp0: phy@84000 { -+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; -+ reg = <0x00084000 0x1bc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; -@@ -248,10 +248,11 @@ - "common"; - status = "disabled"; - -- pcie_phy0: phy@86200 { -- reg = <0x86200 0x16c>, -- <0x86400 0x200>, -- <0x86800 0x4f4>; -+ pcie_phy0: phy@84200 { -+ reg = <0x84200 0x16c>, -+ <0x84400 0x200>, -+ <0x84800 0x1f0>, -+ <0x84c00 0xf4>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; |