diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch b/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch new file mode 100644 index 0000000000..c267297258 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch @@ -0,0 +1,73 @@ +From 1f58043afef0dca3d12dc23ac3a35d7074412939 Mon Sep 17 00:00:00 2001 +From: Minghuan Lian <Minghuan.Lian@nxp.com> +Date: Tue, 2 Feb 2016 16:30:07 +0800 +Subject: [PATCH 01/13] ARM: dts: ls1021a: add PCIe dts node + +Cherry-pick upstream patch. + +LS1021a contains two PCIe controllers. The patch adds their node to +dts file. + +Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> +Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> +--- + arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 44 insertions(+) + +diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi +index 9430a99..38272d0 100644 +--- a/arch/arm/boot/dts/ls1021a.dtsi ++++ b/arch/arm/boot/dts/ls1021a.dtsi +@@ -539,5 +539,49 @@ + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + }; ++ ++ pcie@3400000 { ++ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ ++ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ ++ fsl,pcie-scfg = <&scfg 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ num-lanes = <4>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ pcie@3500000 { ++ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ ++ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; ++ fsl,pcie-scfg = <&scfg 1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ num-lanes = <4>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, ++ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; ++ }; + }; + }; +-- +2.1.0.27.g96db324 + |