diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/701-net-0385-net-mscc-ocelot-export-ANA-DEV-and-QSYS-registers-to.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/701-net-0385-net-mscc-ocelot-export-ANA-DEV-and-QSYS-registers-to.patch | 2457 |
1 files changed, 2457 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/701-net-0385-net-mscc-ocelot-export-ANA-DEV-and-QSYS-registers-to.patch b/target/linux/layerscape/patches-5.4/701-net-0385-net-mscc-ocelot-export-ANA-DEV-and-QSYS-registers-to.patch new file mode 100644 index 0000000000..b300ba9d76 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/701-net-0385-net-mscc-ocelot-export-ANA-DEV-and-QSYS-registers-to.patch @@ -0,0 +1,2457 @@ +From 518d779810c0e4185f2d8a71fc112232df5be62e Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean <vladimir.oltean@nxp.com> +Date: Mon, 16 Dec 2019 15:09:49 +0200 +Subject: [PATCH] net: mscc: ocelot: export ANA, DEV and QSYS registers to + include/soc/mscc + +Since the Felix DSA driver is implementing its own PHYLINK instance due +to SoC differences, it needs access to the few registers that are +common, mainly for flow control. + +Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> + +Conflicts: + drivers/net/ethernet/mscc/ocelot_tsn.c + +which has been added in downstream patch b5c05e3404a5 ("net: mscc: +ocelot: tsn configuration support") and also needs to be adapted to the +new location of the header files. +--- + drivers/net/ethernet/mscc/ocelot.h | 6 +- + drivers/net/ethernet/mscc/ocelot_ana.h | 642 -------------------------------- + drivers/net/ethernet/mscc/ocelot_dev.h | 275 -------------- + drivers/net/ethernet/mscc/ocelot_qsys.h | 270 -------------- + drivers/net/ethernet/mscc/ocelot_tsn.c | 4 +- + include/soc/mscc/ocelot_ana.h | 642 ++++++++++++++++++++++++++++++++ + include/soc/mscc/ocelot_dev.h | 275 ++++++++++++++ + include/soc/mscc/ocelot_qsys.h | 270 ++++++++++++++ + 8 files changed, 1192 insertions(+), 1192 deletions(-) + delete mode 100644 drivers/net/ethernet/mscc/ocelot_ana.h + delete mode 100644 drivers/net/ethernet/mscc/ocelot_dev.h + delete mode 100644 drivers/net/ethernet/mscc/ocelot_qsys.h + create mode 100644 include/soc/mscc/ocelot_ana.h + create mode 100644 include/soc/mscc/ocelot_dev.h + create mode 100644 include/soc/mscc/ocelot_qsys.h + +--- a/drivers/net/ethernet/mscc/ocelot.h ++++ b/drivers/net/ethernet/mscc/ocelot.h +@@ -18,11 +18,11 @@ + #include <linux/ptp_clock_kernel.h> + #include <linux/regmap.h> + ++#include <soc/mscc/ocelot_qsys.h> + #include <soc/mscc/ocelot_sys.h> ++#include <soc/mscc/ocelot_dev.h> ++#include <soc/mscc/ocelot_ana.h> + #include <soc/mscc/ocelot.h> +-#include "ocelot_ana.h" +-#include "ocelot_dev.h" +-#include "ocelot_qsys.h" + #include "ocelot_rew.h" + #include "ocelot_qs.h" + #include "ocelot_tc.h" +--- a/drivers/net/ethernet/mscc/ocelot_ana.h ++++ /dev/null +@@ -1,642 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Microsemi Ocelot Switch driver +- * +- * Copyright (c) 2017 Microsemi Corporation +- */ +- +-#ifndef _MSCC_OCELOT_ANA_H_ +-#define _MSCC_OCELOT_ANA_H_ +- +-#define ANA_ANAGEFIL_B_DOM_EN BIT(22) +-#define ANA_ANAGEFIL_B_DOM_VAL BIT(21) +-#define ANA_ANAGEFIL_AGE_LOCKED BIT(20) +-#define ANA_ANAGEFIL_PID_EN BIT(19) +-#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) +-#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14) +-#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) +-#define ANA_ANAGEFIL_VID_EN BIT(13) +-#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) +-#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0) +- +-#define ANA_STORMLIMIT_CFG_RSZ 0x4 +- +-#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) +-#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3) +-#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) +-#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2) +-#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) +-#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0) +- +-#define ANA_AUTOAGE_AGE_FAST BIT(21) +-#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1)) +-#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1) +-#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1) +-#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0) +- +-#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1) +-#define ANA_MACTOPTIONS_SHADOW BIT(0) +- +-#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12)) +-#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12) +-#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12) +-#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11) +-#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10) +-#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9) +-#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8) +-#define ANA_AGENCTRL_MIRROR_CPU BIT(7) +-#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6) +-#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5) +-#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4) +-#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3) +-#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2) +-#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1) +-#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0) +- +-#define ANA_FLOODING_RSZ 0x4 +- +-#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12)) +-#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12) +-#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12) +-#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6)) +-#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6) +-#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6) +-#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) +-#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0) +- +-#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18)) +-#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18) +-#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18) +-#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12)) +-#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12) +-#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12) +-#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6)) +-#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6) +-#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6) +-#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) +-#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0) +- +-#define ANA_SFLOW_CFG_RSZ 0x4 +- +-#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2)) +-#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2) +-#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2) +-#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1) +-#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0) +- +-#define ANA_PORT_MODE_RSZ 0x4 +- +-#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3) +-#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1)) +-#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1) +-#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1) +-#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0) +- +-#define ANA_CUT_THRU_CFG_RSZ 0x4 +- +-#define ANA_PGID_PGID_RSZ 0x4 +- +-#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) +-#define ANA_PGID_PGID_PGID_M GENMASK(11, 0) +-#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27)) +-#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27) +-#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27) +- +-#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16)) +-#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16) +-#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16) +-#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) +-#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0) +- +-#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16) +-#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9)) +-#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9) +-#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9) +-#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8) +-#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) +-#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0) +- +-#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15) +-#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14) +-#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13) +-#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12) +-#define ANA_TABLES_MACACCESS_VALID BIT(11) +-#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9)) +-#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9) +-#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9) +-#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3)) +-#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3) +-#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3) +-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) +-#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0) +-#define MACACCESS_CMD_IDLE 0 +-#define MACACCESS_CMD_LEARN 1 +-#define MACACCESS_CMD_FORGET 2 +-#define MACACCESS_CMD_AGE 3 +-#define MACACCESS_CMD_GET_NEXT 4 +-#define MACACCESS_CMD_INIT 5 +-#define MACACCESS_CMD_READ 6 +-#define MACACCESS_CMD_WRITE 7 +- +-#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2)) +-#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2) +-#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2) +-#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) +-#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0) +-#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0 +-#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2 +-#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3 +- +-#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17) +-#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16) +-#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15) +-#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14) +-#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13) +-#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12) +-#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0)) +-#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0) +- +-#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2)) +-#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2) +-#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2) +-#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) +-#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0) +- +-#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21)) +-#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21) +-#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21) +-#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15)) +-#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15) +-#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15) +-#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14) +-#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10) +-#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0)) +-#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0) +- +-#define ANA_TABLES_ENTRYLIM_RSZ 0x4 +- +-#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14)) +-#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14) +-#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14) +-#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0)) +-#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0) +- +-#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4)) +-#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4) +-#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4) +-#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3) +-#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2) +-#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0)) +-#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0) +- +-#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30)) +-#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30) +-#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30) +-#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16)) +-#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16) +-#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16) +-#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14) +-#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8)) +-#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8) +-#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8) +-#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7) +-#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6) +-#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5) +-#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0)) +-#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0) +- +-#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16)) +-#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16) +-#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16) +-#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0)) +-#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0) +- +-#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1)) +-#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1) +-#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1) +-#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0) +- +-#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22) +-#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19)) +-#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19) +-#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19) +-#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18) +-#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2)) +-#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2) +-#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2) +-#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0)) +-#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0) +- +-#define SFIDACCESS_CMD_IDLE 0 +-#define SFIDACCESS_CMD_READ 1 +-#define SFIDACCESS_CMD_WRITE 2 +-#define SFIDACCESS_CMD_INIT 3 +- +-#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26) +-#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18)) +-#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18) +-#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18) +-#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17) +-#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8)) +-#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8) +-#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8) +-#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0)) +-#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0) +- +-#define ANA_MSTI_STATE_RSZ 0x4 +- +-#define ANA_OAM_UPM_LM_CNT_RSZ 0x4 +- +-#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0)) +-#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0) +-#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) +- +-#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) +-#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) +-#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16)) +-#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16) +-#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16) +-#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) +-#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21)) +-#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21) +-#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21) +-#define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24) +-#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24)) +-#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21)) +-#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21) +-#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21) +-#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) +- +-#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4 +- +-#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0)) +-#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0) +-#define ANA_SG_GCL_GS_CONFIG_IPV_VALID BIT(3) +-#define ANA_SG_GCL_GS_CONFIG_IPV(x) ((x) & GENMASK(2, 0)) +-#define ANA_SG_GCL_GS_CONFIG_IPV_M GENMASK(2, 0) +-#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) +- +-#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4 +- +-#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) +-#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) +-#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16) +-#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20)) +-#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20) +-#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20) +-#define ANA_SG_STATUS_REG_3_IPV_VALID BIT(23) +-#define ANA_SG_STATUS_REG_3_IPV(x) (((x) << 20) & GENMASK(22, 20)) +-#define ANA_SG_STATUS_REG_3_IPV_M GENMASK(22, 20) +-#define ANA_SG_STATUS_REG_3_IPV_X(x) (((x) & GENMASK(22, 20)) >> 20) +-#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) +- +-#define ANA_PORT_VLAN_CFG_GSZ 0x100 +- +-#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21) +-#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20) +-#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18)) +-#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18) +-#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18) +-#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17) +-#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16) +-#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15) +-#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12)) +-#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12) +-#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) +-#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0)) +-#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0) +- +-#define ANA_PORT_DROP_CFG_GSZ 0x100 +- +-#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) +-#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5) +-#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4) +-#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) +-#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) +-#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1) +-#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) +- +-#define ANA_PORT_QOS_CFG_GSZ 0x100 +- +-#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8) +-#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5)) +-#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5) +-#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5) +-#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4) +-#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3) +-#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2) +-#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0)) +-#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0) +- +-#define ANA_PORT_VCAP_CFG_GSZ 0x100 +- +-#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14) +-#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11)) +-#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11) +-#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11) +-#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8)) +-#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8) +-#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8) +-#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0)) +-#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0) +- +-#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100 +-#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4 +- +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4)) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2)) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0)) +-#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0) +- +-#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100 +- +-#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17)) +-#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17) +-#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17) +-#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15)) +-#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15) +-#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15) +-#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14) +-#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12)) +-#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12) +-#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12) +-#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10)) +-#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10) +-#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8)) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6)) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2)) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2) +-#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2) +-#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0)) +-#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0) +- +-#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100 +-#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4 +- +-#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3) +-#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0)) +-#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0) +- +-#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100 +- +-#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7) +-#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6) +-#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5) +-#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4) +-#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3) +-#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2) +-#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1) +-#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0) +- +-#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100 +- +-#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) +-#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16) +-#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0)) +-#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0) +- +-#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100 +- +-#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) +-#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16) +-#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0)) +-#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0) +- +-#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100 +- +-#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) +-#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16) +-#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0)) +-#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0) +- +-#define ANA_PORT_PORT_CFG_GSZ 0x100 +- +-#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15) +-#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14) +-#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13) +-#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12) +-#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11) +-#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10) +-#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9) +-#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8) +-#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7) +-#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) +-#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2)) +-#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2) +-#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2) +-#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1) +-#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0) +- +-#define ANA_PORT_POL_CFG_GSZ 0x100 +- +-#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19) +-#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18) +-#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17) +-#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9)) +-#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9) +-#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9) +-#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0)) +-#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0) +- +-#define ANA_PORT_PTP_CFG_GSZ 0x100 +- +-#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0) +- +-#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100 +- +-#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100 +- +-#define ANA_PORT_SFID_CFG_GSZ 0x100 +-#define ANA_PORT_SFID_CFG_RSZ 0x4 +- +-#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8) +-#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0)) +-#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0) +- +-#define ANA_PFC_PFC_CFG_GSZ 0x40 +- +-#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2)) +-#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2) +-#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2) +-#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0)) +-#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0) +- +-#define ANA_PFC_PFC_TIMER_GSZ 0x40 +-#define ANA_PFC_PFC_TIMER_RSZ 0x4 +- +-#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8 +- +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6)) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1)) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1) +-#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0) +- +-#define ANA_IPT_IPT_GSZ 0x8 +- +-#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15)) +-#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15) +-#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15) +-#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7)) +-#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7) +-#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7) +-#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0)) +-#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0) +- +-#define ANA_PPT_PPT_RSZ 0x4 +- +-#define ANA_FID_MAP_FID_MAP_RSZ 0x4 +- +-#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6)) +-#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6) +-#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6) +-#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0)) +-#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0) +- +-#define ANA_AGGR_CFG_AC_RND_ENA BIT(7) +-#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6) +-#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5) +-#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4) +-#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3) +-#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2) +-#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1) +-#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0) +- +-#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27)) +-#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27) +-#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27) +-#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24)) +-#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24) +-#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24) +-#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21)) +-#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21) +-#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21) +-#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18)) +-#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18) +-#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18) +-#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15)) +-#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15) +-#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15) +-#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12)) +-#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12) +-#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12) +-#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9)) +-#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9) +-#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9) +-#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6)) +-#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6) +-#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6) +-#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3)) +-#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3) +-#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3) +-#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0)) +-#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0) +- +-#define ANA_CPUQ_8021_CFG_RSZ 0x4 +- +-#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6)) +-#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6) +-#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6) +-#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3)) +-#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3) +-#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3) +-#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0)) +-#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0) +- +-#define ANA_DSCP_CFG_RSZ 0x4 +- +-#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) +-#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8)) +-#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8) +-#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8) +-#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2)) +-#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2) +-#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2) +-#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) +-#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) +- +-#define ANA_DSCP_REWR_CFG_RSZ 0x4 +- +-#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4 +- +-#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4 +- +-#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16)) +-#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16) +-#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0)) +-#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0) +- +-#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12) +-#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0)) +-#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0) +- +-#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3) +-#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2) +-#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1) +-#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0) +- +-#define ANA_FID_CFG_VID_MC_ENA BIT(0) +- +-#define ANA_POL_PIR_CFG_GSZ 0x20 +- +-#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) +-#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6) +-#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) +-#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0)) +-#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0) +- +-#define ANA_POL_CIR_CFG_GSZ 0x20 +- +-#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) +-#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6) +-#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) +-#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) +-#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0) +- +-#define ANA_POL_MODE_CFG_GSZ 0x20 +- +-#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5)) +-#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5) +-#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5) +-#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3)) +-#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3) +-#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3) +-#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2) +-#define ANA_POL_MODE_CFG_CIR_ENA BIT(1) +-#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0) +- +-#define ANA_POL_PIR_STATE_GSZ 0x20 +- +-#define ANA_POL_CIR_STATE_GSZ 0x20 +- +-#define ANA_POL_STATE_GSZ 0x20 +- +-#define ANA_POL_FLOWC_RSZ 0x4 +- +-#define ANA_POL_FLOWC_POL_FLOWC BIT(0) +- +-#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4)) +-#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4) +-#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4) +-#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0)) +-#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0) +- +-#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1) +-#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0) +- +-#endif +--- a/drivers/net/ethernet/mscc/ocelot_dev.h ++++ /dev/null +@@ -1,275 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Microsemi Ocelot Switch driver +- * +- * Copyright (c) 2017 Microsemi Corporation +- */ +- +-#ifndef _MSCC_OCELOT_DEV_H_ +-#define _MSCC_OCELOT_DEV_H_ +- +-#define DEV_CLOCK_CFG 0x0 +- +-#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) +-#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) +-#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) +-#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) +-#define DEV_CLOCK_CFG_PORT_RST BIT(3) +-#define DEV_CLOCK_CFG_PHY_RST BIT(2) +-#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) +-#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0) +- +-#define DEV_PORT_MISC 0x4 +- +-#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4) +-#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3) +-#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2) +-#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1) +-#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0) +- +-#define DEV_EVENTS 0x8 +- +-#define DEV_EEE_CFG 0xc +- +-#define DEV_EEE_CFG_EEE_ENA BIT(22) +-#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) +-#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15) +-#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) +-#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) +-#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8) +-#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) +-#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) +-#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1) +-#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) +-#define DEV_EEE_CFG_PORT_LPI BIT(0) +- +-#define DEV_RX_PATH_DELAY 0x10 +- +-#define DEV_TX_PATH_DELAY 0x14 +- +-#define DEV_PTP_PREDICT_CFG 0x18 +- +-#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) +-#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4) +-#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4) +-#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0)) +-#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0) +- +-#define DEV_MAC_ENA_CFG 0x1c +- +-#define DEV_MAC_ENA_CFG_RX_ENA BIT(4) +-#define DEV_MAC_ENA_CFG_TX_ENA BIT(0) +- +-#define DEV_MAC_MODE_CFG 0x20 +- +-#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) +-#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) +-#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0) +- +-#define DEV_MAC_MAXLEN_CFG 0x24 +- +-#define DEV_MAC_TAGS_CFG 0x28 +- +-#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16)) +-#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16) +-#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2) +-#define DEV_MAC_TAGS_CFG_PB_ENA BIT(1) +-#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) +- +-#define DEV_MAC_ADV_CHK_CFG 0x2c +- +-#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) +- +-#define DEV_MAC_IFG_CFG 0x30 +- +-#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) +-#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16) +-#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8)) +-#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8) +-#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8) +-#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4)) +-#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4) +-#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4) +-#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0)) +-#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0) +- +-#define DEV_MAC_HDX_CFG 0x34 +- +-#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) +-#define DEV_MAC_HDX_CFG_OB_ENA BIT(25) +-#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24) +-#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16)) +-#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16) +-#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16) +-#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) +-#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) +-#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0)) +-#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0) +- +-#define DEV_MAC_DBG_CFG 0x38 +- +-#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4) +-#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0) +- +-#define DEV_MAC_FC_MAC_LOW_CFG 0x3c +- +-#define DEV_MAC_FC_MAC_HIGH_CFG 0x40 +- +-#define DEV_MAC_STICKY 0x44 +- +-#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9) +-#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8) +-#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7) +-#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6) +-#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5) +-#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4) +-#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3) +-#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2) +-#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1) +-#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0) +- +-#define PCS1G_CFG 0x48 +- +-#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4) +-#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) +-#define PCS1G_CFG_PCS_ENA BIT(0) +- +-#define PCS1G_MODE_CFG 0x4c +- +-#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) +-#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) +- +-#define PCS1G_SD_CFG 0x50 +- +-#define PCS1G_SD_CFG_SD_SEL BIT(8) +-#define PCS1G_SD_CFG_SD_POL BIT(4) +-#define PCS1G_SD_CFG_SD_ENA BIT(0) +- +-#define PCS1G_ANEG_CFG 0x54 +- +-#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) +-#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16) +-#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) +-#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) +-#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0) +- +-#define PCS1G_ANEG_NP_CFG 0x58 +- +-#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16)) +-#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16) +-#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0) +- +-#define PCS1G_LB_CFG 0x5c +- +-#define PCS1G_LB_CFG_RA_ENA BIT(4) +-#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) +-#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) +- +-#define PCS1G_DBG_CFG 0x60 +- +-#define PCS1G_DBG_CFG_UDLT BIT(0) +- +-#define PCS1G_CDET_CFG 0x64 +- +-#define PCS1G_CDET_CFG_CDET_ENA BIT(0) +- +-#define PCS1G_ANEG_STATUS 0x68 +- +-#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) +-#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16) +-#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) +-#define PCS1G_ANEG_STATUS_PR BIT(4) +-#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) +-#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) +- +-#define PCS1G_ANEG_NP_STATUS 0x6c +- +-#define PCS1G_LINK_STATUS 0x70 +- +-#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12)) +-#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12) +-#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12) +-#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) +-#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4) +-#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) +- +-#define PCS1G_LINK_DOWN_CNT 0x74 +- +-#define PCS1G_STICKY 0x78 +- +-#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) +-#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) +- +-#define PCS1G_DEBUG_STATUS 0x7c +- +-#define PCS1G_LPI_CFG 0x80 +- +-#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20) +-#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17) +-#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16) +-#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4)) +-#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4) +-#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4) +-#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0) +- +-#define PCS1G_LPI_WAKE_ERROR_CNT 0x84 +- +-#define PCS1G_LPI_STATUS 0x88 +- +-#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16) +-#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12) +-#define PCS1G_LPI_STATUS_RX_QUIET BIT(9) +-#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8) +-#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4) +-#define PCS1G_LPI_STATUS_TX_QUIET BIT(1) +-#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0) +- +-#define PCS1G_TSTPAT_MODE_CFG 0x8c +- +-#define PCS1G_TSTPAT_STATUS 0x90 +- +-#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8)) +-#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8) +-#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8) +-#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4) +-#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0) +- +-#define DEV_PCS_FX100_CFG 0x94 +- +-#define DEV_PCS_FX100_CFG_SD_SEL BIT(26) +-#define DEV_PCS_FX100_CFG_SD_POL BIT(25) +-#define DEV_PCS_FX100_CFG_SD_ENA BIT(24) +-#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) +-#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) +-#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12)) +-#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12) +-#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12) +-#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9)) +-#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9) +-#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9) +-#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) +-#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4)) +-#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4) +-#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4) +-#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) +-#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2) +-#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1) +-#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0) +- +-#define DEV_PCS_FX100_STATUS 0x98 +- +-#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8)) +-#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8) +-#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8) +-#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) +-#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) +-#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) +-#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) +-#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2) +-#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) +-#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0) +- +-#endif +--- a/drivers/net/ethernet/mscc/ocelot_qsys.h ++++ /dev/null +@@ -1,270 +0,0 @@ +-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +-/* +- * Microsemi Ocelot Switch driver +- * +- * Copyright (c) 2017 Microsemi Corporation +- */ +- +-#ifndef _MSCC_OCELOT_QSYS_H_ +-#define _MSCC_OCELOT_QSYS_H_ +- +-#define QSYS_PORT_MODE_RSZ 0x4 +- +-#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) +-#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0) +- +-#define QSYS_SWITCH_PORT_MODE_RSZ 0x4 +- +-#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14) +-#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11)) +-#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11) +-#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11) +-#define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10) +-#define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9) +-#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1)) +-#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1) +-#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1) +-#define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0) +- +-#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5) +-#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4) +-#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3) +-#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2) +-#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1) +-#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0) +- +-#define QSYS_EEE_CFG_RSZ 0x4 +- +-#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) +-#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8) +-#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) +-#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) +-#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0) +- +-#define QSYS_SW_STATUS_RSZ 0x4 +- +-#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) +-#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8) +-#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) +-#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) +-#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0) +- +-#define QSYS_QMAP_GSZ 0x4 +- +-#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) +-#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5) +-#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) +-#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) +-#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2) +-#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2) +-#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) +-#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0) +- +-#define QSYS_ISDX_SGRP_GSZ 0x4 +- +-#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4 +- +-#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9)) +-#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9) +-#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9) +-#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8) +-#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7) +-#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) +-#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0) +- +-#define QSYS_RED_PROFILE_RSZ 0x4 +- +-#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8)) +-#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8) +-#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8) +-#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) +-#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0) +- +-#define QSYS_RES_CFG_GSZ 0x8 +- +-#define QSYS_RES_STAT_GSZ 0x8 +- +-#define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12)) +-#define QSYS_RES_STAT_INUSE_M GENMASK(23, 12) +-#define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12) +-#define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0)) +-#define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0) +- +-#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2)) +-#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2) +-#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2) +-#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) +-#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0) +- +-#define QSYS_QMAXSDU_CFG_0_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_1_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_2_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_3_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_4_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_5_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_6_RSZ 0x4 +- +-#define QSYS_QMAXSDU_CFG_7_RSZ 0x4 +- +-#define QSYS_PREEMPTION_CFG_RSZ 0x4 +- +-#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) +-#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0) +-#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8)) +-#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8) +-#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8) +-#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12)) +-#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12) +-#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12) +-#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16)) +-#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16) +-#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16) +- +-#define QSYS_CIR_CFG_GSZ 0x80 +- +-#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) +-#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6) +-#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) +-#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) +-#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0) +- +-#define QSYS_EIR_CFG_GSZ 0x80 +- +-#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7)) +-#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7) +-#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7) +-#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1)) +-#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1) +-#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1) +-#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0) +- +-#define QSYS_SE_CFG_GSZ 0x80 +- +-#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6)) +-#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6) +-#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6) +-#define QSYS_SE_CFG_SE_RR_ENA BIT(5) +-#define QSYS_SE_CFG_SE_AVB_ENA BIT(4) +-#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2)) +-#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2) +-#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) +-#define QSYS_SE_CFG_SE_EXC_ENA BIT(1) +-#define QSYS_SE_CFG_SE_EXC_FWD BIT(0) +- +-#define QSYS_SE_DWRR_CFG_GSZ 0x80 +-#define QSYS_SE_DWRR_CFG_RSZ 0x4 +- +-#define QSYS_SE_CONNECT_GSZ 0x80 +- +-#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17)) +-#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17) +-#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17) +-#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9)) +-#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9) +-#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9) +-#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5)) +-#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5) +-#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5) +-#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1)) +-#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1) +-#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1) +-#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0) +- +-#define QSYS_SE_DLB_SENSE_GSZ 0x80 +- +-#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11)) +-#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11) +-#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11) +-#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7)) +-#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7) +-#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7) +-#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3)) +-#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3) +-#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3) +-#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2) +-#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1) +-#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) +- +-#define QSYS_CIR_STATE_GSZ 0x80 +- +-#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4)) +-#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4) +-#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4) +-#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) +-#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0) +- +-#define QSYS_EIR_STATE_GSZ 0x80 +- +-#define QSYS_SE_STATE_GSZ 0x80 +- +-#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1)) +-#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1) +-#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1) +-#define QSYS_SE_STATE_SE_WAS_YEL BIT(0) +- +-#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8) +-#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3)) +-#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3) +-#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3) +-#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2) +-#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1) +-#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0) +- +-#define QSYS_TAG_CONFIG_RSZ 0x4 +- +-#define QSYS_TAG_CONFIG_ENABLE BIT(0) +-#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4)) +-#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4) +-#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4) +-#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) +-#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8) +-#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) +-#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16)) +-#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16) +-#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16) +- +-#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0)) +-#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0) +-#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8) +-#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16) +- +-#define QSYS_PORT_MAX_SDU_RSZ 0x4 +- +-#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) +-#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) +-#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) +-#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16) +-#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) +- +-#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) +-#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) +-#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) +-#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8) +-#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) +- +-#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) +-#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) +-#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) +-#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16) +-#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) +- +-#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) +-#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) +-#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16)) +-#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16) +-#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16) +-#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24) +- +-#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) +-#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) +-#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) +-#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8) +-#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) +- +-#endif +--- a/drivers/net/ethernet/mscc/ocelot_tsn.c ++++ b/drivers/net/ethernet/mscc/ocelot_tsn.c +@@ -11,8 +11,8 @@ + #include <linux/iopoll.h> + #include "ocelot.h" + #include <soc/mscc/ocelot_sys.h> +-#include "ocelot_ana.h" +-#include "ocelot_qsys.h" ++#include <soc/mscc/ocelot_ana.h> ++#include <soc/mscc/ocelot_qsys.h> + #include "ocelot_rew.h" + #include "ocelot_dev_gmii.h" + #include "ocelot_tsn.h" +--- /dev/null ++++ b/include/soc/mscc/ocelot_ana.h +@@ -0,0 +1,642 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++/* ++ * Microsemi Ocelot Switch driver ++ * ++ * Copyright (c) 2017 Microsemi Corporation ++ */ ++ ++#ifndef _MSCC_OCELOT_ANA_H_ ++#define _MSCC_OCELOT_ANA_H_ ++ ++#define ANA_ANAGEFIL_B_DOM_EN BIT(22) ++#define ANA_ANAGEFIL_B_DOM_VAL BIT(21) ++#define ANA_ANAGEFIL_AGE_LOCKED BIT(20) ++#define ANA_ANAGEFIL_PID_EN BIT(19) ++#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) ++#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14) ++#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) ++#define ANA_ANAGEFIL_VID_EN BIT(13) ++#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) ++#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0) ++ ++#define ANA_STORMLIMIT_CFG_RSZ 0x4 ++ ++#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) ++#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3) ++#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) ++#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2) ++#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) ++#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0) ++ ++#define ANA_AUTOAGE_AGE_FAST BIT(21) ++#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1)) ++#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1) ++#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1) ++#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0) ++ ++#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1) ++#define ANA_MACTOPTIONS_SHADOW BIT(0) ++ ++#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12)) ++#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12) ++#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12) ++#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11) ++#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10) ++#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9) ++#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8) ++#define ANA_AGENCTRL_MIRROR_CPU BIT(7) ++#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6) ++#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5) ++#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4) ++#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3) ++#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2) ++#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1) ++#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0) ++ ++#define ANA_FLOODING_RSZ 0x4 ++ ++#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12)) ++#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12) ++#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12) ++#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6)) ++#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6) ++#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6) ++#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) ++#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0) ++ ++#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18)) ++#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18) ++#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18) ++#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12)) ++#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12) ++#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12) ++#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6)) ++#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6) ++#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6) ++#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) ++#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0) ++ ++#define ANA_SFLOW_CFG_RSZ 0x4 ++ ++#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2)) ++#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2) ++#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2) ++#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1) ++#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0) ++ ++#define ANA_PORT_MODE_RSZ 0x4 ++ ++#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3) ++#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1)) ++#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1) ++#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1) ++#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0) ++ ++#define ANA_CUT_THRU_CFG_RSZ 0x4 ++ ++#define ANA_PGID_PGID_RSZ 0x4 ++ ++#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) ++#define ANA_PGID_PGID_PGID_M GENMASK(11, 0) ++#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27)) ++#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27) ++#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27) ++ ++#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16)) ++#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16) ++#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16) ++#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) ++#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0) ++ ++#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16) ++#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9)) ++#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9) ++#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9) ++#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8) ++#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) ++#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0) ++ ++#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15) ++#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14) ++#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13) ++#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12) ++#define ANA_TABLES_MACACCESS_VALID BIT(11) ++#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9)) ++#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9) ++#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9) ++#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3)) ++#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3) ++#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3) ++#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) ++#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0) ++#define MACACCESS_CMD_IDLE 0 ++#define MACACCESS_CMD_LEARN 1 ++#define MACACCESS_CMD_FORGET 2 ++#define MACACCESS_CMD_AGE 3 ++#define MACACCESS_CMD_GET_NEXT 4 ++#define MACACCESS_CMD_INIT 5 ++#define MACACCESS_CMD_READ 6 ++#define MACACCESS_CMD_WRITE 7 ++ ++#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2)) ++#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2) ++#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2) ++#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) ++#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0) ++#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0 ++#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2 ++#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3 ++ ++#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17) ++#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16) ++#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15) ++#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14) ++#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13) ++#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12) ++#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0)) ++#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0) ++ ++#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2)) ++#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2) ++#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2) ++#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) ++#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0) ++ ++#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21)) ++#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21) ++#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21) ++#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15)) ++#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15) ++#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15) ++#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14) ++#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10) ++#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0)) ++#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0) ++ ++#define ANA_TABLES_ENTRYLIM_RSZ 0x4 ++ ++#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14)) ++#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14) ++#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14) ++#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0)) ++#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0) ++ ++#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4)) ++#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4) ++#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4) ++#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3) ++#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2) ++#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0)) ++#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0) ++ ++#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30)) ++#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30) ++#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30) ++#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16)) ++#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16) ++#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16) ++#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14) ++#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8)) ++#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8) ++#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8) ++#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7) ++#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6) ++#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5) ++#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0)) ++#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0) ++ ++#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16)) ++#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16) ++#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16) ++#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0)) ++#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0) ++ ++#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1)) ++#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1) ++#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1) ++#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0) ++ ++#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22) ++#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19)) ++#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19) ++#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19) ++#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18) ++#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2)) ++#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2) ++#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2) ++#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0)) ++#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0) ++ ++#define SFIDACCESS_CMD_IDLE 0 ++#define SFIDACCESS_CMD_READ 1 ++#define SFIDACCESS_CMD_WRITE 2 ++#define SFIDACCESS_CMD_INIT 3 ++ ++#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26) ++#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18)) ++#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18) ++#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18) ++#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17) ++#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8)) ++#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8) ++#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8) ++#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0)) ++#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0) ++ ++#define ANA_MSTI_STATE_RSZ 0x4 ++ ++#define ANA_OAM_UPM_LM_CNT_RSZ 0x4 ++ ++#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0)) ++#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0) ++#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) ++ ++#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) ++#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) ++#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16)) ++#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16) ++#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16) ++#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) ++#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21)) ++#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21) ++#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21) ++#define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24) ++#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24)) ++#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21)) ++#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21) ++#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21) ++#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) ++ ++#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4 ++ ++#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0)) ++#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0) ++#define ANA_SG_GCL_GS_CONFIG_IPV_VALID BIT(3) ++#define ANA_SG_GCL_GS_CONFIG_IPV(x) ((x) & GENMASK(2, 0)) ++#define ANA_SG_GCL_GS_CONFIG_IPV_M GENMASK(2, 0) ++#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) ++ ++#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4 ++ ++#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) ++#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) ++#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16) ++#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20)) ++#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20) ++#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20) ++#define ANA_SG_STATUS_REG_3_IPV_VALID BIT(23) ++#define ANA_SG_STATUS_REG_3_IPV(x) (((x) << 20) & GENMASK(22, 20)) ++#define ANA_SG_STATUS_REG_3_IPV_M GENMASK(22, 20) ++#define ANA_SG_STATUS_REG_3_IPV_X(x) (((x) & GENMASK(22, 20)) >> 20) ++#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) ++ ++#define ANA_PORT_VLAN_CFG_GSZ 0x100 ++ ++#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21) ++#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20) ++#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18)) ++#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18) ++#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18) ++#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17) ++#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16) ++#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15) ++#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12)) ++#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12) ++#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) ++#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0)) ++#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0) ++ ++#define ANA_PORT_DROP_CFG_GSZ 0x100 ++ ++#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) ++#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5) ++#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4) ++#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) ++#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) ++#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1) ++#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) ++ ++#define ANA_PORT_QOS_CFG_GSZ 0x100 ++ ++#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8) ++#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5)) ++#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5) ++#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5) ++#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4) ++#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3) ++#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2) ++#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0)) ++#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0) ++ ++#define ANA_PORT_VCAP_CFG_GSZ 0x100 ++ ++#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14) ++#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11)) ++#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11) ++#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11) ++#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8)) ++#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8) ++#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8) ++#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0)) ++#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0) ++ ++#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100 ++#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4 ++ ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4)) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2)) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0)) ++#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0) ++ ++#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100 ++ ++#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17)) ++#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17) ++#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17) ++#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15)) ++#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15) ++#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15) ++#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14) ++#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12)) ++#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12) ++#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12) ++#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10)) ++#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10) ++#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8)) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6)) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2)) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2) ++#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2) ++#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0)) ++#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0) ++ ++#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100 ++#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4 ++ ++#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3) ++#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0)) ++#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0) ++ ++#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100 ++ ++#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7) ++#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6) ++#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5) ++#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4) ++#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3) ++#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2) ++#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1) ++#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0) ++ ++#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100 ++ ++#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) ++#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16) ++#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0)) ++#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0) ++ ++#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100 ++ ++#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) ++#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16) ++#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0)) ++#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0) ++ ++#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100 ++ ++#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16)) ++#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16) ++#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0)) ++#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0) ++ ++#define ANA_PORT_PORT_CFG_GSZ 0x100 ++ ++#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15) ++#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14) ++#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13) ++#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12) ++#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11) ++#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10) ++#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9) ++#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8) ++#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7) ++#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) ++#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2)) ++#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2) ++#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2) ++#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1) ++#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0) ++ ++#define ANA_PORT_POL_CFG_GSZ 0x100 ++ ++#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19) ++#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18) ++#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17) ++#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9)) ++#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9) ++#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9) ++#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0)) ++#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0) ++ ++#define ANA_PORT_PTP_CFG_GSZ 0x100 ++ ++#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0) ++ ++#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100 ++ ++#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100 ++ ++#define ANA_PORT_SFID_CFG_GSZ 0x100 ++#define ANA_PORT_SFID_CFG_RSZ 0x4 ++ ++#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8) ++#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0)) ++#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0) ++ ++#define ANA_PFC_PFC_CFG_GSZ 0x40 ++ ++#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2)) ++#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2) ++#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2) ++#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0)) ++#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0) ++ ++#define ANA_PFC_PFC_TIMER_GSZ 0x40 ++#define ANA_PFC_PFC_TIMER_RSZ 0x4 ++ ++#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8 ++ ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6)) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1)) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1) ++#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0) ++ ++#define ANA_IPT_IPT_GSZ 0x8 ++ ++#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15)) ++#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15) ++#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15) ++#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7)) ++#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7) ++#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7) ++#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0)) ++#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0) ++ ++#define ANA_PPT_PPT_RSZ 0x4 ++ ++#define ANA_FID_MAP_FID_MAP_RSZ 0x4 ++ ++#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6)) ++#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6) ++#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6) ++#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0)) ++#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0) ++ ++#define ANA_AGGR_CFG_AC_RND_ENA BIT(7) ++#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6) ++#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5) ++#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4) ++#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3) ++#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2) ++#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1) ++#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0) ++ ++#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27)) ++#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27) ++#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27) ++#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24)) ++#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24) ++#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24) ++#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21)) ++#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21) ++#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21) ++#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18)) ++#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18) ++#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18) ++#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15)) ++#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15) ++#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15) ++#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12)) ++#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12) ++#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12) ++#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9)) ++#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9) ++#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9) ++#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6)) ++#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6) ++#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6) ++#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3)) ++#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3) ++#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3) ++#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0)) ++#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0) ++ ++#define ANA_CPUQ_8021_CFG_RSZ 0x4 ++ ++#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6)) ++#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6) ++#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6) ++#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3)) ++#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3) ++#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3) ++#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0)) ++#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0) ++ ++#define ANA_DSCP_CFG_RSZ 0x4 ++ ++#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) ++#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8)) ++#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8) ++#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8) ++#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2)) ++#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2) ++#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2) ++#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) ++#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) ++ ++#define ANA_DSCP_REWR_CFG_RSZ 0x4 ++ ++#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4 ++ ++#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4 ++ ++#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16)) ++#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16) ++#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0)) ++#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0) ++ ++#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12) ++#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0)) ++#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0) ++ ++#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3) ++#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2) ++#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1) ++#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0) ++ ++#define ANA_FID_CFG_VID_MC_ENA BIT(0) ++ ++#define ANA_POL_PIR_CFG_GSZ 0x20 ++ ++#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) ++#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6) ++#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) ++#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0)) ++#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0) ++ ++#define ANA_POL_CIR_CFG_GSZ 0x20 ++ ++#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) ++#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6) ++#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) ++#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) ++#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0) ++ ++#define ANA_POL_MODE_CFG_GSZ 0x20 ++ ++#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5)) ++#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5) ++#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5) ++#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3)) ++#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3) ++#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3) ++#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2) ++#define ANA_POL_MODE_CFG_CIR_ENA BIT(1) ++#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0) ++ ++#define ANA_POL_PIR_STATE_GSZ 0x20 ++ ++#define ANA_POL_CIR_STATE_GSZ 0x20 ++ ++#define ANA_POL_STATE_GSZ 0x20 ++ ++#define ANA_POL_FLOWC_RSZ 0x4 ++ ++#define ANA_POL_FLOWC_POL_FLOWC BIT(0) ++ ++#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4)) ++#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4) ++#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4) ++#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0)) ++#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0) ++ ++#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1) ++#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0) ++ ++#endif +--- /dev/null ++++ b/include/soc/mscc/ocelot_dev.h +@@ -0,0 +1,275 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++/* ++ * Microsemi Ocelot Switch driver ++ * ++ * Copyright (c) 2017 Microsemi Corporation ++ */ ++ ++#ifndef _MSCC_OCELOT_DEV_H_ ++#define _MSCC_OCELOT_DEV_H_ ++ ++#define DEV_CLOCK_CFG 0x0 ++ ++#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) ++#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) ++#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) ++#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) ++#define DEV_CLOCK_CFG_PORT_RST BIT(3) ++#define DEV_CLOCK_CFG_PHY_RST BIT(2) ++#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) ++#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0) ++ ++#define DEV_PORT_MISC 0x4 ++ ++#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4) ++#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3) ++#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2) ++#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1) ++#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0) ++ ++#define DEV_EVENTS 0x8 ++ ++#define DEV_EEE_CFG 0xc ++ ++#define DEV_EEE_CFG_EEE_ENA BIT(22) ++#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) ++#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15) ++#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) ++#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) ++#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8) ++#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) ++#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) ++#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1) ++#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) ++#define DEV_EEE_CFG_PORT_LPI BIT(0) ++ ++#define DEV_RX_PATH_DELAY 0x10 ++ ++#define DEV_TX_PATH_DELAY 0x14 ++ ++#define DEV_PTP_PREDICT_CFG 0x18 ++ ++#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) ++#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4) ++#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4) ++#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0)) ++#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0) ++ ++#define DEV_MAC_ENA_CFG 0x1c ++ ++#define DEV_MAC_ENA_CFG_RX_ENA BIT(4) ++#define DEV_MAC_ENA_CFG_TX_ENA BIT(0) ++ ++#define DEV_MAC_MODE_CFG 0x20 ++ ++#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) ++#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) ++#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0) ++ ++#define DEV_MAC_MAXLEN_CFG 0x24 ++ ++#define DEV_MAC_TAGS_CFG 0x28 ++ ++#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16)) ++#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16) ++#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2) ++#define DEV_MAC_TAGS_CFG_PB_ENA BIT(1) ++#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) ++ ++#define DEV_MAC_ADV_CHK_CFG 0x2c ++ ++#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) ++ ++#define DEV_MAC_IFG_CFG 0x30 ++ ++#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) ++#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16) ++#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8)) ++#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8) ++#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8) ++#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4)) ++#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4) ++#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4) ++#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0)) ++#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0) ++ ++#define DEV_MAC_HDX_CFG 0x34 ++ ++#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) ++#define DEV_MAC_HDX_CFG_OB_ENA BIT(25) ++#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24) ++#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16)) ++#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16) ++#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16) ++#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) ++#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) ++#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0)) ++#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0) ++ ++#define DEV_MAC_DBG_CFG 0x38 ++ ++#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4) ++#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0) ++ ++#define DEV_MAC_FC_MAC_LOW_CFG 0x3c ++ ++#define DEV_MAC_FC_MAC_HIGH_CFG 0x40 ++ ++#define DEV_MAC_STICKY 0x44 ++ ++#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9) ++#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8) ++#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7) ++#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6) ++#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5) ++#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4) ++#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3) ++#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2) ++#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1) ++#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0) ++ ++#define PCS1G_CFG 0x48 ++ ++#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4) ++#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) ++#define PCS1G_CFG_PCS_ENA BIT(0) ++ ++#define PCS1G_MODE_CFG 0x4c ++ ++#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) ++#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) ++ ++#define PCS1G_SD_CFG 0x50 ++ ++#define PCS1G_SD_CFG_SD_SEL BIT(8) ++#define PCS1G_SD_CFG_SD_POL BIT(4) ++#define PCS1G_SD_CFG_SD_ENA BIT(0) ++ ++#define PCS1G_ANEG_CFG 0x54 ++ ++#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) ++#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16) ++#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) ++#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) ++#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0) ++ ++#define PCS1G_ANEG_NP_CFG 0x58 ++ ++#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16)) ++#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16) ++#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0) ++ ++#define PCS1G_LB_CFG 0x5c ++ ++#define PCS1G_LB_CFG_RA_ENA BIT(4) ++#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) ++#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) ++ ++#define PCS1G_DBG_CFG 0x60 ++ ++#define PCS1G_DBG_CFG_UDLT BIT(0) ++ ++#define PCS1G_CDET_CFG 0x64 ++ ++#define PCS1G_CDET_CFG_CDET_ENA BIT(0) ++ ++#define PCS1G_ANEG_STATUS 0x68 ++ ++#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16)) ++#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16) ++#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16) ++#define PCS1G_ANEG_STATUS_PR BIT(4) ++#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) ++#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) ++ ++#define PCS1G_ANEG_NP_STATUS 0x6c ++ ++#define PCS1G_LINK_STATUS 0x70 ++ ++#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12)) ++#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12) ++#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12) ++#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) ++#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4) ++#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) ++ ++#define PCS1G_LINK_DOWN_CNT 0x74 ++ ++#define PCS1G_STICKY 0x78 ++ ++#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) ++#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) ++ ++#define PCS1G_DEBUG_STATUS 0x7c ++ ++#define PCS1G_LPI_CFG 0x80 ++ ++#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20) ++#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17) ++#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16) ++#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4)) ++#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4) ++#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4) ++#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0) ++ ++#define PCS1G_LPI_WAKE_ERROR_CNT 0x84 ++ ++#define PCS1G_LPI_STATUS 0x88 ++ ++#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16) ++#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12) ++#define PCS1G_LPI_STATUS_RX_QUIET BIT(9) ++#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8) ++#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4) ++#define PCS1G_LPI_STATUS_TX_QUIET BIT(1) ++#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0) ++ ++#define PCS1G_TSTPAT_MODE_CFG 0x8c ++ ++#define PCS1G_TSTPAT_STATUS 0x90 ++ ++#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8)) ++#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8) ++#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8) ++#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4) ++#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0) ++ ++#define DEV_PCS_FX100_CFG 0x94 ++ ++#define DEV_PCS_FX100_CFG_SD_SEL BIT(26) ++#define DEV_PCS_FX100_CFG_SD_POL BIT(25) ++#define DEV_PCS_FX100_CFG_SD_ENA BIT(24) ++#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) ++#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) ++#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12)) ++#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12) ++#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12) ++#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9)) ++#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9) ++#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9) ++#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) ++#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4)) ++#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4) ++#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4) ++#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) ++#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2) ++#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1) ++#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0) ++ ++#define DEV_PCS_FX100_STATUS 0x98 ++ ++#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8)) ++#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8) ++#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8) ++#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) ++#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) ++#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) ++#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) ++#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2) ++#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) ++#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0) ++ ++#endif +--- /dev/null ++++ b/include/soc/mscc/ocelot_qsys.h +@@ -0,0 +1,270 @@ ++/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ ++/* ++ * Microsemi Ocelot Switch driver ++ * ++ * Copyright (c) 2017 Microsemi Corporation ++ */ ++ ++#ifndef _MSCC_OCELOT_QSYS_H_ ++#define _MSCC_OCELOT_QSYS_H_ ++ ++#define QSYS_PORT_MODE_RSZ 0x4 ++ ++#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) ++#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0) ++ ++#define QSYS_SWITCH_PORT_MODE_RSZ 0x4 ++ ++#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14) ++#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11)) ++#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11) ++#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11) ++#define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10) ++#define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9) ++#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1)) ++#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1) ++#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1) ++#define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0) ++ ++#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5) ++#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4) ++#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3) ++#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2) ++#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1) ++#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0) ++ ++#define QSYS_EEE_CFG_RSZ 0x4 ++ ++#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) ++#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8) ++#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) ++#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) ++#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0) ++ ++#define QSYS_SW_STATUS_RSZ 0x4 ++ ++#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) ++#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8) ++#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) ++#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) ++#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0) ++ ++#define QSYS_QMAP_GSZ 0x4 ++ ++#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) ++#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5) ++#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) ++#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) ++#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2) ++#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2) ++#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) ++#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0) ++ ++#define QSYS_ISDX_SGRP_GSZ 0x4 ++ ++#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4 ++ ++#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9)) ++#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9) ++#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9) ++#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8) ++#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7) ++#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) ++#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0) ++ ++#define QSYS_RED_PROFILE_RSZ 0x4 ++ ++#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8)) ++#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8) ++#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8) ++#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) ++#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0) ++ ++#define QSYS_RES_CFG_GSZ 0x8 ++ ++#define QSYS_RES_STAT_GSZ 0x8 ++ ++#define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12)) ++#define QSYS_RES_STAT_INUSE_M GENMASK(23, 12) ++#define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12) ++#define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0)) ++#define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0) ++ ++#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2)) ++#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2) ++#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2) ++#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) ++#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0) ++ ++#define QSYS_QMAXSDU_CFG_0_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_1_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_2_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_3_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_4_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_5_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_6_RSZ 0x4 ++ ++#define QSYS_QMAXSDU_CFG_7_RSZ 0x4 ++ ++#define QSYS_PREEMPTION_CFG_RSZ 0x4 ++ ++#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) ++#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0) ++#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8)) ++#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8) ++#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8) ++#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12)) ++#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12) ++#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12) ++#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16)) ++#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16) ++#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16) ++ ++#define QSYS_CIR_CFG_GSZ 0x80 ++ ++#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6)) ++#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6) ++#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6) ++#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) ++#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0) ++ ++#define QSYS_EIR_CFG_GSZ 0x80 ++ ++#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7)) ++#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7) ++#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7) ++#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1)) ++#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1) ++#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1) ++#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0) ++ ++#define QSYS_SE_CFG_GSZ 0x80 ++ ++#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6)) ++#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6) ++#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6) ++#define QSYS_SE_CFG_SE_RR_ENA BIT(5) ++#define QSYS_SE_CFG_SE_AVB_ENA BIT(4) ++#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2)) ++#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2) ++#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) ++#define QSYS_SE_CFG_SE_EXC_ENA BIT(1) ++#define QSYS_SE_CFG_SE_EXC_FWD BIT(0) ++ ++#define QSYS_SE_DWRR_CFG_GSZ 0x80 ++#define QSYS_SE_DWRR_CFG_RSZ 0x4 ++ ++#define QSYS_SE_CONNECT_GSZ 0x80 ++ ++#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17)) ++#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17) ++#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17) ++#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9)) ++#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9) ++#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9) ++#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5)) ++#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5) ++#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5) ++#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1)) ++#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1) ++#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1) ++#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0) ++ ++#define QSYS_SE_DLB_SENSE_GSZ 0x80 ++ ++#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11)) ++#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11) ++#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11) ++#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7)) ++#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7) ++#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7) ++#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3)) ++#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3) ++#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3) ++#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2) ++#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1) ++#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) ++ ++#define QSYS_CIR_STATE_GSZ 0x80 ++ ++#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4)) ++#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4) ++#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4) ++#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) ++#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0) ++ ++#define QSYS_EIR_STATE_GSZ 0x80 ++ ++#define QSYS_SE_STATE_GSZ 0x80 ++ ++#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1)) ++#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1) ++#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1) ++#define QSYS_SE_STATE_SE_WAS_YEL BIT(0) ++ ++#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8) ++#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3)) ++#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3) ++#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3) ++#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2) ++#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1) ++#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0) ++ ++#define QSYS_TAG_CONFIG_RSZ 0x4 ++ ++#define QSYS_TAG_CONFIG_ENABLE BIT(0) ++#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4)) ++#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4) ++#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4) ++#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) ++#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8) ++#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) ++#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16)) ++#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16) ++#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16) ++ ++#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0)) ++#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0) ++#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8) ++#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16) ++ ++#define QSYS_PORT_MAX_SDU_RSZ 0x4 ++ ++#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) ++#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) ++#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) ++#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16) ++#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) ++ ++#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) ++#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) ++#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) ++#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8) ++#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) ++ ++#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) ++#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0) ++#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16)) ++#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16) ++#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16) ++ ++#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0)) ++#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0) ++#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16)) ++#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16) ++#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16) ++#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24) ++ ++#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0)) ++#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0) ++#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8)) ++#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8) ++#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8) ++ ++#endif |