diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/812-pcie-0013-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/812-pcie-0013-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch | 150 |
1 files changed, 150 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0013-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch b/target/linux/layerscape/patches-5.4/812-pcie-0013-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch new file mode 100644 index 0000000000..6171a621f6 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/812-pcie-0013-PCI-mobiveil-ls_pcie_g4-add-Workaround-for-A-011577.patch @@ -0,0 +1,150 @@ +From 7f38d09c9fd7906cea160e198299a7e378f9c796 Mon Sep 17 00:00:00 2001 +From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> +Date: Tue, 6 Nov 2018 09:44:05 +0800 +Subject: [PATCH] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 + +PCIe configuration access to non-existent function triggered +SERROR interrupt exception. + +Workaround: +Disable error reporting on AXI bus during the Vendor ID read +transactions in enumeration. + +This ERRATA is only for LX2160A Rev1.0, and it will be fixed +in Rev2.0. + +Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> +--- + .../pci/controller/mobiveil/pcie-layerscape-gen4.c | 36 ++++++++++++++++++++++ + .../pci/controller/mobiveil/pcie-mobiveil-host.c | 17 +++++++++- + drivers/pci/controller/mobiveil/pcie-mobiveil.h | 3 ++ + 3 files changed, 55 insertions(+), 1 deletion(-) + +--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c ++++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +@@ -22,8 +22,12 @@ + + #include "pcie-mobiveil.h" + ++#define REV_1_0 (0x10) ++ + /* LUT and PF control registers */ + #define PCIE_LUT_OFF 0x80000 ++#define PCIE_LUT_GCR (0x28) ++#define PCIE_LUT_GCR_RRE (0) + #define PCIE_PF_OFF 0xc0000 + #define PCIE_PF_INT_STAT 0x18 + #define PF_INT_STAT_PABRST BIT(31) +@@ -40,6 +44,7 @@ struct ls_pcie_g4 { + struct mobiveil_pcie pci; + struct delayed_work dwork; + int irq; ++ u8 rev; + }; + + static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) +@@ -75,6 +80,15 @@ static bool ls_pcie_g4_is_bridge(struct + return header_type == PCI_HEADER_TYPE_BRIDGE; + } + ++static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci) ++{ ++ struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); ++ ++ pcie->rev = csr_readb(pci, PCI_REVISION_ID); ++ ++ return 0; ++} ++ + static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) + { + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); +@@ -206,12 +220,34 @@ static void ls_pcie_g4_reset(struct work + ls_pcie_g4_enable_interrupt(pcie); + } + ++static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *val) ++{ ++ struct mobiveil_pcie *pci = bus->sysdata; ++ struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); ++ int ret; ++ ++ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID) ++ ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR, ++ 0 << PCIE_LUT_GCR_RRE); ++ ++ ret = pci_generic_config_read(bus, devfn, where, size, val); ++ ++ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID) ++ ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR, ++ 1 << PCIE_LUT_GCR_RRE); ++ ++ return ret; ++} ++ + static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { + .interrupt_init = ls_pcie_g4_interrupt_init, ++ .read_other_conf = ls_pcie_g4_read_other_conf, + }; + + static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { + .link_up = ls_pcie_g4_link_up, ++ .host_init = ls_pcie_g4_host_init, + }; + + static int __init ls_pcie_g4_probe(struct platform_device *pdev) +--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c ++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +@@ -77,9 +77,20 @@ static void __iomem *mobiveil_pcie_map_b + return pcie->rp.config_axi_slave_base + where; + } + ++static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *val) ++{ ++ struct mobiveil_pcie *pcie = bus->sysdata; ++ struct root_port *rp = &pcie->rp; ++ ++ if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf) ++ return rp->ops->read_other_conf(bus, devfn, where, size, val); ++ ++ return pci_generic_config_read(bus, devfn, where, size, val); ++} + static struct pci_ops mobiveil_pcie_ops = { + .map_bus = mobiveil_pcie_map_bus, +- .read = pci_generic_config_read, ++ .read = mobiveil_pcie_config_read, + .write = pci_generic_config_write, + }; + +@@ -300,6 +311,10 @@ int mobiveil_host_init(struct mobiveil_p + value |= (PCI_CLASS_BRIDGE_PCI << 16); + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); + ++ /* Platform specific host init */ ++ if (pcie->ops->host_init) ++ return pcie->ops->host_init(pcie); ++ + return 0; + } + +--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h ++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h +@@ -146,6 +146,8 @@ struct mobiveil_msi { /* MSI informati + + struct mobiveil_rp_ops { + int (*interrupt_init)(struct mobiveil_pcie *pcie); ++ int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *val); + }; + + struct root_port { +@@ -161,6 +163,7 @@ struct root_port { + + struct mobiveil_pab_ops { + int (*link_up)(struct mobiveil_pcie *pcie); ++ int (*host_init)(struct mobiveil_pcie *pcie); + }; + + struct mobiveil_pcie { |