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-rw-r--r--target/linux/mediatek/patches-4.4/0067-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch45
1 files changed, 45 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.4/0067-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch b/target/linux/mediatek/patches-4.4/0067-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch
new file mode 100644
index 0000000000..5f02dd5820
--- /dev/null
+++ b/target/linux/mediatek/patches-4.4/0067-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch
@@ -0,0 +1,45 @@
+From 429b5becfb1e4aacf392c4b246a17b83faad3072 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 29 Mar 2016 14:32:07 +0200
+Subject: [PATCH 67/78] net: mediatek: update the IRQ part of the binding
+ document
+
+The current binding document only describes a single interrupt. Update the
+document by adding the 2 other interrupts.
+
+The driver currently only uses a single interrupt. The HW is however able
+to using IRQ grouping to split TX and RX onto separate GIC irqs.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+ Acked-by: Rob Herring <robh@kernel.org>
+---
+ Documentation/devicetree/bindings/net/mediatek-net.txt | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+index 5ca7929..2f142be 100644
+--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
++++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
+@@ -9,7 +9,7 @@ have dual GMAC each represented by a child node..
+ Required properties:
+ - compatible: Should be "mediatek,mt7623-eth"
+ - reg: Address and length of the register set for the device
+-- interrupts: Should contain the frame engines interrupt
++- interrupts: Should contain the three frame engines interrupts
+ - clocks: the clock used by the core
+ - clock-names: the names of the clock listed in the clocks property. These are
+ "ethif", "esw", "gp2", "gp1"
+@@ -42,7 +42,9 @@ eth: ethernet@1b100000 {
+ <&ethsys CLK_ETHSYS_GP2>,
+ <&ethsys CLK_ETHSYS_GP1>;
+ clock-names = "ethif", "esw", "gp2", "gp1";
+- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
++ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
++ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
+ reset-names = "eth";
+--
+1.7.10.4
+