diff options
Diffstat (limited to 'target/linux/mediatek/patches/0072-mfd.patch')
| -rw-r--r-- | target/linux/mediatek/patches/0072-mfd.patch | 1577 |
1 files changed, 0 insertions, 1577 deletions
diff --git a/target/linux/mediatek/patches/0072-mfd.patch b/target/linux/mediatek/patches/0072-mfd.patch deleted file mode 100644 index a94b6a1d25..0000000000 --- a/target/linux/mediatek/patches/0072-mfd.patch +++ /dev/null @@ -1,1577 +0,0 @@ -From 1a4dcc30578512d687528adcf963203faee50d83 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 3 Jul 2015 05:45:17 +0200 -Subject: [PATCH 72/76] mfd - ---- - drivers/mfd/mt6323-core.c | 168 +++---- - drivers/regulator/mt6323-regulator.c | 218 ++++---- - include/linux/mfd/mt6323/core.h | 76 +-- - include/linux/mfd/mt6323/registers.h | 745 +++++++++++++++------------- - include/linux/regulator/mt6323-regulator.h | 37 ++ - 5 files changed, 636 insertions(+), 608 deletions(-) - create mode 100644 include/linux/regulator/mt6323-regulator.h - ---- a/drivers/mfd/mt6323-core.c -+++ b/drivers/mfd/mt6323-core.c -@@ -18,111 +18,99 @@ - #include <linux/of_irq.h> - #include <linux/regmap.h> - #include <linux/mfd/core.h> --#include <linux/mfd/mt6397/core.h> --#include <linux/mfd/mt6397/registers.h> -+#include <linux/mfd/mt6323/core.h> -+#include <linux/mfd/mt6323/registers.h> - --static const struct mfd_cell mt6397_devs[] = { -+static const struct mfd_cell mt6323_devs[] = { - { -- .name = "mt6397-rtc", -- .of_compatible = "mediatek,mt6397-rtc", -- }, { -- .name = "mt6397-regulator", -- .of_compatible = "mediatek,mt6397-regulator", -- }, { -- .name = "mt6397-codec", -- .of_compatible = "mediatek,mt6397-codec", -- }, { -- .name = "mt6397-clk", -- .of_compatible = "mediatek,mt6397-clk", -- }, { -- .name = "mediatek-mt6397-pinctrl", -- .of_compatible = "mediatek,mt6397-pinctrl", -+ .name = "mt6323-regulator", -+ .of_compatible = "mediatek,mt6323-regulator", - }, - }; - --static void mt6397_irq_lock(struct irq_data *data) -+static void mt6323_irq_lock(struct irq_data *data) - { -- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); -+ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); - -- mutex_lock(&mt6397->irqlock); -+ mutex_lock(&mt6323->irqlock); - } - --static void mt6397_irq_sync_unlock(struct irq_data *data) -+static void mt6323_irq_sync_unlock(struct irq_data *data) - { -- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); -+ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); - -- regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]); -- regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]); -+ regmap_write(mt6323->regmap, MT6323_INT_CON0, mt6323->irq_masks_cur[0]); -+ regmap_write(mt6323->regmap, MT6323_INT_CON1, mt6323->irq_masks_cur[1]); - -- mutex_unlock(&mt6397->irqlock); -+ mutex_unlock(&mt6323->irqlock); - } - --static void mt6397_irq_disable(struct irq_data *data) -+static void mt6323_irq_disable(struct irq_data *data) - { -- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); -+ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); - int shift = data->hwirq & 0xf; - int reg = data->hwirq >> 4; - -- mt6397->irq_masks_cur[reg] &= ~BIT(shift); -+ mt6323->irq_masks_cur[reg] &= ~BIT(shift); - } - --static void mt6397_irq_enable(struct irq_data *data) -+static void mt6323_irq_enable(struct irq_data *data) - { -- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); -+ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); - int shift = data->hwirq & 0xf; - int reg = data->hwirq >> 4; - -- mt6397->irq_masks_cur[reg] |= BIT(shift); -+ mt6323->irq_masks_cur[reg] |= BIT(shift); - } - --static struct irq_chip mt6397_irq_chip = { -- .name = "mt6397-irq", -- .irq_bus_lock = mt6397_irq_lock, -- .irq_bus_sync_unlock = mt6397_irq_sync_unlock, -- .irq_enable = mt6397_irq_enable, -- .irq_disable = mt6397_irq_disable, -+static struct irq_chip mt6323_irq_chip = { -+ .name = "mt6323-irq", -+ .irq_bus_lock = mt6323_irq_lock, -+ .irq_bus_sync_unlock = mt6323_irq_sync_unlock, -+ .irq_enable = mt6323_irq_enable, -+ .irq_disable = mt6323_irq_disable, - }; - --static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg, -+static void mt6323_irq_handle_reg(struct mt6323_chip *mt6323, int reg, - int irqbase) - { - unsigned int status; - int i, irq, ret; - -- ret = regmap_read(mt6397->regmap, reg, &status); -+ ret = regmap_read(mt6323->regmap, reg, &status); - if (ret) { -- dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret); -+ dev_err(mt6323->dev, "Failed to read irq status: %d\n", ret); - return; - } - - for (i = 0; i < 16; i++) { - if (status & BIT(i)) { -- irq = irq_find_mapping(mt6397->irq_domain, irqbase + i); -+ irq = irq_find_mapping(mt6323->irq_domain, irqbase + i); - if (irq) - handle_nested_irq(irq); - } - } - -- regmap_write(mt6397->regmap, reg, status); -+ regmap_write(mt6323->regmap, reg, status); - } - --static irqreturn_t mt6397_irq_thread(int irq, void *data) -+static irqreturn_t mt6323_irq_thread(int irq, void *data) - { -- struct mt6397_chip *mt6397 = data; -+ struct mt6323_chip *mt6323 = data; - -- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0); -- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16); -+ mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS0, 0); -+ mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS1, 16); - - return IRQ_HANDLED; - } - --static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq, -+static int mt6323_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) - { -- struct mt6397_chip *mt6397 = d->host_data; -+ struct mt6323_chip *mt6323 = d->host_data; - -- irq_set_chip_data(irq, mt6397); -- irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, mt6323); -+ irq_set_chip_and_handler(irq, &mt6323_irq_chip, handle_level_irq); - irq_set_nested_thread(irq, 1); - #ifdef CONFIG_ARM - set_irq_flags(irq, IRQF_VALID); -@@ -133,98 +121,98 @@ static int mt6397_irq_domain_map(struct - return 0; - } - --static struct irq_domain_ops mt6397_irq_domain_ops = { -- .map = mt6397_irq_domain_map, -+static struct irq_domain_ops mt6323_irq_domain_ops = { -+ .map = mt6323_irq_domain_map, - }; - --static int mt6397_irq_init(struct mt6397_chip *mt6397) -+static int mt6323_irq_init(struct mt6323_chip *mt6323) - { - int ret; - -- mutex_init(&mt6397->irqlock); -+ mutex_init(&mt6323->irqlock); - - /* Mask all interrupt sources */ -- regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0); -- regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0); -+ regmap_write(mt6323->regmap, MT6323_INT_CON0, 0x0); -+ regmap_write(mt6323->regmap, MT6323_INT_CON1, 0x0); - -- mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node, -- MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397); -- if (!mt6397->irq_domain) { -- dev_err(mt6397->dev, "could not create irq domain\n"); -+ mt6323->irq_domain = irq_domain_add_linear(mt6323->dev->of_node, -+ MT6323_IRQ_NR, &mt6323_irq_domain_ops, mt6323); -+ if (!mt6323->irq_domain) { -+ dev_err(mt6323->dev, "could not create irq domain\n"); - return -ENOMEM; - } - -- ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL, -- mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397); -+ ret = devm_request_threaded_irq(mt6323->dev, mt6323->irq, NULL, -+ mt6323_irq_thread, IRQF_ONESHOT, "mt6323-pmic", mt6323); - if (ret) { -- dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n", -- mt6397->irq, ret); -+ dev_err(mt6323->dev, "failed to register irq=%d; err: %d\n", -+ mt6323->irq, ret); - return ret; - } - - return 0; - } - --static int mt6397_probe(struct platform_device *pdev) -+static int mt6323_probe(struct platform_device *pdev) - { - int ret; -- struct mt6397_chip *mt6397; -+ struct mt6323_chip *mt6323; - -- mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL); -- if (!mt6397) -+ mt6323 = devm_kzalloc(&pdev->dev, sizeof(*mt6323), GFP_KERNEL); -+ if (!mt6323) - return -ENOMEM; - -- mt6397->dev = &pdev->dev; -+ mt6323->dev = &pdev->dev; - /* -- * mt6397 MFD is child device of soc pmic wrapper. -+ * mt6323 MFD is child device of soc pmic wrapper. - * Regmap is set from its parent. - */ -- mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL); -- if (!mt6397->regmap) -+ mt6323->regmap = dev_get_regmap(pdev->dev.parent, NULL); -+ if (!mt6323->regmap) - return -ENODEV; - -- platform_set_drvdata(pdev, mt6397); -+ platform_set_drvdata(pdev, mt6323); - -- mt6397->irq = platform_get_irq(pdev, 0); -- if (mt6397->irq > 0) { -- ret = mt6397_irq_init(mt6397); -+ mt6323->irq = platform_get_irq(pdev, 0); -+ if (mt6323->irq > 0) { -+ ret = mt6323_irq_init(mt6323); - if (ret) - return ret; - } - -- ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs, -- ARRAY_SIZE(mt6397_devs), NULL, 0, NULL); -+ ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs, -+ ARRAY_SIZE(mt6323_devs), NULL, 0, NULL); - if (ret) - dev_err(&pdev->dev, "failed to add child devices: %d\n", ret); - - return ret; - } - --static int mt6397_remove(struct platform_device *pdev) -+static int mt6323_remove(struct platform_device *pdev) - { - mfd_remove_devices(&pdev->dev); - - return 0; - } - --static const struct of_device_id mt6397_of_match[] = { -- { .compatible = "mediatek,mt6397" }, -+static const struct of_device_id mt6323_of_match[] = { -+ { .compatible = "mediatek,mt6323" }, - { } - }; --MODULE_DEVICE_TABLE(of, mt6397_of_match); -+MODULE_DEVICE_TABLE(of, mt6323_of_match); - --static struct platform_driver mt6397_driver = { -- .probe = mt6397_probe, -- .remove = mt6397_remove, -+static struct platform_driver mt6323_driver = { -+ .probe = mt6323_probe, -+ .remove = mt6323_remove, - .driver = { -- .name = "mt6397", -- .of_match_table = of_match_ptr(mt6397_of_match), -+ .name = "mt6323", -+ .of_match_table = of_match_ptr(mt6323_of_match), - }, - }; - --module_platform_driver(mt6397_driver); -+module_platform_driver(mt6323_driver); - - MODULE_AUTHOR("Flora Fu, MediaTek"); --MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC"); -+MODULE_DESCRIPTION("Driver for MediaTek MT6323 PMIC"); - MODULE_LICENSE("GPL"); --MODULE_ALIAS("platform:mt6397"); -+MODULE_ALIAS("platform:mt6323"); ---- a/drivers/regulator/mt6323-regulator.c -+++ b/drivers/regulator/mt6323-regulator.c -@@ -16,15 +16,15 @@ - #include <linux/of.h> - #include <linux/platform_device.h> - #include <linux/regmap.h> --#include <linux/mfd/mt6397/core.h> --#include <linux/mfd/mt6397/registers.h> -+#include <linux/mfd/mt6323/core.h> -+#include <linux/mfd/mt6323/registers.h> - #include <linux/regulator/driver.h> - #include <linux/regulator/machine.h> --#include <linux/regulator/mt6397-regulator.h> -+#include <linux/regulator/mt6323-regulator.h> - #include <linux/regulator/of_regulator.h> - - /* -- * MT6397 regulators' information -+ * MT6323 regulators' information - * - * @desc: standard fields of regulator description. - * @qi: Mask for query enable signal status of regulators -@@ -32,7 +32,7 @@ - * @vselctrl_reg: Register for controlling the buck control mode. - * @vselctrl_mask: Mask for query buck's voltage control mode. - */ --struct mt6397_regulator_info { -+struct mt6323_regulator_info { - struct regulator_desc desc; - u32 qi; - u32 vselon_reg; -@@ -40,15 +40,15 @@ struct mt6397_regulator_info { - u32 vselctrl_mask; - }; - --#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ -+#define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ - vosel, vosel_mask, voselon, vosel_ctrl) \ --[MT6397_ID_##vreg] = { \ -+[MT6323_ID_##vreg] = { \ - .desc = { \ - .name = #vreg, \ - .of_match = of_match_ptr(match), \ -- .ops = &mt6397_volt_range_ops, \ -+ .ops = &mt6323_volt_range_ops, \ - .type = REGULATOR_VOLTAGE, \ -- .id = MT6397_ID_##vreg, \ -+ .id = MT6323_ID_##vreg, \ - .owner = THIS_MODULE, \ - .n_voltages = (max - min)/step + 1, \ - .linear_ranges = volt_ranges, \ -@@ -64,15 +64,15 @@ struct mt6397_regulator_info { - .vselctrl_mask = BIT(1), \ - } - --#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ -+#define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ - vosel_mask) \ --[MT6397_ID_##vreg] = { \ -+[MT6323_ID_##vreg] = { \ - .desc = { \ - .name = #vreg, \ - .of_match = of_match_ptr(match), \ -- .ops = &mt6397_volt_table_ops, \ -+ .ops = &mt6323_volt_table_ops, \ - .type = REGULATOR_VOLTAGE, \ -- .id = MT6397_ID_##vreg, \ -+ .id = MT6323_ID_##vreg, \ - .owner = THIS_MODULE, \ - .n_voltages = ARRAY_SIZE(ldo_volt_table), \ - .volt_table = ldo_volt_table, \ -@@ -84,14 +84,14 @@ struct mt6397_regulator_info { - .qi = BIT(15), \ - } - --#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ --[MT6397_ID_##vreg] = { \ -+#define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt) \ -+[MT6323_ID_##vreg] = { \ - .desc = { \ - .name = #vreg, \ - .of_match = of_match_ptr(match), \ -- .ops = &mt6397_volt_fixed_ops, \ -+ .ops = &mt6323_volt_fixed_ops, \ - .type = REGULATOR_VOLTAGE, \ -- .id = MT6397_ID_##vreg, \ -+ .id = MT6323_ID_##vreg, \ - .owner = THIS_MODULE, \ - .n_voltages = 1, \ - .enable_reg = enreg, \ -@@ -106,50 +106,34 @@ static const struct regulator_linear_ran - }; - - static const struct regulator_linear_range buck_volt_range2[] = { -- REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250), -+ REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), - }; - - static const struct regulator_linear_range buck_volt_range3[] = { -- REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), -+ REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), - }; - - static const u32 ldo_volt_table1[] = { -- 1500000, 1800000, 2500000, 2800000, -+ 1800000, 3300000, - }; - - static const u32 ldo_volt_table2[] = { -- 1800000, 3300000, -+ 3000000, 3300000, - }; - - static const u32 ldo_volt_table3[] = { -- 3000000, 3300000, -+ 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, - }; - - static const u32 ldo_volt_table4[] = { -- 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, --}; -- --static const u32 ldo_volt_table5[] = { - 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, - }; - --static const u32 ldo_volt_table5_v2[] = { -- 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, --}; -- --static const u32 ldo_volt_table6[] = { -- 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000, --}; -- --static const u32 ldo_volt_table7[] = { -- 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000, --}; -- --static int mt6397_get_status(struct regulator_dev *rdev) -+static int mt6323_get_status(struct regulator_dev *rdev) - { - int ret; - u32 regval; -- struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); -+ struct mt6323_regulator_info *info = rdev_get_drvdata(rdev); - - ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); - if (ret != 0) { -@@ -160,7 +144,7 @@ static int mt6397_get_status(struct regu - return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; - } - --static struct regulator_ops mt6397_volt_range_ops = { -+static struct regulator_ops mt6323_volt_range_ops = { - .list_voltage = regulator_list_voltage_linear_range, - .map_voltage = regulator_map_voltage_linear_range, - .set_voltage_sel = regulator_set_voltage_sel_regmap, -@@ -169,10 +153,10 @@ static struct regulator_ops mt6397_volt_ - .enable = regulator_enable_regmap, - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, -- .get_status = mt6397_get_status, -+ .get_status = mt6323_get_status, - }; - --static struct regulator_ops mt6397_volt_table_ops = { -+static struct regulator_ops mt6323_volt_table_ops = { - .list_voltage = regulator_list_voltage_table, - .map_voltage = regulator_map_voltage_iterate, - .set_voltage_sel = regulator_set_voltage_sel_regmap, -@@ -181,90 +165,68 @@ static struct regulator_ops mt6397_volt_ - .enable = regulator_enable_regmap, - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, -- .get_status = mt6397_get_status, -+ .get_status = mt6323_get_status, - }; - --static struct regulator_ops mt6397_volt_fixed_ops = { -+static struct regulator_ops mt6323_volt_fixed_ops = { - .list_voltage = regulator_list_voltage_linear, - .enable = regulator_enable_regmap, - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, -- .get_status = mt6397_get_status, -+ .get_status = mt6323_get_status, - }; - --/* The array is indexed by id(MT6397_ID_XXX) */ --static struct mt6397_regulator_info mt6397_regulators[] = { -- MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250, -- buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f, -- MT6397_VCA15_CON10, MT6397_VCA15_CON5), -- MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250, -- buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f, -- MT6397_VPCA7_CON10, MT6397_VPCA7_CON5), -- MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250, -- buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9, -- 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5), -- MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250, -- buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9, -- 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5), -- MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, -- buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f, -- MT6397_VCORE_CON10, MT6397_VCORE_CON5), -- MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1, -- MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f, -- MT6397_VGPU_CON10, MT6397_VGPU_CON5), -- MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2, -- MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f, -- MT6397_VDRM_CON10, MT6397_VDRM_CON5), -- MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, -- buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f, -- MT6397_VIO18_CON10, MT6397_VIO18_CON5), -- MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000), -- MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000), -- MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1, -- MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0), -- MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000), -- MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000), -- MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2, -- MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10), -- MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3, -- MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80), -- MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3, -- MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10), -- MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4, -- MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0), -- MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5, -- MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0), -- MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5, -- MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0), -- MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5, -- MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0), -- MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6, -- MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0), -- MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5, -- MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0), -- MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7, -- MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00), -+/* The array is indexed by id(MT6323_ID_XXX) */ -+static struct mt6323_regulator_info mt6323_regulators[] = { -+ /* buck */ -+ MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, -+ buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f, -+ MT6323_VPROC_CON10, MT6323_VPROC_CON5), -+ MT6323_BUCK("buck_vsys", VSYS, 1400000, 3000000, 12500, -+ buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9, -+ 0x7f, MT6323_VSYS_CON10, MT6323_VSYS_CON5), -+ MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, -+ buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9, 0x7f, -+ MT6323_VPA_CON10, MT6323_VPA_CON5), -+ -+ /* analog */ -+ MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000), -+ MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000), -+ MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000), -+ MT6323_REG_FIXED("ldo_vcn33", VCN33, MT6323_ANALDO_CON21, 12, 3300000), -+ -+ /* digital */ -+ MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 15, 2800000), -+ MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 15, 3300000), -+ MT6323_LDO("ldo_vmc", VMC, ldo_volt_table1, -+ MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10), -+ MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table2, -+ MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80), -+ MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table3, -+ MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0), -+ MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table4, -+ MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0), - }; - --static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) -+static int mt6323_set_buck_vosel_reg(struct platform_device *pdev) - { -- struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); -+ struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent); - int i; - u32 regval; - -- for (i = 0; i < MT6397_MAX_REGULATOR; i++) { -- if (mt6397_regulators[i].vselctrl_reg) { -- if (regmap_read(mt6397->regmap, -- mt6397_regulators[i].vselctrl_reg, -+ for (i = 0; i < MT6323_MAX_REGULATOR; i++) { -+ if (mt6323_regulators[i].vselctrl_reg) { -+ if (regmap_read(mt6323->regmap, -+ mt6323_regulators[i].vselctrl_reg, - ®val) < 0) { - dev_err(&pdev->dev, - "Failed to read buck ctrl\n"); - return -EIO; - } - -- if (regval & mt6397_regulators[i].vselctrl_mask) { -- mt6397_regulators[i].desc.vsel_reg = -- mt6397_regulators[i].vselon_reg; -+ if (regval & mt6323_regulators[i].vselctrl_mask) { -+ mt6323_regulators[i].desc.vsel_reg = -+ mt6323_regulators[i].vselon_reg; - } - } - } -@@ -272,44 +234,34 @@ static int mt6397_set_buck_vosel_reg(str - return 0; - } - --static int mt6397_regulator_probe(struct platform_device *pdev) -+static int mt6323_regulator_probe(struct platform_device *pdev) - { -- struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); -+ struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent); - struct regulator_config config = {}; - struct regulator_dev *rdev; - int i; -- u32 reg_value, version; -+ u32 reg_value; - - /* Query buck controller to select activated voltage register part */ -- if (mt6397_set_buck_vosel_reg(pdev)) -+ if (mt6323_set_buck_vosel_reg(pdev)) - return -EIO; - - /* Read PMIC chip revision to update constraints and voltage table */ -- if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { -+ if (regmap_read(mt6323->regmap, MT6323_CID, ®_value) < 0) { - dev_err(&pdev->dev, "Failed to read Chip ID\n"); - return -EIO; - } - dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); - -- version = (reg_value & 0xFF); -- switch (version) { -- case MT6397_REGULATOR_ID91: -- mt6397_regulators[MT6397_ID_VGP2].desc.volt_table = -- ldo_volt_table5_v2; -- break; -- default: -- break; -- } -- -- for (i = 0; i < MT6397_MAX_REGULATOR; i++) { -+ for (i = 0; i < MT6323_MAX_REGULATOR; i++) { - config.dev = &pdev->dev; -- config.driver_data = &mt6397_regulators[i]; -- config.regmap = mt6397->regmap; -+ config.driver_data = &mt6323_regulators[i]; -+ config.regmap = mt6323->regmap; - rdev = devm_regulator_register(&pdev->dev, -- &mt6397_regulators[i].desc, &config); -+ &mt6323_regulators[i].desc, &config); - if (IS_ERR(rdev)) { - dev_err(&pdev->dev, "failed to register %s\n", -- mt6397_regulators[i].desc.name); -+ mt6323_regulators[i].desc.name); - return PTR_ERR(rdev); - } - } -@@ -317,16 +269,16 @@ static int mt6397_regulator_probe(struct - return 0; - } - --static struct platform_driver mt6397_regulator_driver = { -+static struct platform_driver mt6323_regulator_driver = { - .driver = { -- .name = "mt6397-regulator", -+ .name = "mt6323-regulator", - }, -- .probe = mt6397_regulator_probe, -+ .probe = mt6323_regulator_probe, - }; - --module_platform_driver(mt6397_regulator_driver); -+module_platform_driver(mt6323_regulator_driver); - - MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>"); --MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC"); -+MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC"); - MODULE_LICENSE("GPL"); --MODULE_ALIAS("platform:mt6397-regulator"); -+MODULE_ALIAS("platform:mt6323-regulator"); ---- a/include/linux/mfd/mt6323/core.h -+++ b/include/linux/mfd/mt6323/core.h -@@ -12,46 +12,46 @@ - * GNU General Public License for more details. - */ - --#ifndef __MFD_MT6397_CORE_H__ --#define __MFD_MT6397_CORE_H__ -+#ifndef __MFD_MT6323_CORE_H__ -+#define __MFD_MT6323_CORE_H__ - --enum mt6397_irq_numbers { -- MT6397_IRQ_SPKL_AB = 0, -- MT6397_IRQ_SPKR_AB, -- MT6397_IRQ_SPKL, -- MT6397_IRQ_SPKR, -- MT6397_IRQ_BAT_L, -- MT6397_IRQ_BAT_H, -- MT6397_IRQ_FG_BAT_L, -- MT6397_IRQ_FG_BAT_H, -- MT6397_IRQ_WATCHDOG, -- MT6397_IRQ_PWRKEY, -- MT6397_IRQ_THR_L, -- MT6397_IRQ_THR_H, -- MT6397_IRQ_VBATON_UNDET, -- MT6397_IRQ_BVALID_DET, -- MT6397_IRQ_CHRDET, -- MT6397_IRQ_OV, -- MT6397_IRQ_LDO, -- MT6397_IRQ_HOMEKEY, -- MT6397_IRQ_ACCDET, -- MT6397_IRQ_AUDIO, -- MT6397_IRQ_RTC, -- MT6397_IRQ_PWRKEY_RSTB, -- MT6397_IRQ_HDMI_SIFM, -- MT6397_IRQ_HDMI_CEC, -- MT6397_IRQ_VCA15, -- MT6397_IRQ_VSRMCA15, -- MT6397_IRQ_VCORE, -- MT6397_IRQ_VGPU, -- MT6397_IRQ_VIO18, -- MT6397_IRQ_VPCA7, -- MT6397_IRQ_VSRMCA7, -- MT6397_IRQ_VDRM, -- MT6397_IRQ_NR, -+enum mt6323_irq_numbers { -+ MT6323_IRQ_SPKL_AB = 0, -+ MT6323_IRQ_SPKR_AB, -+ MT6323_IRQ_SPKL, -+ MT6323_IRQ_SPKR, -+ MT6323_IRQ_BAT_L, -+ MT6323_IRQ_BAT_H, -+ MT6323_IRQ_FG_BAT_L, -+ MT6323_IRQ_FG_BAT_H, -+ MT6323_IRQ_WATCHDOG, -+ MT6323_IRQ_PWRKEY, -+ MT6323_IRQ_THR_L, -+ MT6323_IRQ_THR_H, -+ MT6323_IRQ_VBATON_UNDET, -+ MT6323_IRQ_BVALID_DET, -+ MT6323_IRQ_CHRDET, -+ MT6323_IRQ_OV, -+ MT6323_IRQ_LDO, -+ MT6323_IRQ_HOMEKEY, -+ MT6323_IRQ_ACCDET, -+ MT6323_IRQ_AUDIO, -+ MT6323_IRQ_RTC, -+ MT6323_IRQ_PWRKEY_RSTB, -+ MT6323_IRQ_HDMI_SIFM, -+ MT6323_IRQ_HDMI_CEC, -+ MT6323_IRQ_VCA15, -+ MT6323_IRQ_VSRMCA15, -+ MT6323_IRQ_VCORE, -+ MT6323_IRQ_VGPU, -+ MT6323_IRQ_VIO18, -+ MT6323_IRQ_VPCA7, -+ MT6323_IRQ_VSRMCA7, -+ MT6323_IRQ_VDRM, -+ MT6323_IRQ_NR, - }; - --struct mt6397_chip { -+struct mt6323_chip { - struct device *dev; - struct regmap *regmap; - int irq; -@@ -61,4 +61,4 @@ struct mt6397_chip { - u16 irq_masks_cache[2]; - }; - --#endif /* __MFD_MT6397_CORE_H__ */ -+#endif /* __MFD_MT6323_CORE_H__ */ ---- a/include/linux/mfd/mt6323/registers.h -+++ b/include/linux/mfd/mt6323/registers.h -@@ -1,6 +1,5 @@ - /* -- * Copyright (c) 2014 MediaTek Inc. -- * Author: Flora Fu, MediaTek -+ * Copyright (c) 2015 - John Crispin <blogic@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as -@@ -12,351 +11,403 @@ - * GNU General Public License for more details. - */ - --#ifndef __MFD_MT6397_REGISTERS_H__ --#define __MFD_MT6397_REGISTERS_H__ -+#ifndef __MFD_MT6323_REGISTERS_H__ -+#define __MFD_MT6323_REGISTERS_H__ - - /* PMIC Registers */ --#define MT6397_CID 0x0100 --#define MT6397_TOP_CKPDN 0x0102 --#define MT6397_TOP_CKPDN_SET 0x0104 --#define MT6397_TOP_CKPDN_CLR 0x0106 --#define MT6397_TOP_CKPDN2 0x0108 --#define MT6397_TOP_CKPDN2_SET 0x010A --#define MT6397_TOP_CKPDN2_CLR 0x010C --#define MT6397_TOP_GPIO_CKPDN 0x010E --#define MT6397_TOP_RST_CON 0x0114 --#define MT6397_WRP_CKPDN 0x011A --#define MT6397_WRP_RST_CON 0x0120 --#define MT6397_TOP_RST_MISC 0x0126 --#define MT6397_TOP_CKCON1 0x0128 --#define MT6397_TOP_CKCON2 0x012A --#define MT6397_TOP_CKTST1 0x012C --#define MT6397_TOP_CKTST2 0x012E --#define MT6397_OC_DEG_EN 0x0130 --#define MT6397_OC_CTL0 0x0132 --#define MT6397_OC_CTL1 0x0134 --#define MT6397_OC_CTL2 0x0136 --#define MT6397_INT_RSV 0x0138 --#define MT6397_TEST_CON0 0x013A --#define MT6397_TEST_CON1 0x013C --#define MT6397_STATUS0 0x013E --#define MT6397_STATUS1 0x0140 --#define MT6397_PGSTATUS 0x0142 --#define MT6397_CHRSTATUS 0x0144 --#define MT6397_OCSTATUS0 0x0146 --#define MT6397_OCSTATUS1 0x0148 --#define MT6397_OCSTATUS2 0x014A --#define MT6397_HDMI_PAD_IE 0x014C --#define MT6397_TEST_OUT_L 0x014E --#define MT6397_TEST_OUT_H 0x0150 --#define MT6397_TDSEL_CON 0x0152 --#define MT6397_RDSEL_CON 0x0154 --#define MT6397_GPIO_SMT_CON0 0x0156 --#define MT6397_GPIO_SMT_CON1 0x0158 --#define MT6397_GPIO_SMT_CON2 0x015A --#define MT6397_GPIO_SMT_CON3 0x015C --#define MT6397_DRV_CON0 0x015E --#define MT6397_DRV_CON1 0x0160 --#define MT6397_DRV_CON2 0x0162 --#define MT6397_DRV_CON3 0x0164 --#define MT6397_DRV_CON4 0x0166 --#define MT6397_DRV_CON5 0x0168 --#define MT6397_DRV_CON6 0x016A --#define MT6397_DRV_CON7 0x016C --#define MT6397_DRV_CON8 0x016E --#define MT6397_DRV_CON9 0x0170 --#define MT6397_DRV_CON10 0x0172 --#define MT6397_DRV_CON11 0x0174 --#define MT6397_DRV_CON12 0x0176 --#define MT6397_INT_CON0 0x0178 --#define MT6397_INT_CON1 0x017E --#define MT6397_INT_STATUS0 0x0184 --#define MT6397_INT_STATUS1 0x0186 --#define MT6397_FQMTR_CON0 0x0188 --#define MT6397_FQMTR_CON1 0x018A --#define MT6397_FQMTR_CON2 0x018C --#define MT6397_EFUSE_DOUT_0_15 0x01C4 --#define MT6397_EFUSE_DOUT_16_31 0x01C6 --#define MT6397_EFUSE_DOUT_32_47 0x01C8 --#define MT6397_EFUSE_DOUT_48_63 0x01CA --#define MT6397_SPI_CON 0x01CC --#define MT6397_TOP_CKPDN3 0x01CE --#define MT6397_TOP_CKCON3 0x01D4 --#define MT6397_EFUSE_DOUT_64_79 0x01D6 --#define MT6397_EFUSE_DOUT_80_95 0x01D8 --#define MT6397_EFUSE_DOUT_96_111 0x01DA --#define MT6397_EFUSE_DOUT_112_127 0x01DC --#define MT6397_EFUSE_DOUT_128_143 0x01DE --#define MT6397_EFUSE_DOUT_144_159 0x01E0 --#define MT6397_EFUSE_DOUT_160_175 0x01E2 --#define MT6397_EFUSE_DOUT_176_191 0x01E4 --#define MT6397_EFUSE_DOUT_192_207 0x01E6 --#define MT6397_EFUSE_DOUT_208_223 0x01E8 --#define MT6397_EFUSE_DOUT_224_239 0x01EA --#define MT6397_EFUSE_DOUT_240_255 0x01EC --#define MT6397_EFUSE_DOUT_256_271 0x01EE --#define MT6397_EFUSE_DOUT_272_287 0x01F0 --#define MT6397_EFUSE_DOUT_288_300 0x01F2 --#define MT6397_EFUSE_DOUT_304_319 0x01F4 --#define MT6397_BUCK_CON0 0x0200 --#define MT6397_BUCK_CON1 0x0202 --#define MT6397_BUCK_CON2 0x0204 --#define MT6397_BUCK_CON3 0x0206 --#define MT6397_BUCK_CON4 0x0208 --#define MT6397_BUCK_CON5 0x020A --#define MT6397_BUCK_CON6 0x020C --#define MT6397_BUCK_CON7 0x020E --#define MT6397_BUCK_CON8 0x0210 --#define MT6397_BUCK_CON9 0x0212 --#define MT6397_VCA15_CON0 0x0214 --#define MT6397_VCA15_CON1 0x0216 --#define MT6397_VCA15_CON2 0x0218 --#define MT6397_VCA15_CON3 0x021A --#define MT6397_VCA15_CON4 0x021C --#define MT6397_VCA15_CON5 0x021E --#define MT6397_VCA15_CON6 0x0220 --#define MT6397_VCA15_CON7 0x0222 --#define MT6397_VCA15_CON8 0x0224 --#define MT6397_VCA15_CON9 0x0226 --#define MT6397_VCA15_CON10 0x0228 --#define MT6397_VCA15_CON11 0x022A --#define MT6397_VCA15_CON12 0x022C --#define MT6397_VCA15_CON13 0x022E --#define MT6397_VCA15_CON14 0x0230 --#define MT6397_VCA15_CON15 0x0232 --#define MT6397_VCA15_CON16 0x0234 --#define MT6397_VCA15_CON17 0x0236 --#define MT6397_VCA15_CON18 0x0238 --#define MT6397_VSRMCA15_CON0 0x023A --#define MT6397_VSRMCA15_CON1 0x023C --#define MT6397_VSRMCA15_CON2 0x023E --#define MT6397_VSRMCA15_CON3 0x0240 --#define MT6397_VSRMCA15_CON4 0x0242 --#define MT6397_VSRMCA15_CON5 0x0244 --#define MT6397_VSRMCA15_CON6 0x0246 --#define MT6397_VSRMCA15_CON7 0x0248 --#define MT6397_VSRMCA15_CON8 0x024A --#define MT6397_VSRMCA15_CON9 0x024C --#define MT6397_VSRMCA15_CON10 0x024E --#define MT6397_VSRMCA15_CON11 0x0250 --#define MT6397_VSRMCA15_CON12 0x0252 --#define MT6397_VSRMCA15_CON13 0x0254 --#define MT6397_VSRMCA15_CON14 0x0256 --#define MT6397_VSRMCA15_CON15 0x0258 --#define MT6397_VSRMCA15_CON16 0x025A --#define MT6397_VSRMCA15_CON17 0x025C --#define MT6397_VSRMCA15_CON18 0x025E --#define MT6397_VSRMCA15_CON19 0x0260 --#define MT6397_VSRMCA15_CON20 0x0262 --#define MT6397_VSRMCA15_CON21 0x0264 --#define MT6397_VCORE_CON0 0x0266 --#define MT6397_VCORE_CON1 0x0268 --#define MT6397_VCORE_CON2 0x026A --#define MT6397_VCORE_CON3 0x026C --#define MT6397_VCORE_CON4 0x026E --#define MT6397_VCORE_CON5 0x0270 --#define MT6397_VCORE_CON6 0x0272 --#define MT6397_VCORE_CON7 0x0274 --#define MT6397_VCORE_CON8 0x0276 --#define MT6397_VCORE_CON9 0x0278 --#define MT6397_VCORE_CON10 0x027A --#define MT6397_VCORE_CON11 0x027C --#define MT6397_VCORE_CON12 0x027E --#define MT6397_VCORE_CON13 0x0280 --#define MT6397_VCORE_CON14 0x0282 --#define MT6397_VCORE_CON15 0x0284 --#define MT6397_VCORE_CON16 0x0286 --#define MT6397_VCORE_CON17 0x0288 --#define MT6397_VCORE_CON18 0x028A --#define MT6397_VGPU_CON0 0x028C --#define MT6397_VGPU_CON1 0x028E --#define MT6397_VGPU_CON2 0x0290 --#define MT6397_VGPU_CON3 0x0292 --#define MT6397_VGPU_CON4 0x0294 --#define MT6397_VGPU_CON5 0x0296 --#define MT6397_VGPU_CON6 0x0298 --#define MT6397_VGPU_CON7 0x029A --#define MT6397_VGPU_CON8 0x029C --#define MT6397_VGPU_CON9 0x029E --#define MT6397_VGPU_CON10 0x02A0 --#define MT6397_VGPU_CON11 0x02A2 --#define MT6397_VGPU_CON12 0x02A4 --#define MT6397_VGPU_CON13 0x02A6 --#define MT6397_VGPU_CON14 0x02A8 --#define MT6397_VGPU_CON15 0x02AA --#define MT6397_VGPU_CON16 0x02AC --#define MT6397_VGPU_CON17 0x02AE --#define MT6397_VGPU_CON18 0x02B0 --#define MT6397_VIO18_CON0 0x0300 --#define MT6397_VIO18_CON1 0x0302 --#define MT6397_VIO18_CON2 0x0304 --#define MT6397_VIO18_CON3 0x0306 --#define MT6397_VIO18_CON4 0x0308 --#define MT6397_VIO18_CON5 0x030A --#define MT6397_VIO18_CON6 0x030C --#define MT6397_VIO18_CON7 0x030E --#define MT6397_VIO18_CON8 0x0310 --#define MT6397_VIO18_CON9 0x0312 --#define MT6397_VIO18_CON10 0x0314 --#define MT6397_VIO18_CON11 0x0316 --#define MT6397_VIO18_CON12 0x0318 --#define MT6397_VIO18_CON13 0x031A --#define MT6397_VIO18_CON14 0x031C --#define MT6397_VIO18_CON15 0x031E --#define MT6397_VIO18_CON16 0x0320 --#define MT6397_VIO18_CON17 0x0322 --#define MT6397_VIO18_CON18 0x0324 --#define MT6397_VPCA7_CON0 0x0326 --#define MT6397_VPCA7_CON1 0x0328 --#define MT6397_VPCA7_CON2 0x032A --#define MT6397_VPCA7_CON3 0x032C --#define MT6397_VPCA7_CON4 0x032E --#define MT6397_VPCA7_CON5 0x0330 --#define MT6397_VPCA7_CON6 0x0332 --#define MT6397_VPCA7_CON7 0x0334 --#define MT6397_VPCA7_CON8 0x0336 --#define MT6397_VPCA7_CON9 0x0338 --#define MT6397_VPCA7_CON10 0x033A --#define MT6397_VPCA7_CON11 0x033C --#define MT6397_VPCA7_CON12 0x033E --#define MT6397_VPCA7_CON13 0x0340 --#define MT6397_VPCA7_CON14 0x0342 --#define MT6397_VPCA7_CON15 0x0344 --#define MT6397_VPCA7_CON16 0x0346 --#define MT6397_VPCA7_CON17 0x0348 --#define MT6397_VPCA7_CON18 0x034A --#define MT6397_VSRMCA7_CON0 0x034C --#define MT6397_VSRMCA7_CON1 0x034E --#define MT6397_VSRMCA7_CON2 0x0350 --#define MT6397_VSRMCA7_CON3 0x0352 --#define MT6397_VSRMCA7_CON4 0x0354 --#define MT6397_VSRMCA7_CON5 0x0356 --#define MT6397_VSRMCA7_CON6 0x0358 --#define MT6397_VSRMCA7_CON7 0x035A --#define MT6397_VSRMCA7_CON8 0x035C --#define MT6397_VSRMCA7_CON9 0x035E --#define MT6397_VSRMCA7_CON10 0x0360 --#define MT6397_VSRMCA7_CON11 0x0362 --#define MT6397_VSRMCA7_CON12 0x0364 --#define MT6397_VSRMCA7_CON13 0x0366 --#define MT6397_VSRMCA7_CON14 0x0368 --#define MT6397_VSRMCA7_CON15 0x036A --#define MT6397_VSRMCA7_CON16 0x036C --#define MT6397_VSRMCA7_CON17 0x036E --#define MT6397_VSRMCA7_CON18 0x0370 --#define MT6397_VSRMCA7_CON19 0x0372 --#define MT6397_VSRMCA7_CON20 0x0374 --#define MT6397_VSRMCA7_CON21 0x0376 --#define MT6397_VDRM_CON0 0x0378 --#define MT6397_VDRM_CON1 0x037A --#define MT6397_VDRM_CON2 0x037C --#define MT6397_VDRM_CON3 0x037E --#define MT6397_VDRM_CON4 0x0380 --#define MT6397_VDRM_CON5 0x0382 --#define MT6397_VDRM_CON6 0x0384 --#define MT6397_VDRM_CON7 0x0386 --#define MT6397_VDRM_CON8 0x0388 --#define MT6397_VDRM_CON9 0x038A --#define MT6397_VDRM_CON10 0x038C --#define MT6397_VDRM_CON11 0x038E --#define MT6397_VDRM_CON12 0x0390 --#define MT6397_VDRM_CON13 0x0392 --#define MT6397_VDRM_CON14 0x0394 --#define MT6397_VDRM_CON15 0x0396 --#define MT6397_VDRM_CON16 0x0398 --#define MT6397_VDRM_CON17 0x039A --#define MT6397_VDRM_CON18 0x039C --#define MT6397_BUCK_K_CON0 0x039E --#define MT6397_BUCK_K_CON1 0x03A0 --#define MT6397_ANALDO_CON0 0x0400 --#define MT6397_ANALDO_CON1 0x0402 --#define MT6397_ANALDO_CON2 0x0404 --#define MT6397_ANALDO_CON3 0x0406 --#define MT6397_ANALDO_CON4 0x0408 --#define MT6397_ANALDO_CON5 0x040A --#define MT6397_ANALDO_CON6 0x040C --#define MT6397_ANALDO_CON7 0x040E --#define MT6397_DIGLDO_CON0 0x0410 --#define MT6397_DIGLDO_CON1 0x0412 --#define MT6397_DIGLDO_CON2 0x0414 --#define MT6397_DIGLDO_CON3 0x0416 --#define MT6397_DIGLDO_CON4 0x0418 --#define MT6397_DIGLDO_CON5 0x041A --#define MT6397_DIGLDO_CON6 0x041C --#define MT6397_DIGLDO_CON7 0x041E --#define MT6397_DIGLDO_CON8 0x0420 --#define MT6397_DIGLDO_CON9 0x0422 --#define MT6397_DIGLDO_CON10 0x0424 --#define MT6397_DIGLDO_CON11 0x0426 --#define MT6397_DIGLDO_CON12 0x0428 --#define MT6397_DIGLDO_CON13 0x042A --#define MT6397_DIGLDO_CON14 0x042C --#define MT6397_DIGLDO_CON15 0x042E --#define MT6397_DIGLDO_CON16 0x0430 --#define MT6397_DIGLDO_CON17 0x0432 --#define MT6397_DIGLDO_CON18 0x0434 --#define MT6397_DIGLDO_CON19 0x0436 --#define MT6397_DIGLDO_CON20 0x0438 --#define MT6397_DIGLDO_CON21 0x043A --#define MT6397_DIGLDO_CON22 0x043C --#define MT6397_DIGLDO_CON23 0x043E --#define MT6397_DIGLDO_CON24 0x0440 --#define MT6397_DIGLDO_CON25 0x0442 --#define MT6397_DIGLDO_CON26 0x0444 --#define MT6397_DIGLDO_CON27 0x0446 --#define MT6397_DIGLDO_CON28 0x0448 --#define MT6397_DIGLDO_CON29 0x044A --#define MT6397_DIGLDO_CON30 0x044C --#define MT6397_DIGLDO_CON31 0x044E --#define MT6397_DIGLDO_CON32 0x0450 --#define MT6397_DIGLDO_CON33 0x045A --#define MT6397_SPK_CON0 0x0600 --#define MT6397_SPK_CON1 0x0602 --#define MT6397_SPK_CON2 0x0604 --#define MT6397_SPK_CON3 0x0606 --#define MT6397_SPK_CON4 0x0608 --#define MT6397_SPK_CON5 0x060A --#define MT6397_SPK_CON6 0x060C --#define MT6397_SPK_CON7 0x060E --#define MT6397_SPK_CON8 0x0610 --#define MT6397_SPK_CON9 0x0612 --#define MT6397_SPK_CON10 0x0614 --#define MT6397_SPK_CON11 0x0616 --#define MT6397_AUDDAC_CON0 0x0700 --#define MT6397_AUDBUF_CFG0 0x0702 --#define MT6397_AUDBUF_CFG1 0x0704 --#define MT6397_AUDBUF_CFG2 0x0706 --#define MT6397_AUDBUF_CFG3 0x0708 --#define MT6397_AUDBUF_CFG4 0x070A --#define MT6397_IBIASDIST_CFG0 0x070C --#define MT6397_AUDACCDEPOP_CFG0 0x070E --#define MT6397_AUD_IV_CFG0 0x0710 --#define MT6397_AUDCLKGEN_CFG0 0x0712 --#define MT6397_AUDLDO_CFG0 0x0714 --#define MT6397_AUDLDO_CFG1 0x0716 --#define MT6397_AUDNVREGGLB_CFG0 0x0718 --#define MT6397_AUD_NCP0 0x071A --#define MT6397_AUDPREAMP_CON0 0x071C --#define MT6397_AUDADC_CON0 0x071E --#define MT6397_AUDADC_CON1 0x0720 --#define MT6397_AUDADC_CON2 0x0722 --#define MT6397_AUDADC_CON3 0x0724 --#define MT6397_AUDADC_CON4 0x0726 --#define MT6397_AUDADC_CON5 0x0728 --#define MT6397_AUDADC_CON6 0x072A --#define MT6397_AUDDIGMI_CON0 0x072C --#define MT6397_AUDLSBUF_CON0 0x072E --#define MT6397_AUDLSBUF_CON1 0x0730 --#define MT6397_AUDENCSPARE_CON0 0x0732 --#define MT6397_AUDENCCLKSQ_CON0 0x0734 --#define MT6397_AUDPREAMPGAIN_CON0 0x0736 --#define MT6397_ZCD_CON0 0x0738 --#define MT6397_ZCD_CON1 0x073A --#define MT6397_ZCD_CON2 0x073C --#define MT6397_ZCD_CON3 0x073E --#define MT6397_ZCD_CON4 0x0740 --#define MT6397_ZCD_CON5 0x0742 --#define MT6397_NCP_CLKDIV_CON0 0x0744 --#define MT6397_NCP_CLKDIV_CON1 0x0746 -+#define MT6323_CHR_CON0 0x0000 -+#define MT6323_CHR_CON1 0x0002 -+#define MT6323_CHR_CON2 0x0004 -+#define MT6323_CHR_CON3 0x0006 -+#define MT6323_CHR_CON4 0x0008 -+#define MT6323_CHR_CON5 0x000A -+#define MT6323_CHR_CON6 0x000C -+#define MT6323_CHR_CON7 0x000E -+#define MT6323_CHR_CON8 0x0010 -+#define MT6323_CHR_CON9 0x0012 -+#define MT6323_CHR_CON10 0x0014 -+#define MT6323_CHR_CON11 0x0016 -+#define MT6323_CHR_CON12 0x0018 -+#define MT6323_CHR_CON13 0x001A -+#define MT6323_CHR_CON14 0x001C -+#define MT6323_CHR_CON15 0x001E -+#define MT6323_CHR_CON16 0x0020 -+#define MT6323_CHR_CON17 0x0022 -+#define MT6323_CHR_CON18 0x0024 -+#define MT6323_CHR_CON19 0x0026 -+#define MT6323_CHR_CON20 0x0028 -+#define MT6323_CHR_CON21 0x002A -+#define MT6323_CHR_CON22 0x002C -+#define MT6323_CHR_CON23 0x002E -+#define MT6323_CHR_CON24 0x0030 -+#define MT6323_CHR_CON25 0x0032 -+#define MT6323_CHR_CON26 0x0034 -+#define MT6323_CHR_CON27 0x0036 -+#define MT6323_CHR_CON28 0x0038 -+#define MT6323_CHR_CON29 0x003A -+#define MT6323_STRUP_CON0 0x003C -+#define MT6323_STRUP_CON2 0x003E -+#define MT6323_STRUP_CON3 0x0040 -+#define MT6323_STRUP_CON4 0x0042 -+#define MT6323_STRUP_CON5 0x0044 -+#define MT6323_STRUP_CON6 0x0046 -+#define MT6323_STRUP_CON7 0x0048 -+#define MT6323_STRUP_CON8 0x004A -+#define MT6323_STRUP_CON9 0x004C -+#define MT6323_STRUP_CON10 0x004E -+#define MT6323_STRUP_CON11 0x0050 -+#define MT6323_SPK_CON0 0x0052 -+#define MT6323_SPK_CON1 0x0054 -+#define MT6323_SPK_CON2 0x0056 -+#define MT6323_SPK_CON6 0x005E -+#define MT6323_SPK_CON7 0x0060 -+#define MT6323_SPK_CON8 0x0062 -+#define MT6323_SPK_CON9 0x0064 -+#define MT6323_SPK_CON10 0x0066 -+#define MT6323_SPK_CON11 0x0068 -+#define MT6323_SPK_CON12 0x006A -+#define MT6323_CID 0x0100 -+#define MT6323_TOP_CKPDN0 0x0102 -+#define MT6323_TOP_CKPDN0_SET 0x0104 -+#define MT6323_TOP_CKPDN0_CLR 0x0106 -+#define MT6323_TOP_CKPDN1 0x0108 -+#define MT6323_TOP_CKPDN1_SET 0x010A -+#define MT6323_TOP_CKPDN1_CLR 0x010C -+#define MT6323_TOP_CKPDN2 0x010E -+#define MT6323_TOP_CKPDN2_SET 0x0110 -+#define MT6323_TOP_CKPDN2_CLR 0x0112 -+#define MT6323_TOP_RST_CON 0x0114 -+#define MT6323_TOP_RST_CON_SET 0x0116 -+#define MT6323_TOP_RST_CON_CLR 0x0118 -+#define MT6323_TOP_RST_MISC 0x011A -+#define MT6323_TOP_RST_MISC_SET 0x011C -+#define MT6323_TOP_RST_MISC_CLR 0x011E -+#define MT6323_TOP_CKCON0 0x0120 -+#define MT6323_TOP_CKCON0_SET 0x0122 -+#define MT6323_TOP_CKCON0_CLR 0x0124 -+#define MT6323_TOP_CKCON1 0x0126 -+#define MT6323_TOP_CKCON1_SET 0x0128 -+#define MT6323_TOP_CKCON1_CLR 0x012A -+#define MT6323_TOP_CKTST0 0x012C -+#define MT6323_TOP_CKTST1 0x012E -+#define MT6323_TOP_CKTST2 0x0130 -+#define MT6323_TEST_OUT 0x0132 -+#define MT6323_TEST_CON0 0x0134 -+#define MT6323_TEST_CON1 0x0136 -+#define MT6323_EN_STATUS0 0x0138 -+#define MT6323_EN_STATUS1 0x013A -+#define MT6323_OCSTATUS0 0x013C -+#define MT6323_OCSTATUS1 0x013E -+#define MT6323_PGSTATUS 0x0140 -+#define MT6323_CHRSTATUS 0x0142 -+#define MT6323_TDSEL_CON 0x0144 -+#define MT6323_RDSEL_CON 0x0146 -+#define MT6323_SMT_CON0 0x0148 -+#define MT6323_SMT_CON1 0x014A -+#define MT6323_SMT_CON2 0x014C -+#define MT6323_SMT_CON3 0x014E -+#define MT6323_SMT_CON4 0x0150 -+#define MT6323_DRV_CON0 0x0152 -+#define MT6323_DRV_CON1 0x0154 -+#define MT6323_DRV_CON2 0x0156 -+#define MT6323_DRV_CON3 0x0158 -+#define MT6323_DRV_CON4 0x015A -+#define MT6323_SIMLS1_CON 0x015C -+#define MT6323_SIMLS2_CON 0x015E -+#define MT6323_INT_CON0 0x0160 -+#define MT6323_INT_CON0_SET 0x0162 -+#define MT6323_INT_CON0_CLR 0x0164 -+#define MT6323_INT_CON1 0x0166 -+#define MT6323_INT_CON1_SET 0x0168 -+#define MT6323_INT_CON1_CLR 0x016A -+#define MT6323_INT_MISC_CON 0x016C -+#define MT6323_INT_MISC_CON_SET 0x016E -+#define MT6323_INT_MISC_CON_CLR 0x0170 -+#define MT6323_INT_STATUS0 0x0172 -+#define MT6323_INT_STATUS1 0x0174 -+#define MT6323_OC_GEAR_0 0x0176 -+#define MT6323_OC_GEAR_1 0x0178 -+#define MT6323_OC_GEAR_2 0x017A -+#define MT6323_OC_CTL_VPROC 0x017C -+#define MT6323_OC_CTL_VSYS 0x017E -+#define MT6323_OC_CTL_VPA 0x0180 -+#define MT6323_FQMTR_CON0 0x0182 -+#define MT6323_FQMTR_CON1 0x0184 -+#define MT6323_FQMTR_CON2 0x0186 -+#define MT6323_RG_SPI_CON 0x0188 -+#define MT6323_DEW_DIO_EN 0x018A -+#define MT6323_DEW_READ_TEST 0x018C -+#define MT6323_DEW_WRITE_TEST 0x018E -+#define MT6323_DEW_CRC_SWRST 0x0190 -+#define MT6323_DEW_CRC_EN 0x0192 -+#define MT6323_DEW_CRC_VAL 0x0194 -+#define MT6323_DEW_DBG_MON_SEL 0x0196 -+#define MT6323_DEW_CIPHER_KEY_SEL 0x0198 -+#define MT6323_DEW_CIPHER_IV_SEL 0x019A -+#define MT6323_DEW_CIPHER_EN 0x019C -+#define MT6323_DEW_CIPHER_RDY 0x019E -+#define MT6323_DEW_CIPHER_MODE 0x01A0 -+#define MT6323_DEW_CIPHER_SWRST 0x01A2 -+#define MT6323_DEW_RDDMY_NO 0x01A4 -+#define MT6323_DEW_RDATA_DLY_SEL 0x01A6 -+#define MT6323_BUCK_CON0 0x0200 -+#define MT6323_BUCK_CON1 0x0202 -+#define MT6323_BUCK_CON2 0x0204 -+#define MT6323_BUCK_CON3 0x0206 -+#define MT6323_BUCK_CON4 0x0208 -+#define MT6323_BUCK_CON5 0x020A -+#define MT6323_VPROC_CON0 0x020C -+#define MT6323_VPROC_CON1 0x020E -+#define MT6323_VPROC_CON2 0x0210 -+#define MT6323_VPROC_CON3 0x0212 -+#define MT6323_VPROC_CON4 0x0214 -+#define MT6323_VPROC_CON5 0x0216 -+#define MT6323_VPROC_CON7 0x021A -+#define MT6323_VPROC_CON8 0x021C -+#define MT6323_VPROC_CON9 0x021E -+#define MT6323_VPROC_CON10 0x0220 -+#define MT6323_VPROC_CON11 0x0222 -+#define MT6323_VPROC_CON12 0x0224 -+#define MT6323_VPROC_CON13 0x0226 -+#define MT6323_VPROC_CON14 0x0228 -+#define MT6323_VPROC_CON15 0x022A -+#define MT6323_VPROC_CON18 0x0230 -+#define MT6323_VSYS_CON0 0x0232 -+#define MT6323_VSYS_CON1 0x0234 -+#define MT6323_VSYS_CON2 0x0236 -+#define MT6323_VSYS_CON3 0x0238 -+#define MT6323_VSYS_CON4 0x023A -+#define MT6323_VSYS_CON5 0x023C -+#define MT6323_VSYS_CON7 0x0240 -+#define MT6323_VSYS_CON8 0x0242 -+#define MT6323_VSYS_CON9 0x0244 -+#define MT6323_VSYS_CON10 0x0246 -+#define MT6323_VSYS_CON11 0x0248 -+#define MT6323_VSYS_CON12 0x024A -+#define MT6323_VSYS_CON13 0x024C -+#define MT6323_VSYS_CON14 0x024E -+#define MT6323_VSYS_CON15 0x0250 -+#define MT6323_VSYS_CON18 0x0256 -+#define MT6323_VPA_CON0 0x0300 -+#define MT6323_VPA_CON1 0x0302 -+#define MT6323_VPA_CON2 0x0304 -+#define MT6323_VPA_CON3 0x0306 -+#define MT6323_VPA_CON4 0x0308 -+#define MT6323_VPA_CON5 0x030A -+#define MT6323_VPA_CON7 0x030E -+#define MT6323_VPA_CON8 0x0310 -+#define MT6323_VPA_CON9 0x0312 -+#define MT6323_VPA_CON10 0x0314 -+#define MT6323_VPA_CON11 0x0316 -+#define MT6323_VPA_CON12 0x0318 -+#define MT6323_VPA_CON14 0x031C -+#define MT6323_VPA_CON16 0x0320 -+#define MT6323_VPA_CON17 0x0322 -+#define MT6323_VPA_CON18 0x0324 -+#define MT6323_VPA_CON19 0x0326 -+#define MT6323_VPA_CON20 0x0328 -+#define MT6323_BUCK_K_CON0 0x032A -+#define MT6323_BUCK_K_CON1 0x032C -+#define MT6323_BUCK_K_CON2 0x032E -+#define MT6323_ISINK0_CON0 0x0330 -+#define MT6323_ISINK0_CON1 0x0332 -+#define MT6323_ISINK0_CON2 0x0334 -+#define MT6323_ISINK0_CON3 0x0336 -+#define MT6323_ISINK1_CON0 0x0338 -+#define MT6323_ISINK1_CON1 0x033A -+#define MT6323_ISINK1_CON2 0x033C -+#define MT6323_ISINK1_CON3 0x033E -+#define MT6323_ISINK2_CON0 0x0340 -+#define MT6323_ISINK2_CON1 0x0342 -+#define MT6323_ISINK2_CON2 0x0344 -+#define MT6323_ISINK2_CON3 0x0346 -+#define MT6323_ISINK3_CON0 0x0348 -+#define MT6323_ISINK3_CON1 0x034A -+#define MT6323_ISINK3_CON2 0x034C -+#define MT6323_ISINK3_CON3 0x034E -+#define MT6323_ISINK_ANA0 0x0350 -+#define MT6323_ISINK_ANA1 0x0352 -+#define MT6323_ISINK_PHASE_DLY 0x0354 -+#define MT6323_ISINK_EN_CTRL 0x0356 -+#define MT6323_ANALDO_CON0 0x0400 -+#define MT6323_ANALDO_CON1 0x0402 -+#define MT6323_ANALDO_CON2 0x0404 -+#define MT6323_ANALDO_CON3 0x0406 -+#define MT6323_ANALDO_CON4 0x0408 -+#define MT6323_ANALDO_CON5 0x040A -+#define MT6323_ANALDO_CON6 0x040C -+#define MT6323_ANALDO_CON7 0x040E -+#define MT6323_ANALDO_CON8 0x0410 -+#define MT6323_ANALDO_CON10 0x0412 -+#define MT6323_ANALDO_CON15 0x0414 -+#define MT6323_ANALDO_CON16 0x0416 -+#define MT6323_ANALDO_CON17 0x0418 -+#define MT6323_ANALDO_CON18 0x041A -+#define MT6323_ANALDO_CON19 0x041C -+#define MT6323_ANALDO_CON20 0x041E -+#define MT6323_ANALDO_CON21 0x0420 -+#define MT6323_DIGLDO_CON0 0x0500 -+#define MT6323_DIGLDO_CON2 0x0502 -+#define MT6323_DIGLDO_CON3 0x0504 -+#define MT6323_DIGLDO_CON5 0x0506 -+#define MT6323_DIGLDO_CON6 0x0508 -+#define MT6323_DIGLDO_CON7 0x050A -+#define MT6323_DIGLDO_CON8 0x050C -+#define MT6323_DIGLDO_CON9 0x050E -+#define MT6323_DIGLDO_CON10 0x0510 -+#define MT6323_DIGLDO_CON11 0x0512 -+#define MT6323_DIGLDO_CON12 0x0514 -+#define MT6323_DIGLDO_CON13 0x0516 -+#define MT6323_DIGLDO_CON14 0x0518 -+#define MT6323_DIGLDO_CON15 0x051A -+#define MT6323_DIGLDO_CON16 0x051C -+#define MT6323_DIGLDO_CON17 0x051E -+#define MT6323_DIGLDO_CON18 0x0520 -+#define MT6323_DIGLDO_CON19 0x0522 -+#define MT6323_DIGLDO_CON20 0x0524 -+#define MT6323_DIGLDO_CON21 0x0526 -+#define MT6323_DIGLDO_CON23 0x0528 -+#define MT6323_DIGLDO_CON24 0x052A -+#define MT6323_DIGLDO_CON26 0x052C -+#define MT6323_DIGLDO_CON27 0x052E -+#define MT6323_DIGLDO_CON28 0x0530 -+#define MT6323_DIGLDO_CON29 0x0532 -+#define MT6323_DIGLDO_CON30 0x0534 -+#define MT6323_DIGLDO_CON31 0x0536 -+#define MT6323_DIGLDO_CON32 0x0538 -+#define MT6323_DIGLDO_CON33 0x053A -+#define MT6323_DIGLDO_CON34 0x053C -+#define MT6323_DIGLDO_CON35 0x053E -+#define MT6323_DIGLDO_CON36 0x0540 -+#define MT6323_DIGLDO_CON39 0x0542 -+#define MT6323_DIGLDO_CON40 0x0544 -+#define MT6323_DIGLDO_CON41 0x0546 -+#define MT6323_DIGLDO_CON42 0x0548 -+#define MT6323_DIGLDO_CON43 0x054A -+#define MT6323_DIGLDO_CON44 0x054C -+#define MT6323_DIGLDO_CON45 0x054E -+#define MT6323_DIGLDO_CON46 0x0550 -+#define MT6323_DIGLDO_CON47 0x0552 -+#define MT6323_DIGLDO_CON48 0x0554 -+#define MT6323_DIGLDO_CON49 0x0556 -+#define MT6323_DIGLDO_CON50 0x0558 -+#define MT6323_DIGLDO_CON51 0x055A -+#define MT6323_DIGLDO_CON52 0x055C -+#define MT6323_DIGLDO_CON53 0x055E -+#define MT6323_DIGLDO_CON54 0x0560 -+#define MT6323_EFUSE_CON0 0x0600 -+#define MT6323_EFUSE_CON1 0x0602 -+#define MT6323_EFUSE_CON2 0x0604 -+#define MT6323_EFUSE_CON3 0x0606 -+#define MT6323_EFUSE_CON4 0x0608 -+#define MT6323_EFUSE_CON5 0x060A -+#define MT6323_EFUSE_CON6 0x060C -+#define MT6323_EFUSE_VAL_0_15 0x060E -+#define MT6323_EFUSE_VAL_16_31 0x0610 -+#define MT6323_EFUSE_VAL_32_47 0x0612 -+#define MT6323_EFUSE_VAL_48_63 0x0614 -+#define MT6323_EFUSE_VAL_64_79 0x0616 -+#define MT6323_EFUSE_VAL_80_95 0x0618 -+#define MT6323_EFUSE_VAL_96_111 0x061A -+#define MT6323_EFUSE_VAL_112_127 0x061C -+#define MT6323_EFUSE_VAL_128_143 0x061E -+#define MT6323_EFUSE_VAL_144_159 0x0620 -+#define MT6323_EFUSE_VAL_160_175 0x0622 -+#define MT6323_EFUSE_VAL_176_191 0x0624 -+#define MT6323_EFUSE_DOUT_0_15 0x0626 -+#define MT6323_EFUSE_DOUT_16_31 0x0628 -+#define MT6323_EFUSE_DOUT_32_47 0x062A -+#define MT6323_EFUSE_DOUT_48_63 0x062C -+#define MT6323_EFUSE_DOUT_64_79 0x062E -+#define MT6323_EFUSE_DOUT_80_95 0x0630 -+#define MT6323_EFUSE_DOUT_96_111 0x0632 -+#define MT6323_EFUSE_DOUT_112_127 0x0634 -+#define MT6323_EFUSE_DOUT_128_143 0x0636 -+#define MT6323_EFUSE_DOUT_144_159 0x0638 -+#define MT6323_EFUSE_DOUT_160_175 0x063A -+#define MT6323_EFUSE_DOUT_176_191 0x063C -+#define MT6323_EFUSE_CON7 0x063E -+#define MT6323_EFUSE_CON8 0x0640 -+#define MT6323_EFUSE_CON9 0x0642 -+#define MT6323_RTC_MIX_CON0 0x0644 -+#define MT6323_RTC_MIX_CON1 0x0646 -+#define MT6323_AUDTOP_CON0 0x0700 -+#define MT6323_AUDTOP_CON1 0x0702 -+#define MT6323_AUDTOP_CON2 0x0704 -+#define MT6323_AUDTOP_CON3 0x0706 -+#define MT6323_AUDTOP_CON4 0x0708 -+#define MT6323_AUDTOP_CON5 0x070A -+#define MT6323_AUDTOP_CON6 0x070C -+#define MT6323_AUDTOP_CON7 0x070E -+#define MT6323_AUDTOP_CON8 0x0710 -+#define MT6323_AUDTOP_CON9 0x0712 -+#define MT6323_AUXADC_ADC0 0x0714 -+#define MT6323_AUXADC_ADC1 0x0716 -+#define MT6323_AUXADC_ADC2 0x0718 -+#define MT6323_AUXADC_ADC3 0x071A -+#define MT6323_AUXADC_ADC4 0x071C -+#define MT6323_AUXADC_ADC5 0x071E -+#define MT6323_AUXADC_ADC6 0x0720 -+#define MT6323_AUXADC_ADC7 0x0722 -+#define MT6323_AUXADC_ADC8 0x0724 -+#define MT6323_AUXADC_ADC9 0x0726 -+#define MT6323_AUXADC_ADC10 0x0728 -+#define MT6323_AUXADC_ADC11 0x072A -+#define MT6323_AUXADC_ADC12 0x072C -+#define MT6323_AUXADC_ADC13 0x072E -+#define MT6323_AUXADC_ADC14 0x0730 -+#define MT6323_AUXADC_ADC15 0x0732 -+#define MT6323_AUXADC_ADC16 0x0734 -+#define MT6323_AUXADC_ADC17 0x0736 -+#define MT6323_AUXADC_ADC18 0x0738 -+#define MT6323_AUXADC_ADC19 0x073A -+#define MT6323_AUXADC_ADC20 0x073C -+#define MT6323_AUXADC_RSV1 0x073E -+#define MT6323_AUXADC_RSV2 0x0740 -+#define MT6323_AUXADC_CON0 0x0742 -+#define MT6323_AUXADC_CON1 0x0744 -+#define MT6323_AUXADC_CON2 0x0746 -+#define MT6323_AUXADC_CON3 0x0748 -+#define MT6323_AUXADC_CON4 0x074A -+#define MT6323_AUXADC_CON5 0x074C -+#define MT6323_AUXADC_CON6 0x074E -+#define MT6323_AUXADC_CON7 0x0750 -+#define MT6323_AUXADC_CON8 0x0752 -+#define MT6323_AUXADC_CON9 0x0754 -+#define MT6323_AUXADC_CON10 0x0756 -+#define MT6323_AUXADC_CON11 0x0758 -+#define MT6323_AUXADC_CON12 0x075A -+#define MT6323_AUXADC_CON13 0x075C -+#define MT6323_AUXADC_CON14 0x075E -+#define MT6323_AUXADC_CON15 0x0760 -+#define MT6323_AUXADC_CON16 0x0762 -+#define MT6323_AUXADC_CON17 0x0764 -+#define MT6323_AUXADC_CON18 0x0766 -+#define MT6323_AUXADC_CON19 0x0768 -+#define MT6323_AUXADC_CON20 0x076A -+#define MT6323_AUXADC_CON21 0x076C -+#define MT6323_AUXADC_CON22 0x076E -+#define MT6323_AUXADC_CON23 0x0770 -+#define MT6323_AUXADC_CON24 0x0772 -+#define MT6323_AUXADC_CON25 0x0774 -+#define MT6323_AUXADC_CON26 0x0776 -+#define MT6323_AUXADC_CON27 0x0778 -+#define MT6323_ACCDET_CON0 0x077A -+#define MT6323_ACCDET_CON1 0x077C -+#define MT6323_ACCDET_CON2 0x077E -+#define MT6323_ACCDET_CON3 0x0780 -+#define MT6323_ACCDET_CON4 0x0782 -+#define MT6323_ACCDET_CON5 0x0784 -+#define MT6323_ACCDET_CON6 0x0786 -+#define MT6323_ACCDET_CON7 0x0788 -+#define MT6323_ACCDET_CON8 0x078A -+#define MT6323_ACCDET_CON9 0x078C -+#define MT6323_ACCDET_CON10 0x078E -+#define MT6323_ACCDET_CON11 0x0790 -+#define MT6323_ACCDET_CON12 0x0792 -+#define MT6323_ACCDET_CON13 0x0794 -+#define MT6323_ACCDET_CON14 0x0796 -+#define MT6323_ACCDET_CON15 0x0798 -+#define MT6323_ACCDET_CON16 0x079A - --#endif /* __MFD_MT6397_REGISTERS_H__ */ -+#endif ---- /dev/null -+++ b/include/linux/regulator/mt6323-regulator.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (c) 2015 MediaTek Inc. -+ * Author: John Crispin <blogic@openwrt.org> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __LINUX_REGULATOR_MT6323_H -+#define __LINUX_REGULATOR_MT6323_H -+ -+enum { -+ MT6323_ID_VPROC = 0, -+ MT6323_ID_VSYS, -+ MT6323_ID_VPA, -+ MT6323_ID_VTCXO, -+ MT6323_ID_VA, -+ MT6323_ID_VCN28, -+ MT6323_ID_VCN33, -+ MT6323_ID_VIO28, -+ MT6323_ID_VUSB, -+ MT6323_ID_VMC, -+ MT6323_ID_VMCH, -+ MT6323_ID_VGP1, -+ MT6323_ID_VGP2, -+ MT6323_ID_RG_MAX, -+}; -+ -+#define MT6323_MAX_REGULATOR MT6323_ID_RG_MAX -+ -+#endif /* __LINUX_REGULATOR_MT6323_H */ |