diff options
Diffstat (limited to 'target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch')
| -rw-r--r-- | target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch b/target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch new file mode 100644 index 0000000000..a57b6c8d06 --- /dev/null +++ b/target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch @@ -0,0 +1,31 @@ +From 67373874e07eb8c54ab27f8fe9998690e50b1e91 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +Date: Thu, 6 Jun 2013 11:21:23 +0200 +Subject: [PATCH 021/203] arm: mvebu: armada-xp-db: ensure PCIe range is + specified + +The ranges DT entry needed by the PCIe controller is defined at the +SoC .dtsi level. However, some boards have a NOR flash, and to support +it, they need to override the SoC-level ranges property to add an +additional range. Since PCIe and NOR support came separately, some +boards were not properly changed to include the PCIe range in their +ranges property at the .dts level. + +This commit fixes those platforms. + +Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +Signed-off-by: Jason Cooper <jason@lakedaemon.net> +--- + arch/arm/boot/dts/armada-xp-db.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/armada-xp-db.dts ++++ b/arch/arm/boot/dts/armada-xp-db.dts +@@ -31,6 +31,7 @@ + + soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ ++ 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ + 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ + + internal-regs { |