diff options
Diffstat (limited to 'target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts')
| -rw-r--r-- | target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts new file mode 100644 index 0000000000..d1d6a534b6 --- /dev/null +++ b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts @@ -0,0 +1,127 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "storylink,sap-g3200u3", "mediatek,mt7621-soc"; + model = "STORYLiNK SAP-G3200U3"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "sap-g3200u3:green:usb"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + + rfkill { + label = "rfkill"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RFKILL>; + }; + }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x1000>; + read-only; + }; + + partition@31000 { + label = "config"; + reg = <0x31000 0xf000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&pcie1 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0000>; + ieee80211-freq-limit = <2400000 2500000>; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe006>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart3", "jtag"; + ralink,function = "gpio"; + }; + }; +}; |