| Commit message (Collapse) | Author | Age | Files | Lines |
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This target has been mostly replaced by ath79 and won't be included
in the upcoming release anymore. Finally put it to rest.
This also removes all references in packages, tools, etc. as well as
the uboot-ar71xx and vsc73x5-ucode packages.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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The QCA955X is affected by a hardware bug which causes link-loss of the
SGMII link between SoC and PHY. This happens on change of link-state or
speed.
It is not really known what causes this bug. It definitely occurs when
using a AR8033 Gigabit Ethernet PHY.
Qualcomm solves this Bug in a similar fashion. We need to apply the fix
on a per-device base via platform-data as performing the fixup work will
break connectivity in case the SGMII interface is connected to a Switch.
This bug was first proposed to be fixed by Sven Eckelmann in 2016.
https://patchwork.ozlabs.org/patch/604782/
Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Signed-off-by: David Bauer <mail@david-bauer.net>
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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With this change, the timestamp variable is only used in ag71xx_check_dma_stuck. Small tx speedup.
Based on a Qualcomm commit. ag->timestamp = jiffies was not replaced with netif_trans_update(dev) because of this quote:
It should be noted that after this series several instances
of netif_trans_update() are useless (if they occur in
.ndo_start_xmit and driver doesn't set LLTX flag -- stack already
did an update).
From: http://lists.openwall.net/netdev/2016/05/03/87
Signed-off-by: Rosen Penev <rosenp@gmail.com>
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Shrink the size of struct ag71xx_buf to 8 bytes, which improves cache
footprint
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Qualcomm claims this improves the D-cache footprint. Origina commit message below:
From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Date: Fri, 7 Jun 2013 10:57:28 -0500
Subject: [ag71xx] cluster/align structs for cache perf
Cluster the frequently used, per-packet structures in ag71xx near
to each other, and cacheline-align them. Some other re-ordering
occurred to move "warmer" structures near the per-packet structures.
Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
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Qualcomm claims this reduces cache misses. Original commit message below:
From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Date: Tue, 11 Jun 2013 12:18:46 -0500
Subject: [ag71xx] reduce NAPI weight
In an attempt to increase our cache warmth, we are decreasing NAPI.
This increases the warmth of the reused SKBs.
Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
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The motivation for this was misguided. It turns out tuning the NAPI weight could be useful for testing purposes. Therefore reverting.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
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NAPI_POLL_WEIGHT was introduced in the kernel for exactly this purpose 5 years ago.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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positives"
This reverts commit 3d58d7f053eae83b59baf5c8b8a58da78653f605.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48694
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48693
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48692
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pointer
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 43588
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(improves performance) (patch from #13072)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 42427
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This improves performance when doing concurrent rx/tx on a single
ethernet MAC, e.g. when routing between VLANs.
Fixes #13072
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 42328
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The currently used bitmask is not correct for all SoCs.
Introduce a new field in struct ag71xx and store the
bitmask in that. Use the current value for now, it will
be adjusted for each SoCs in further patches.
Aslo use the new field directly in the ag71xx_rx_packets
and ag71xx_hard_start_xmit() functions and remove the
ag71xx_desc_pktlen() helper.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39144
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Currently, the AG71XX_RX_PKT_SIZE value limits the received
frame size to 1514/1516 bytes with/without a VLAN header
respectively. However the hardware limit is controlled by
the value the AG71XX_REG_MAC_MFL register which contains
the value of the max_frame_len field.
Compute the RX buffer size from the max_frame_len field
to get rid of the 1514/1516 byte limitation. Also remove
the unused AG71XX_RX_PKT_SIZE definition.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39121
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This allows to change the value dynamically.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39120
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This will allow to use different values for the
different SoCs.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39117
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 37765
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256 entries is a bit excessive, even for gigabit speeds
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 37762
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again in completion
Improves ethernet performance, especially during bridging
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 37761
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deliver a cache-hot skb to the network stack
SVN-Revision: 31934
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stability on AR934x
SVN-Revision: 31925
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Eric Dumazet)
SVN-Revision: 31736
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SVN-Revision: 30405
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