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* remove the brcm-2.4 target, it will no longer be supported in future releases...Felix Fietkau2010-06-2654-19811/+0
* brcm-2.4: fix commit r18413 "128MB ram problem"Hauke Mehrtens2010-04-011-9/+16
* fix serial flash support (#6442)Jo-Philipp Wich2010-01-162-0/+1097
* fix problem with 128MB ram.Hauke Mehrtens2009-11-131-0/+9
* brcm-2.4: rip out all /dev/nvram and nvram setting/committing code from the k...Felix Fietkau2009-04-274-982/+153
* get rid of $Id$ - it has never helped us and it has broken too many patches ;)Felix Fietkau2009-04-1746-46/+0
* final fix for BCM5354 USB cores, hopefullyImre Kaloz2008-09-021-3/+13
* (5/6) bcm57xx: bcm4785 incomplete rebootFelix Fietkau2008-06-151-0/+13
* update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broad...Felix Fietkau2008-01-0651-3930/+8044
* fix pci init for brcm-2.4 with atheros wifi cardsFelix Fietkau2007-09-081-0/+1
* workaround for timer glitch on some boardsMike Baker2007-08-251-0/+11
* convert brcm-2.4 to the new target structureFelix Fietkau2007-05-0449-0/+15424
nt-weight: bold } /* Literal.Number.Integer */ .highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */ .highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */ .highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */ .highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */ .highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */ .highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */ .highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */ .highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */ .highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */ .highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */ .highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */ .highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */ .highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */ .highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */ .highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */ .highlight .vc { color: #336699 } /* Name.Variable.Class */ .highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2020  Marcelina Koƛcielnicka <mwk@0x04.net>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef MEM_H
#define MEM_H

#include "kernel/yosys.h"

YOSYS_NAMESPACE_BEGIN

struct MemRd {
	dict<IdString, Const> attributes;
	Cell *cell;
	bool clk_enable, clk_polarity;
	bool transparent;
	SigSpec clk, en, addr, data;
	MemRd() : cell(nullptr) {}
};

struct MemWr {
	dict<IdString, Const> attributes;
	Cell *cell;
	bool clk_enable, clk_polarity;
	SigSpec clk, en, addr, data;
	MemWr() : cell(nullptr) {}
};

struct MemInit {
	dict<IdString, Const> attributes;
	Cell *cell;
	Const addr;
	Const data;
	MemInit() : cell(nullptr) {}
};

struct Mem {
	Module *module;
	IdString memid;
	dict<IdString, Const> attributes;
	bool packed;
	RTLIL::Memory *mem;
	Cell *cell;
	int width, start_offset, size;
	std::vector<MemInit> inits;
	std::vector<MemRd> rd_ports;
	std::vector<MemWr> wr_ports;

	void remove();
	void emit();
	void remove_wr_port(int idx);
	void remove_rd_port(int idx);
	void clear_inits();
	Const get_init_data() const;
	static std::vector<Mem> get_all_memories(Module *module);
	static std::vector<Mem> get_selected_memories(Module *module);
	Cell *extract_rdff(int idx);
	Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
};

YOSYS_NAMESPACE_END

#endif