| Commit message (Collapse) | Author | Age | Files | Lines |
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This target has not been updated to 5.4 yet, and the only person
trying it (Koen) decided to retreat based on the following reasons:
- The target is not DT-aware at all
- The huge amount of effort required
- The SoC itself reached EoL at Cavium for some time now
- Upstream removed some important parts as it's also slowly getting EoL
over there
- The commercial product that used this will fade out shortly
- The amount of download for this binary suggest that the target is not
that popular
Since nobody has picked up the work since then, and this is the last
remaining 4.19-only target, finally drop it now.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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The cns3xxx interrupt controller uses a single register and as such
the 'mask' reg/functions must be used as opposed to the 'enable'/'disable'
reg/functions.
This fixes an issue that occurs if more than one GPIO on a specific controller
(there is GPIOA and GPIOB each having 32 GPIO's) uses interrupts. When one
would get enabled all others would be disabled prior to this patch.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48334
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Have gpio driver adopt irqdomain support so that there are
non-overlapping allocations of irq numbers mapped to gpio's.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
SVN-Revision: 42844
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 41917
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This makes the PCI bus topology more standard for devices behind a bridge
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 35078
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SVN-Revision: 34101
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