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* treewide: use upstream compatible for RedBoot FIS parserTomasz Maciej Nowak2022-06-241-2/+2
* gemini: only provide squashfs image for storlink-derivatesChristian Lamparter2021-12-041-0/+1
* target: use SPDX license identifiers on MakefilesAdrian Schmutzler2021-02-101-4/+2
* treewide: provide global default for SUPPORTED_DEVICESAdrian Schmutzler2021-01-231-1/+0
* gemini: Add swap partition to DNS-313Linus Walleij2020-07-311-7/+13
* treewide: drop DEVICE_TYPE when used as device variableAdrian Schmutzler2020-06-031-2/+0
* samba36: RemoveRosen Penev2020-05-081-1/+1
* gemini: Refine package listLinus Walleij2020-04-091-3/+4
* gemini: dns313_gen_hdd_img.sh: switch to /bin/shRosen Penev2019-12-311-1/+1
* treewide: replace backticks by $(...) in gen_*_img.sh scriptsAdrian Schmutzler2019-09-291-1/+1
* gemini: image: fix race condition when building copy-kernel.binYousong Zhou2019-09-112-8/+15
* gemini: Enable flash boot on reference design typeLinus Walleij2019-08-171-8/+23
* gemini: Add copy-kernel utility packageLinus Walleij2019-08-173-0/+78
* gemini: split up DEVICE_TITLEMoritz Warning2019-08-021-7/+14
* gemini: Add SL93512r missing ImageInfo fileLinus Walleij2019-07-071-0/+18
* gemini: Fix device name for StorLink SL93512rAdrian Schmutzler2019-07-071-1/+1
* gemini: Add StorLink SL93512r imagesLinus Walleij2019-07-011-7/+17
* gemini: Drop switch kmod and swconfigLinus Walleij2019-07-011-1/+0
* gemini: Support sysupgrade on DIR-685Linus Walleij2019-05-231-1/+3
* gemini: Classify Raidsonic NAS IB-4220-B as a NASChristian Lamparter2019-03-251-0/+1
* gemini: D-Link DNS-313 is a NASChristian Lamparter2019-03-251-0/+1
* gemini: Generate padded kernel+rootfs images for DIR-685Linus Walleij2019-03-131-3/+20
* gemini: Generate harddisk image for DNS-313Linus Walleij2019-02-202-6/+49
* gemini: Name binary "bootpart.tar.gz"Linus Walleij2019-02-141-2/+2
* gemini: dlink-dir-685: fix rt2800-pci package nameChristian Lamparter2019-01-261-1/+1
* gemini: add EOD marker to rootfs imagesMathias Kresin2019-01-261-1/+2
* gemini: fix ITian Square One SQ201 package selectionMathias Kresin2019-01-261-1/+1
* gemini: replace date placeholderMathias Kresin2019-01-261-0/+2
* gemini: drop Teltonika RUT1xx artifactsMathias Kresin2019-01-261-7/+0
* gemini: add wiligear image build codeMathias Kresin2019-01-261-2/+23
* gemini: fix alphabetical orderMathias Kresin2019-01-261-10/+10
* gemini: use dts compatible based image filenamesMathias Kresin2019-01-263-15/+21
* gemini: drop unnecessary image build default variablesMathias Kresin2019-01-261-3/+0
* gemini: drop unnecessary imagesMathias Kresin2019-01-261-4/+1
* gemini: all images are factory imagesMathias Kresin2019-01-261-6/+6
* gemini: follow common pattern for temp dir namingMathias Kresin2019-01-261-8/+10
* gemini: use existing build code where possibleMathias Kresin2019-01-261-2/+2
* gemini: make all tar files more reproducibleMathias Kresin2019-01-261-3/+5
* gemini: build images in temporary directoriesMathias Kresin2019-01-261-11/+13
* gemini: don't hardcode image filenamesMathias Kresin2019-01-261-6/+8
* gemini: fix parallel buildMathias Kresin2019-01-261-0/+1
* gemini: unify and fix ib-nas4220b and sq201 image creationChristian Lamparter2019-01-242-34/+25
* gemini: lazy set IMAGE_NAMEChristian Lamparter2019-01-241-1/+1
* gemini: Fix up image generationLinus Walleij2018-10-201-6/+10
* gemini: Break out USB to packagesLinus Walleij2018-10-201-1/+1
* gemini: Cook SQ201 imagesLinus Walleij2018-06-182-0/+35
* gemini: Add appropriate Wireless kernel modulesLinus Walleij2018-06-181-2/+3
* gemini: Cook a WRGG firmware imageLinus Walleij2018-06-181-2/+10
* gemini: create zImage for DIR-685Linus Walleij2018-05-141-3/+8
* gemini: fix hard disk boot on D-Link devicesRoman Yeryomin2018-05-051-7/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-30 19:43:02 +0000
">#define MSR_P4_CCCR0 0x360 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25) #define P4_ESCR_OS0 (1<<3) #define P4_ESCR_USR0 (1<<2) #define P4_ESCR_OS1 (1<<1) #define P4_ESCR_USR1 (1<<0) #define P4_CCCR_OVF_PMI0 (1<<26) #define P4_CCCR_OVF_PMI1 (1<<27) #define P4_CCCR_THRESHOLD(N) ((N)<<20) #define P4_CCCR_COMPLEMENT (1<<19) #define P4_CCCR_COMPARE (1<<18) #define P4_CCCR_REQUIRED (3<<16) #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) #define P4_CCCR_ENABLE (1<<12) /* * Set up IQ_COUNTER{0,1} to behave like a clock, by having IQ_CCCR{0,1} filter * CRU_ESCR0 (with any non-null event selector) through a complemented * max threshold. [IA32-Vol3, Section 14.9.9] */ #define MSR_P4_IQ_COUNTER0 0x30C #define MSR_P4_IQ_COUNTER1 0x30D #define MSR_P4_IQ_CCCR0 0x36C #define MSR_P4_IQ_CCCR1 0x36D #define MSR_P4_CRU_ESCR0 0x3B8 /* ESCR no. 4 */ #define P4_NMI_CRU_ESCR0 \ (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS0|P4_ESCR_USR0| \ P4_ESCR_OS1|P4_ESCR_USR1) #define P4_NMI_IQ_CCCR0 \ (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) #define P4_NMI_IQ_CCCR1 \ (P4_CCCR_OVF_PMI1|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) int __init check_nmi_watchdog (void) { unsigned int prev_nmi_count[NR_CPUS]; int j, cpu; if ( !nmi_watchdog ) return 0; printk("Testing NMI watchdog --- "); for ( j = 0; j < smp_num_cpus; j++ ) { cpu = cpu_logical_map(j); prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count; } __sti(); mdelay((10*1000)/nmi_hz); /* wait 10 ticks */ for ( j = 0; j < smp_num_cpus; j++ ) { cpu = cpu_logical_map(j); if ( nmi_count(cpu) - prev_nmi_count[cpu] <= 5 ) printk("CPU#%d stuck. ", cpu); else printk("CPU#%d okay. ", cpu); } printk("\n"); /* now that we know it works we can reduce NMI frequency to something more reasonable; makes a difference in some configs */ if ( nmi_watchdog == NMI_LOCAL_APIC ) nmi_hz = 1; return 0; } static inline void nmi_pm_init(void) { } #define __pminit __init /* * Activate the NMI watchdog via the local APIC. * Original code written by Keith Owens. */ static void __pminit clear_msr_range(unsigned int base, unsigned int n) { unsigned int i; for ( i = 0; i < n; i++ ) wrmsr(base+i, 0, 0); } static void __pminit setup_k7_watchdog(void) { unsigned int evntsel; nmi_perfctr_msr = MSR_K7_PERFCTR0; clear_msr_range(MSR_K7_EVNTSEL0, 4); clear_msr_range(MSR_K7_PERFCTR0, 4); evntsel = K7_EVNTSEL_INT | K7_EVNTSEL_OS | K7_EVNTSEL_USR | K7_NMI_EVENT; wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000)); wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |= K7_EVNTSEL_ENABLE; wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); } static void __pminit setup_p6_watchdog(void) { unsigned int evntsel; nmi_perfctr_msr = MSR_P6_PERFCTR0; clear_msr_range(MSR_P6_EVNTSEL0, 2); clear_msr_range(MSR_P6_PERFCTR0, 2); evntsel = P6_EVNTSEL_INT | P6_EVNTSEL_OS | P6_EVNTSEL_USR | P6_NMI_EVENT; wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000)); wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0); apic_write(APIC_LVTPC, APIC_DM_NMI); evntsel |= P6_EVNTSEL0_ENABLE; wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); } static int __pminit setup_p4_watchdog(void) { unsigned int misc_enable, dummy; rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy); if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL)) return 0; nmi_perfctr_msr = MSR_P4_IQ_COUNTER0; if ( logical_proc_id[smp_processor_id()] == 0 ) { if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL)) clear_msr_range(0x3F1, 2); /* MSR 0x3F0 seems to have a default value of 0xFC00, but current docs doesn't fully define it, so leave it alone for now. */ clear_msr_range(0x3A0, 31); clear_msr_range(0x3C0, 6); clear_msr_range(0x3C8, 6); clear_msr_range(0x3E0, 2); clear_msr_range(MSR_P4_CCCR0, 18); clear_msr_range(MSR_P4_PERFCTR0, 18); wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); apic_write(APIC_LVTPC, APIC_DM_NMI); wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0); } else if ( logical_proc_id[smp_processor_id()] == 1 ) { wrmsr(MSR_P4_IQ_CCCR1, P4_NMI_IQ_CCCR1 & ~P4_CCCR_ENABLE, 0); Dprintk("setting P4_IQ_COUNTER2 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); wrmsr(MSR_P4_IQ_COUNTER1, -(cpu_khz/nmi_hz*1000), -1); apic_write(APIC_LVTPC, APIC_DM_NMI); wrmsr(MSR_P4_IQ_CCCR1, P4_NMI_IQ_CCCR1, 0); } else { return 0; } return 1; } void __pminit setup_apic_nmi_watchdog(void) { if (!nmi_watchdog) return; switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15) return; setup_k7_watchdog(); break; case X86_VENDOR_INTEL: switch (boot_cpu_data.x86) { case 6: setup_p6_watchdog(); break; case 15: if (!setup_p4_watchdog()) return; break; default: return; } break; default: return; } nmi_pm_init(); } static unsigned int last_irq_sums [NR_CPUS], alert_counter [NR_CPUS]; void touch_nmi_watchdog (void) { int i; for (i = 0; i < smp_num_cpus; i++) alert_counter[i] = 0; } void nmi_watchdog_tick (struct pt_regs * regs) { extern void die(const char * str, struct pt_regs * regs, long err); int sum, cpu = smp_processor_id(); sum = apic_timer_irqs[cpu]; if ( (last_irq_sums[cpu] == sum) && watchdog_on ) { /* * Ayiee, looks like this CPU is stuck ... wait a few IRQs (5 seconds) * before doing the oops ... */ alert_counter[cpu]++; if ( alert_counter[cpu] == 5*nmi_hz ) { console_force_unlock(); die("NMI Watchdog detected LOCKUP on CPU", regs, cpu); } } else { last_irq_sums[cpu] = sum; alert_counter[cpu] = 0; } if ( nmi_perfctr_msr ) { if ( nmi_perfctr_msr == MSR_P4_IQ_COUNTER0 ) { if ( logical_proc_id[cpu] == 0 ) { wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0); apic_write(APIC_LVTPC, APIC_DM_NMI); wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); } else { wrmsr(MSR_P4_IQ_CCCR1, P4_NMI_IQ_CCCR1, 0); apic_write(APIC_LVTPC, APIC_DM_NMI); wrmsr(MSR_P4_IQ_COUNTER1, -(cpu_khz/nmi_hz*1000), -1); } } else { wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1); } } }
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-30 19:43:01 +0000