Makefile « src « 6rd « ipv6 « network « package - openwrt/upstream - upstream openwrt

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path: root/package/network/ipv6/6rd/src/Makefile

blob: 2881d435890ddc23027fc6e1df281cf0e038c267 (plain)

all: 6rdcalc

6rdcalc: 6rdcalc.c
	$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $<

clean:
	rm -f 6rdcalc

200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */ .highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */ .highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */ .highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */ .highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */ .highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */ .highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */ .highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */ .highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */ .highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */ .highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */ .highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */ .highlight .vc { color: #336699 } /* Name.Variable.Class */ .highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */

entity tb_ram2 is
end tb_ram2;

library ieee;
use ieee.std_logic_1164.all;

architecture behav of tb_ram2 is
  signal clkA : std_logic;
  signal enA : std_logic;
  signal weA : std_logic;
  signal addrA : std_logic_vector(5 downto 0);
  signal rdatA : std_logic_vector(31 downto 0);
  signal wdatA : std_logic_vector(31 downto 0);
  
  signal clkB : std_logic;
  signal enB : std_logic;
  signal weB : std_logic;
  signal addrB : std_logic_vector(5 downto 0);
  signal rdatB : std_logic_vector(31 downto 0);
  signal wdatB : std_logic_vector(31 downto 0);
begin
  dut: entity work.ram2
    port map (clkA => clkA, clkB => clkB,
              enA => enA, enB => enB,
              weA => weA, weB => weB,
              addrA => addrA, addrB => addrB,
              diA => wdatA, diB => wdatB,
              doA => rdatA, doB => rdatB);

  process
    procedure pulseB is
    begin
      clkB <= '0';
      wait for 1 ns;
      clkB <= '1';
      wait for 1 ns;
    end pulseB;
    procedure pulseA is
    begin
      clkA <= '0';
      wait for 1 ns;
      clkA <= '1';
      wait for 1 ns;
    end pulseA;
  begin
    clkA <= '0';
    enA <= '0';

    enB <= '1';
    weB <= '1';
    addrB <= b"00_0000";
    wdatB <= x"11_22_33_f0";
    pulseB;
    assert rdatB = x"11_22_33_f0" severity failure;

    addrB <= b"00_0001";
    wdatB <= x"11_22_33_f1";
    pulseB;
    assert rdatB = x"11_22_33_f1" severity failure;

    --  Read.
    weB <= '0';
    addrB <= b"00_0000";
    wdatB <= x"ff_22_33_f1";
    pulseB;
    assert rdatB = x"11_22_33_f0" severity failure;

    addrB <= b"00_0001";
    wdatB <= x"ff_22_33_f1";
    pulseB;
    assert rdatB = x"11_22_33_f1" severity failure;

    --  Disable.
    enB <= '0';
    weB <= '1';
    addrB <= b"00_0000";
    wdatB <= x"11_22_33_f0";
    pulseB;
    assert rdatB = x"11_22_33_f1" severity failure;

    --  Read from A.
    enA <= '1';
    weA <= '0';
    addrA <= b"00_0001";
    wdatA <= x"88_22_33_f1";
    pulseA;
    assert rdatA = x"11_22_33_f1" severity failure;
    
    wait;
  end process;
end behav;