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From 5ebee96094c5a97a89a986108242cca9d853ff55 Mon Sep 17 00:00:00 2001
From: Roy Pledge <roy.pledge@nxp.com>
Date: Wed, 27 Sep 2017 14:50:08 -0400
Subject: [PATCH] staging/fsl_qbman: Calculate valid bit from MC-RR
Use the management commmand response registers to determine
the next expected valid bit when initializing a software
portal. This avoids using the wrong valid bit in cases
where a command was partially written but then not
completed.
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
---
drivers/staging/fsl_qbman/qman_low.h | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
--- a/drivers/staging/fsl_qbman/qman_low.h
+++ b/drivers/staging/fsl_qbman/qman_low.h
@@ -1095,11 +1095,26 @@ static inline void qm_mr_set_ithresh(str
static inline int qm_mc_init(struct qm_portal *portal)
{
+ u8 rr0, rr1;
register struct qm_mc *mc = &portal->mc;
+
mc->cr = portal->addr.addr_ce + QM_CL_CR;
mc->rr = portal->addr.addr_ce + QM_CL_RR0;
- mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &
- QM_MCC_VERB_VBIT) ? 0 : 1;
+
+ /*
+ * The expected valid bit polarity for the next CR command is 0
+ * if RR1 contains a valid response, and is 1 if RR0 contains a
+ * valid response. If both RR contain all 0, this indicates either
+ * that no command has been executed since reset (in which case the
+ * expected valid bit polarity is 1)
+ */
+ rr0 = __raw_readb(&mc->rr->verb);
+ rr1 = __raw_readb(&(mc->rr+1)->verb);
+ if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
+ mc->rridx = 1;
+ else
+ mc->rridx = 0;
+
mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
#ifdef CONFIG_FSL_DPA_CHECKING
mc->state = qman_mc_idle;
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