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author | root <root@lab.ourano.james.local> | 2021-02-25 19:12:38 +0000 |
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committer | root <root@lab.ourano.james.local> | 2021-02-25 19:12:38 +0000 |
commit | 6d3a824e1cdae6e28146b7de380724b49488f3c2 (patch) | |
tree | b8865608c9749e4251b316b74484b5151f2e683b /app/main.c | |
parent | 0548136a4c886830414fb575d9d0daa7f1a7d170 (diff) | |
download | clock-6d3a824e1cdae6e28146b7de380724b49488f3c2.tar.gz clock-6d3a824e1cdae6e28146b7de380724b49488f3c2.tar.bz2 clock-6d3a824e1cdae6e28146b7de380724b49488f3c2.zip |
tim
Diffstat (limited to 'app/main.c')
-rw-r--r-- | app/main.c | 92 |
1 files changed, 27 insertions, 65 deletions
@@ -138,6 +138,7 @@ static const clock_scale_t hse_10mhz_3v3_168 = { .apb2_frequency = 84000000, }; + #if 0 static const clock_scale_t hse_10mhz_3v3_120 = { /* 120 */ @@ -202,69 +203,6 @@ static const clock_scale_t hse_10mhz_3v3_10 = { #endif -/* - * Erugh the STM32F4's PLL is shite, we need - * to drive the entire clock tree from the 10MHz - * input, we use the PLL only to drive the 48MHz - * clock tree. - * - * So PTP, AHB, APB1, APB2 all are directly from - * the HSE input - */ - - -void rcc_clock_setup_hse_3v3_no_pll (const clock_scale_t *clock) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on (HSI); - rcc_wait_for_osc_ready (HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source (RCC_CFGR_SW_HSI); - - /* receive the 10MHz external oscillator */ - rcc_osc_bypass_enable (HSE); - rcc_osc_on (HSE); - rcc_wait_for_osc_ready (HSE); - - /* Enable/disable high performance mode */ - if (!clock->power_save) - pwr_set_vos_scale (SCALE1); - else - pwr_set_vos_scale (SCALE2); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre (clock->hpre); - rcc_set_ppre1 (clock->ppre1); - rcc_set_ppre2 (clock->ppre2); - - rcc_set_main_pll_hse (clock->pllm, clock->plln, - clock->pllp, clock->pllq); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on (PLL); - rcc_wait_for_osc_ready (PLL); - - /* Configure flash settings. */ - flash_set_ws (clock->flash_config); - - /* Select HSE as SYSCLK source. */ - rcc_set_sysclk_source (RCC_CFGR_SW_HSE); - - /* Wait for HSE clock to be selected. */ - rcc_wait_for_sysclk_status (HSE); - - /* Set the peripheral clock frequencies used. */ - rcc_apb1_frequency = clock->apb1_frequency; - rcc_apb2_frequency = clock->apb2_frequency; - - /* Disable internal high-speed oscillator. */ - rcc_osc_off (HSI); -} - static void ptp_clock_start (void) { /* Get the PTP clock running early */ @@ -283,6 +221,7 @@ static void ptp_clock_start (void) static void clock_setup (void) { +static uint32_t fail; /* * Caution, The PLL is somewhat rubbish, and causes all sorts of misery * so sysclk isn't really a reference, if we use it, however not using it @@ -292,8 +231,26 @@ static void clock_setup (void) * */ + /*Get us up and running on the 16MHz RC clock */ + rcc_osc_on (HSI); + rcc_wait_for_osc_ready (HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source (RCC_CFGR_SW_HSI); + + /* confiure HSE as input not oscillator */ - rcc_osc_bypass_enable (HSE); + rcc_osc_bypass_enable (HSE); + rcc_osc_on (HSE); + + while ((RCC_CR & RCC_CR_HSERDY) == 0) { + if (fail++ == 4000000) { + /*No external clock, try seeing if we have a crystal */ + rcc_osc_off (HSE); + rcc_osc_bypass_disable (HSE); + rcc_osc_on (HSE); + } + } /* turn off SSC */ RCC_SSCGR = 0; @@ -406,6 +363,7 @@ board_setup (void) rcc_periph_clock_enable (RCC_ETHMACPTP); rcc_periph_clock_enable (RCC_TIM1); rcc_periph_clock_enable (RCC_TIM2); + rcc_periph_clock_enable (RCC_OTGFS); nvic_set_priority (NVIC_EXTI9_5_IRQ, 0x00); nvic_set_priority (NVIC_EXTI3_IRQ, 0x10); @@ -420,6 +378,7 @@ board_setup (void) } + static void system_init (void) { @@ -443,11 +402,13 @@ system_init (void) ptp_clock_start(); - max7219_init (1); + max7219_init (1, 8); gps_init(); ntp_init(); + usb_init(); + } int @@ -495,6 +456,7 @@ main (void) dispatch_lwip(); max7219_dispatch(); + cdcacm_dispatch(); } |