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author | fishsoupisgood <github@madingley.org> | 2019-02-20 02:39:38 +0000 |
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committer | fishsoupisgood <github@madingley.org> | 2019-02-20 02:39:38 +0000 |
commit | c93861c733ced9c6659241cea69c7feed56afcce (patch) | |
tree | edcef2f980ae99f8ff8746c585eaf611c940e9ef /app/main.c | |
parent | 971cc458aea21832a20b1b087185659d8e9ec2b3 (diff) | |
download | clock-c93861c733ced9c6659241cea69c7feed56afcce.tar.gz clock-c93861c733ced9c6659241cea69c7feed56afcce.tar.bz2 clock-c93861c733ced9c6659241cea69c7feed56afcce.zip |
use OCXO, and auto fail-over between different clock sources
Diffstat (limited to 'app/main.c')
-rw-r--r-- | app/main.c | 19 |
1 files changed, 18 insertions, 1 deletions
@@ -28,11 +28,28 @@ static void cmd_dispatch() } } +static const clock_scale_t hse_10mhz_3v3_168 = { + /* 168MHz */ + .pllm = 10, + .plln = 336, + .pllp = 2, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_5WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, +}; + + static void board_setup (void) { - rcc_clock_setup_hse_3v3 (&hse_8mhz_3v3[CLOCK_3V3_168MHZ]); + rcc_osc_bypass_enable (HSE); + rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168); rcc_periph_clock_enable (RCC_SYSCFG); rcc_periph_clock_enable (RCC_GPIOA); |