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author | fishsoupisgood <github@madingley.org> | 2019-04-29 01:17:54 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2019-05-27 03:43:43 +0100 |
commit | 3f2546b2ef55b661fd8dd69682b38992225e86f6 (patch) | |
tree | 65ca85f13617aee1dce474596800950f266a456c /tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c | |
download | qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.tar.gz qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.tar.bz2 qemu-3f2546b2ef55b661fd8dd69682b38992225e86f6.zip |
Diffstat (limited to 'tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c')
-rw-r--r-- | tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c b/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c new file mode 100644 index 00000000..02548f85 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long achi, acli; + long long acho, aclo; + long long resl, resh; + + achi = 0x4; + acli = 0x4; + + rs = 0x1234567887654321; + rt = 0x8765432112345678; + + resh = 0x4; + resl = 0x4; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "mulsaq_s.l.pw $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 mulsaq_s.l.pw wrong\n"); + + return -1; + } + + achi = 0x4; + acli = 0x4; + + rs = 0x8000000087654321; + rt = 0x8000000012345678; + + resh = 0x4; + resl = 0x1e8ee513; + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "mulsaq_s.l.pw $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (acho != resh) || (aclo != resl)) { + printf("2 mulsaq_s.l.pw wrong\n"); + + return -1; + } + return 0; +} |