168 files changed, 108416 insertions, 0 deletions

diff --git a/roms/u-boot/board/esd/apc405/Makefile b/roms/u-boot/board/esd/apc405/Makefile
new file mode 100644
index 00000000..ada8bfd3
--- /dev/null
+++ b/roms/u-boot/board/esd/apc405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= apc405.o \
+	../common/misc.o \
+	../common/auto_update.o
diff --git a/roms/u-boot/board/esd/apc405/apc405.c b/roms/u-boot/board/esd/apc405/apc405.c
new file mode 100644
index 00000000..5cc1d0d9
--- /dev/null
+++ b/roms/u-boot/board/esd/apc405/apc405.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+#include <asm/4xx_pci.h>
+#include <pci.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef FPGA_DEBUG
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#ifdef CONFIG_LCD_USED
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+#include "../common/s1d13505_640_480_16bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#endif /* CONFIG_LCD_USED */
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"preinst.img", 0, -1, AU_SCRIPT},
+	{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
+	{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
+	{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
+	{"work.img", 0xfe500000, 0x01400000, AU_NOR},
+	{"data.img", 0xff900000, 0x00580000, AU_NOR},
+	{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
+	{"postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+int board_revision(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
+
+	/* wait some time before reading input */
+	udelay(1000);
+
+	/* get config bits */
+	value = in_be32((void*)GPIO0_IR) & 0x001c0000;
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x001c0000:
+		/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
+		return 2;
+	case 0x000c0000:
+		/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
+		return 3;
+	case 0x00180000:
+		/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
+		return 6;
+	case 0x00140000:
+		/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
+		return 8;
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+int board_early_init_f (void)
+{
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic
+	 */
+	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
+	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * New boards have a single 32MB flash connected to CS0
+	 * instead of two 16MB flashes on CS0+1.
+	 */
+	if (board_revision() >= 8) {
+		/* disable CS1 */
+		mtebc(PB1AP, 0);
+		mtebc(PB1CR, 0);
+
+		/* resize CS0 to 32MB */
+		mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+		mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	if (gd->board_type >= 8)
+		cfi_flash_num_flash_banks = 1;
+
+	return 0;
+}
+
+#define FUJI_BASE    0xf0100200
+#define LCDBL_PWM    0xa0
+#define LCDBL_PWMMIN 0xa4
+#define LCDBL_PWMMAX 0xa8
+
+int misc_init_r(void)
+{
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
+	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
+	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long CPC0_CR0Reg;
+	char *str;
+	uchar *logo_addr;
+	ulong logo_size;
+	ushort minb, maxb;
+	int result;
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: "
+			       "INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: "
+			       "INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: "
+			       "DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len + 3;
+		}
+		putc('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index = 0; index < 1000; index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	/* restore gpio/cs settings */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index + 1]));
+		index += len + 3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write board revision in FPGA
+	 */
+	out_be16(fpga_ctrl2,
+		 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+	for (i=0;i<100;i++)
+		udelay(1000);
+	udelay(1000);
+	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8(duart0_mcr, 0x08);
+	out_8(duart1_mcr, 0x08);
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	str = getenv("splashimage");
+	if (str) {
+		logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
+		logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+	} else {
+		logo_addr = logo_bmp;
+		logo_size = sizeof(logo_bmp);
+	}
+
+	if (gd->board_type >= 6) {
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				  regs_13505_640_480_16bpp,
+				  sizeof(regs_13505_640_480_16bpp) /
+				  sizeof(regs_13505_640_480_16bpp[0]),
+				  logo_addr, logo_size);
+		if (result && str) {
+			/* retry with internal image */
+			logo_addr = logo_bmp;
+			logo_size = sizeof(logo_bmp);
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				 regs_13505_640_480_16bpp,
+				 sizeof(regs_13505_640_480_16bpp) /
+				 sizeof(regs_13505_640_480_16bpp[0]),
+				 logo_addr, logo_size);
+		}
+	} else {
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				  regs_13806_640_480_16bpp,
+				  sizeof(regs_13806_640_480_16bpp) /
+				  sizeof(regs_13806_640_480_16bpp[0]),
+				  logo_addr, logo_size);
+		if (result && str) {
+			/* retry with internal image */
+			logo_addr = logo_bmp;
+			logo_size = sizeof(logo_bmp);
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+				 regs_13806_640_480_16bpp,
+				 sizeof(regs_13806_640_480_16bpp) /
+				 sizeof(regs_13806_640_480_16bpp[0]),
+				 logo_addr, logo_size);
+		}
+	}
+
+	/*
+	 * Reset microcontroller and setup backlight PWM controller
+	 */
+	out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
+	for (i=0;i<10;i++)
+		udelay(1000);
+	out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
+
+	minb = 0;
+	maxb = 0xff;
+	str = getenv("lcdbl");
+	if (str) {
+		minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
+		if (str && (*str=',')) {
+			str++;
+			maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
+		} else
+			minb = 0;
+
+		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
+		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
+
+		printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
+	}
+	out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
+
+	/*
+	 * fix environment for field updated units
+	 */
+	if (getenv("altbootcmd") == NULL) {
+		setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+		setenv("usbargs", CONFIG_SYS_USB_ARGS);
+		setenv("bootcmd", CONFIG_BOOTCOMMAND);
+		setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+		setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+		setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
+		saveenv();
+	}
+
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming APC405");
+	} else {
+		puts(str);
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev. 1.%ld\n", gd->board_type);
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {
+		out_be16(fpga_mode,
+			 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {
+		out_be16(fpga_mode,
+			 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	unsigned short tmp;
+	int i;
+
+	/*
+	 * reset PCI bus
+	 * This is required to make some very old Linux OHCI driver
+	 * work after U-Boot has used the OHCI controller.
+	 */
+	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
+	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
+
+	for (i = 0; i < 100; i++)
+		udelay(1000);
+
+	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return usb_board_stop();
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/roms/u-boot/board/esd/apc405/fpgadata.c b/roms/u-boot/board/esd/apc405/fpgadata.c
new file mode 100644
index 00000000..b68668c1
--- /dev/null
+++ b/roms/u-boot/board/esd/apc405/fpgadata.c
@@ -0,0 +1,4008 @@
+0x1f, 0x8b, 0x08, 0x08, 0x49, 0xe1, 0xdb, 0x46,
+0x00, 0x03, 0x61, 0x62, 0x67, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x14, 0xd7,
+0x75, 0x3f, 0x8e, 0x9f, 0xb9, 0x33, 0x12, 0xa3,
+0xdd, 0x95, 0x76, 0xf4, 0xe4, 0xac, 0x6d, 0x20,
+0xa3, 0x95, 0x20, 0x6b, 0xb2, 0x88, 0x45, 0x60,
+0x8c, 0xb1, 0x90, 0x06, 0x49, 0x26, 0x8a, 0x4d,
+0x8c, 0x4c, 0xdd, 0x84, 0xf6, 0x9b, 0xa6, 0x6b,
+0x42, 0x53, 0xda, 0x17, 0x49, 0x65, 0x27, 0x9f,
+0x96, 0xe6, 0x93, 0x26, 0x57, 0x2b, 0x81, 0x85,
+0x21, 0xf6, 0x1a, 0x93, 0x46, 0x4e, 0x69, 0xba,
+0x60, 0xea, 0xc8, 0x09, 0x4d, 0x96, 0x07, 0x9b,
+0x07, 0x53, 0x3c, 0xc2, 0x32, 0x11, 0x18, 0xdb,
+0x0a, 0x71, 0x53, 0xf9, 0x21, 0xf6, 0x9a, 0xc8,
+0x44, 0xb6, 0x89, 0x23, 0xdb, 0xc4, 0x11, 0xcf,
+0xdf, 0x73, 0xee, 0xec, 0x3c, 0xec, 0x4a, 0x24,
+0xe9, 0xe7, 0xf3, 0xf3, 0xef, 0xf7, 0xc7, 0x2f,
+0x9b, 0x3f, 0x72, 0x3c, 0x7b, 0x35, 0xcc, 0x3d,
+0x7b, 0xe7, 0xdc, 0xf7, 0x3d, 0xe7, 0x7d, 0xce,
+0x81, 0xa2, 0xe0, 0xa8, 0xf5, 0x3f, 0x00, 0xe9,
+0x4e, 0xd0, 0xee, 0x5c, 0xf1, 0xd7, 0x73, 0x63,
+0xd7, 0xff, 0xe5, 0xec, 0xbf, 0x8c, 0xcd, 0xa9,
+0xfd, 0xd2, 0xe7, 0x57, 0xc2, 0x0a, 0xf0, 0xd5,
+0x7d, 0xf9, 0xfa, 0xd8, 0x17, 0xfe, 0xba, 0xee,
+0xfa, 0x79, 0xf0, 0x79, 0xf0, 0xd7, 0xc5, 0x62,
+0x37, 0xcc, 0xd2, 0x6f, 0x9c, 0xa5, 0xcf, 0x81,
+0x95, 0x50, 0x34, 0xbb, 0x6e, 0x41, 0x5d, 0xdd,
+0x82, 0x39, 0xd7, 0xc3, 0x5f, 0x81, 0x54, 0x1a,
+0xb8, 0x8c, 0x9f, 0xef, 0x3f, 0xf4, 0xa7, 0x5f,
+0x88, 0x01, 0x97, 0x00, 0x60, 0x52, 0x4c, 0x8a,
+0xd3, 0xff, 0xfb, 0x63, 0x92, 0x2e, 0x01, 0x6f,
+0x9c, 0x19, 0x03, 0x93, 0xfe, 0x1b, 0xb2, 0xdf,
+0x17, 0xc5, 0x40, 0xf7, 0xfe, 0xb7, 0x14, 0x03,
+0x03, 0xda, 0xa0, 0x41, 0x81, 0x32, 0xf8, 0xfd,
+0x1f, 0x09, 0x14, 0x6e, 0xcb, 0xff, 0xd3, 0xf1,
+0xec, 0x0f, 0x18, 0x8f, 0x9f, 0xff, 0xe3, 0xf1,
+0x7f, 0xc8, 0xf3, 0x00, 0x28, 0xff, 0xc7, 0xe3,
+0xb5, 0x3f, 0x6c, 0xbc, 0x2d, 0x5c, 0xd6, 0xa0,
+0x02, 0x0a, 0x40, 0x22, 0xed, 0x0a, 0x01, 0x50,
+0xd1, 0x1a, 0x7e, 0xef, 0x5e, 0x41, 0xa1, 0xb1,
+0xdf, 0xbe, 0xbf, 0x59, 0x70, 0x09, 0x2e, 0xf3,
+0xeb, 0xe3, 0xc5, 0x63, 0xf2, 0x57, 0xe0, 0x35,
+0xde, 0x98, 0x09, 0x8e, 0xc9, 0x74, 0x65, 0x61,
+0xa6, 0xe4, 0x8c, 0x3c, 0x07, 0x2e, 0xeb, 0x8d,
+0x03, 0xb7, 0x9e, 0xa9, 0x8e, 0x49, 0xed, 0xd9,
+0xf1, 0x5c, 0x7b, 0x07, 0x9e, 0xe0, 0x61, 0x43,
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diff --git a/roms/u-boot/board/esd/apc405/logo_640_480_24bpp.c b/roms/u-boot/board/esd/apc405/logo_640_480_24bpp.c
new file mode 100644
index 00000000..a2180323
--- /dev/null
+++ b/roms/u-boot/board/esd/apc405/logo_640_480_24bpp.c
@@ -0,0 +1,1129 @@
+0x1f, 0x8b, 0x08, 0x08, 0x30, 0x72, 0x03, 0x48,
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+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x4f, 0xc5,
+0xff, 0x02, 0x04, 0xc4, 0x15, 0x0c, 0x36, 0xb4,
+0x04, 0x00,
diff --git a/roms/u-boot/board/esd/ar405/Makefile b/roms/u-boot/board/esd/ar405/Makefile
new file mode 100644
index 00000000..dd54f546
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ar405.o flash.o ../common/misc.o
diff --git a/roms/u-boot/board/esd/ar405/ar405.c b/roms/u-boot/board/esd/ar405/ar405.c
new file mode 100644
index 00000000..d33aba47
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/ar405.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "ar405.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	/* first try 40er image */
+	gd->board_type = 40;
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* try xl30er image */
+		gd->board_type = 30;
+		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f ();
+#endif
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf ("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay (1000);
+			}
+			putc ('\n');
+			do_reset (NULL, 0, 0, NULL);
+		}
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+	const unsigned char *fpga;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	if (gd->board_type == 30) {
+		fpga = fpgadata_xl30;
+	} else {
+		fpga = fpgadata;
+	}
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpga[index];
+		printf ("%s ", &(fpga[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+#if 1 /* test-only: some internal test routines... */
+#define DIGEN	((void *)0xf03000b4) /* u8 */
+#define DIGOUT	((void *)0xf03000b0) /* u16 */
+#define DIGIN	((void *)0xf03000a0) /* u16 */
+
+/*
+ * Some test routines
+ */
+int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	int k;
+	int start;
+	int end;
+
+	if (argc != 3) {
+		puts("Usage: digtest n_start n_end (digtest 0 7)\n");
+		return 0;
+	}
+
+	start = simple_strtol (argv[1], NULL, 10);
+	end = simple_strtol (argv[2], NULL, 10);
+
+	/*
+	 * Enable digital outputs
+	 */
+	out_8(DIGEN, 0x08);
+
+	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
+	       start, end);
+
+	/*
+	 * Set outputs one by one
+	 */
+	for (;;) {
+		for (i=start; i<=end; i++) {
+			out_be16(DIGOUT, 0x0001 << i);
+			for (k=0; k<200; k++)
+				udelay(1000);
+
+			if (in_be16(DIGIN) != (0x0001 << i)) {
+				printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
+				       0x0001 << i, in_be16(DIGIN));
+				return 0;
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	digtest,	3,	1,	do_digtest,
+	"Test digital in-/output",
+	""
+);
+
+#define ERROR_DELTA     256
+
+struct io {
+	short val;
+	short dummy;
+};
+
+int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	short val;
+	int i;
+	int volt;
+	struct io *out;
+	struct io *in;
+
+	out = (struct io *)0xf0300090;
+	in = (struct io *)0xf0300000;
+
+	i = simple_strtol (argv[1], NULL, 10);
+
+	volt = 0;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 5;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 10;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+	udelay(10000);
+	val = in_be16((void *)&(in[i*2].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in_be16((void *)&(in[i*2+1].val));
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	printf("Channel %d OK!\n", i);
+
+	return 0;
+}
+U_BOOT_CMD(
+	anatest,	2,	1,	do_anatest,
+	"Test analog in-/output",
+	""
+);
+
+
+int counter = 0;
+
+void cyclicInt(void *ptr)
+{
+	out_be16((void *)0xf03000e8, 0x0800); /* ack int */
+	counter++;
+}
+
+
+int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong *incin;
+	int i;
+
+	incin = (ulong *)0xf0300040;
+
+	/*
+	 * Clear inc counter
+	 */
+	out_be32((void *)&incin[0], 0);
+	out_be32((void *)&incin[1], 0);
+	out_be32((void *)&incin[2], 0);
+	out_be32((void *)&incin[3], 0);
+
+	incin = (ulong *)0xf0300050;
+
+	/*
+	 * Inc a little
+	 */
+	for (i=0; i<10000; i++) {
+		switch (i & 0x03) {
+		case 0:
+			out_8(DIGEN, 0x02);
+			break;
+		case 1:
+			out_8(DIGEN, 0x03);
+			break;
+		case 2:
+			out_8(DIGEN, 0x01);
+			break;
+		case 3:
+			out_8(DIGEN, 0x00);
+			break;
+		}
+		udelay(10);
+	}
+
+	printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
+	printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
+	printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
+	printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
+
+	out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
+	out_be16((void *)0xf03000ec,
+		 in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
+	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
+	printf("counter=%d\n", counter);
+
+	return 0;
+}
+U_BOOT_CMD(
+	inctest,	3,	1,	do_inctest,
+	"Test incremental encoder inputs",
+	""
+);
+#endif
diff --git a/roms/u-boot/board/esd/ar405/ar405.h b/roms/u-boot/board/esd/ar405/ar405.h
new file mode 100644
index 00000000..75e7950b
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/ar405.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/roms/u-boot/board/esd/ar405/flash.c b/roms/u-boot/board/esd/ar405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/ar405/fpgadata.c b/roms/u-boot/board/esd/ar405/fpgadata.c
new file mode 100644
index 00000000..055ab6ba
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/fpgadata.c
@@ -0,0 +1,5500 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
+0x70, 0x70, 0x63, 0x5f, 0x61, 0x72, 0x30, 0x31,
+0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
+0x73, 0x34, 0x30, 0x78, 0x6c, 0x70, 0x71, 0x32,
+0x34, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
+0x30, 0x31, 0x2f, 0x30, 0x32, 0x2f, 0x31, 0x34,
+0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x34,
+0x30, 0x3a, 0x30, 0x34, 0x00, 0x65, 0xe2, 0x01,
+0x00, 0x00, 0xab, 0x8e, 0xff, 0x30, 0xe5, 0xe5,
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diff --git a/roms/u-boot/board/esd/ar405/fpgadata_xl30.c b/roms/u-boot/board/esd/ar405/fpgadata_xl30.c
new file mode 100644
index 00000000..42a9206c
--- /dev/null
+++ b/roms/u-boot/board/esd/ar405/fpgadata_xl30.c
@@ -0,0 +1,4872 @@
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+0x02, 0x02, 0x04, 0x06, 0x01, 0xe5, 0x51, 0x01,
+0xe7, 0x1e, 0x05, 0x35, 0x08, 0x0f, 0x08, 0x05,
+0x01, 0xe5, 0x05, 0x06, 0x09, 0x0f, 0xe5, 0xe5,
+0x19, 0x06, 0x27, 0x0b, 0x01, 0xe6, 0x07, 0x04,
+0xe5, 0xe5, 0x10, 0x09, 0x09, 0x2b, 0x09, 0x09,
+0x01, 0x0a, 0xe5, 0x04, 0x05, 0x09, 0x10, 0x01,
+0x02, 0x0a, 0x09, 0x03, 0x01, 0x02, 0x09, 0x13,
+0x17, 0x01, 0x02, 0x0a, 0x02, 0x13, 0x09, 0xe7,
+0x05, 0xe5, 0xe5, 0x08, 0x06, 0x01, 0xe5, 0x08,
+0x03, 0x0f, 0x03, 0x05, 0x09, 0xe5, 0x04, 0x0e,
+0x16, 0x0d, 0x01, 0x0f, 0x14, 0xe5, 0x01, 0x06,
+0x0d, 0x0c, 0x03, 0x02, 0x0c, 0x13, 0xe5, 0x11,
+0x1a, 0x1d, 0x12, 0x01, 0x08, 0xe5, 0x04, 0xe6,
+0x19, 0x1d, 0x05, 0x03, 0x05, 0x02, 0x07, 0x02,
+0x17, 0x02, 0xe5, 0x11, 0x12, 0x18, 0x09, 0x04,
+0x0c, 0x06, 0x14, 0x0e, 0x06, 0x08, 0x03, 0x14,
+0x04, 0x03, 0x0a, 0x04, 0x1c, 0x03, 0x12, 0x0a,
+0x01, 0x01, 0x46, 0x1b, 0x02, 0x0f, 0x03, 0x06,
+0x03, 0xe6, 0x1b, 0x05, 0xe5, 0x13, 0x0c, 0x3d,
+0xe5, 0x0f, 0x02, 0x04, 0x02, 0x01, 0x02, 0x01,
+0x04, 0xe5, 0x02, 0x09, 0x04, 0x04, 0x03, 0x05,
+0x01, 0x02, 0x04, 0x09, 0x01, 0x02, 0x04, 0x2b,
+0x16, 0x04, 0x09, 0x0d, 0x01, 0x03, 0x04, 0x02,
+0x01, 0x13, 0x01, 0x07, 0x09, 0x06, 0x01, 0x04,
+0x0c, 0x01, 0x03, 0x01, 0x09, 0x08, 0x07, 0x01,
+0xe5, 0xe5, 0xe5, 0x03, 0xe5, 0x0c, 0x05, 0x09,
+0x08, 0xe6, 0xe5, 0x13, 0x13, 0x08, 0x0a, 0x07,
+0x06, 0x02, 0x07, 0x01, 0x09, 0x09, 0x07, 0x01,
+0x09, 0x02, 0x06, 0x02, 0x0e, 0xe5, 0x16, 0x0a,
+0x0e, 0x05, 0x09, 0x03, 0x03, 0x09, 0x01, 0x01,
+0xe5, 0x03, 0xe5, 0x09, 0x06, 0x1f, 0x1e, 0xe5,
+0x07, 0xe5, 0x11, 0xe5, 0x04, 0x04, 0x01, 0x0f,
+0xe5, 0x07, 0x01, 0x0b, 0x03, 0xe5, 0xe5, 0x0b,
+0x02, 0xe5, 0x08, 0x09, 0x09, 0x09, 0x04, 0xe5,
+0x02, 0x09, 0x09, 0x05, 0x02, 0xe5, 0xe5, 0x01,
+0xe5, 0x01, 0xe5, 0xe5, 0x03, 0xe7, 0x07, 0xe5,
+0x03, 0x05, 0xe5, 0x05, 0xe7, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x08, 0x04, 0xe5, 0x02, 0x04,
+0x04, 0x08, 0xe5, 0x03, 0x04, 0x08, 0xe5, 0x07,
+0xe5, 0x0c, 0x02, 0xe5, 0x17, 0x14, 0x05, 0x0a,
+0x09, 0x01, 0x0a, 0x08, 0x01, 0x08, 0xe5, 0x01,
+0x01, 0x02, 0x01, 0x09, 0x02, 0x07, 0xe5, 0x06,
+0x01, 0x09, 0x08, 0xe5, 0x08, 0x0e, 0x18, 0x09,
+0x09, 0x09, 0x0e, 0x02, 0x03, 0x0b, 0x06, 0x02,
+0x06, 0x0c, 0x06, 0x0c, 0x0e, 0x01, 0x02, 0x02,
+0x06, 0x03, 0x05, 0x03, 0x05, 0x06, 0x02, 0x04,
+0x01, 0x04, 0x03, 0x02, 0x02, 0x09, 0x09, 0x03,
+0x03, 0x01, 0x07, 0x01, 0x07, 0x07, 0x01, 0x01,
+0x09, 0xe5, 0x11, 0x09, 0x0f, 0x02, 0x08, 0xe5,
+0x1c, 0x08, 0x13, 0x09, 0x03, 0x09, 0x0d, 0x0b,
+0x09, 0x0b, 0x17, 0x03, 0x0b, 0x09, 0xe5, 0x07,
+0x27, 0x12, 0x02, 0xe6, 0xe5, 0x0e, 0x01, 0x0c,
+0x04, 0x04, 0x05, 0x05, 0x02, 0x13, 0x0a, 0x03,
+0x18, 0x09, 0x0b, 0xe5, 0x04, 0x02, 0x09, 0x01,
+0x07, 0x07, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x02,
+0x01, 0x01, 0x01, 0x04, 0x0e, 0x09, 0x09, 0x0f,
+0x01, 0xe5, 0x0b, 0xe6, 0x07, 0xe5, 0x05, 0x01,
+0xe5, 0x02, 0x04, 0xe5, 0x07, 0xe5, 0x04, 0x02,
+0xe5, 0x04, 0x02, 0xe5, 0x04, 0x02, 0xe5, 0x07,
+0xe6, 0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x08,
+0xe6, 0x07, 0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x07,
+0x13, 0x03, 0x03, 0x0b, 0xe5, 0x01, 0x05, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x0e, 0x01, 0xe6, 0x02,
+0x09, 0x01, 0x07, 0x05, 0x03, 0x01, 0x07, 0x07,
+0x01, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x06, 0x09,
+0x04, 0x04, 0x09, 0x09, 0x0a, 0xe5, 0x02, 0x05,
+0x09, 0x05, 0x03, 0x12, 0x0c, 0x04, 0x05, 0x06,
+0x08, 0xe5, 0x08, 0x09, 0x0b, 0x06, 0x01, 0x0e,
+0xe5, 0x07, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
+0x09, 0x09, 0x09, 0xe5, 0x07, 0x02, 0x06, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x0b, 0x02, 0xe5, 0x0d,
+0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x02, 0x04,
+0x09, 0x01, 0x07, 0x09, 0x01, 0x07, 0x03, 0x05,
+0x05, 0x03, 0x02, 0x06, 0x0b, 0x04, 0x04, 0x09,
+0x1f, 0x07, 0x13, 0x09, 0x09, 0x09, 0x02, 0x10,
+0x12, 0x44, 0x02, 0x04, 0xe5, 0x04, 0x02, 0xe5,
+0x18, 0x25, 0x01, 0x01, 0x21, 0x2f, 0x05, 0x01,
+0x01, 0x0e, 0x09, 0x02, 0x06, 0x02, 0x06, 0x09,
+0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09,
+0x09, 0x09, 0x01, 0xe5, 0x05, 0x05, 0x03, 0x02,
+0x05, 0x02, 0x09, 0x02, 0xe5, 0x04, 0x04, 0x03,
+0xe5, 0x07, 0x03, 0x05, 0xe5, 0x08, 0x05, 0x02,
+0xe5, 0x02, 0x03, 0x01, 0x04, 0x04, 0x09, 0x09,
+0x09, 0x06, 0xe5, 0xe5, 0x06, 0x18, 0x09, 0x09,
+0x1d, 0x0f, 0x13, 0x03, 0x0a, 0x0a, 0x04, 0x10,
+0x09, 0x06, 0xe5, 0xe5, 0x4a, 0xe5, 0x01, 0x07,
+0x08, 0xe5, 0x07, 0x09, 0x09, 0x03, 0x05, 0x09,
+0x09, 0xe5, 0x07, 0x09, 0x09, 0x09, 0x05, 0x03,
+0x06, 0xe5, 0x02, 0x09, 0x09, 0x09, 0xe5, 0x07,
+0x07, 0x01, 0x01, 0x07, 0x01, 0x07, 0x05, 0x03,
+0x01, 0x07, 0x09, 0x09, 0x0e, 0x01, 0xe5, 0x03,
+0x61, 0x11, 0x01, 0x07, 0x0b, 0x09, 0x09, 0x03,
+0x05, 0x02, 0xe5, 0x05, 0x15, 0x3b, 0xe5, 0x14,
+0x13, 0x13, 0x09, 0x14, 0x09, 0x0d, 0x09, 0x06,
+0x04, 0x09, 0x04, 0xe5, 0x02, 0x04, 0x04, 0x18,
+0x13, 0x09, 0x27, 0xe5, 0xe5, 0x09, 0x17, 0x06,
+0x02, 0x4f, 0x4f, 0x09, 0x2b, 0x05, 0xe6, 0x0a,
+0x3b, 0x27, 0x5b, 0x3c, 0xe6, 0x3c, 0x5b, 0x1e,
+0x26, 0x27, 0xe5, 0xe5, 0x03, 0x10, 0x31, 0x2a,
+0x05, 0x03, 0x05, 0x02, 0x02, 0x05, 0x03, 0x05,
+0x03, 0x05, 0xe5, 0x01, 0x05, 0x14, 0x13, 0x29,
+0x06, 0xe5, 0xe6, 0x46, 0x27, 0x15, 0x46, 0x33,
+0x05, 0xe5, 0x01, 0x04, 0x57, 0xa9, 0x03, 0x14,
+0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
+0xe6, 0x06, 0x09, 0xe6, 0x06, 0x09, 0x0b, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
+0x09, 0x09, 0x09, 0x0a, 0x02, 0x05, 0x09, 0x08,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0x01,
+0xe5, 0x07, 0xe5, 0x05, 0x02, 0x09, 0x07, 0x03,
+0x09, 0x09, 0x09, 0x09, 0x04, 0x03, 0xe5, 0x07,
+0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x08, 0x09, 0x10, 0xe6, 0x15, 0x05, 0x03, 0x05,
+0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
+0x03, 0x05, 0x03, 0x09, 0x05, 0x03, 0x04, 0x09,
+0x05, 0x05, 0x09, 0x09, 0x09, 0x14, 0x03, 0x09,
+0x05, 0x03, 0x09, 0x27, 0x01, 0x0d, 0x03, 0x03,
+0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03,
+0x09, 0x05, 0x03, 0x09, 0x05, 0x03, 0x09, 0x01,
+0x04, 0x04, 0x04, 0x06, 0x04, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0x06, 0x0b, 0x03, 0x09, 0x09,
+0x09, 0x09, 0x03, 0x05, 0x03, 0x0d, 0x02, 0x01,
+0x0b, 0x06, 0x01, 0x02, 0x01, 0x04, 0x02, 0x01,
+0x04, 0x02, 0x01, 0x04, 0x02, 0x01, 0x04, 0x02,
+0x01, 0x01, 0x05, 0x01, 0x04, 0x02, 0x01, 0x01,
+0x05, 0x01, 0x02, 0x01, 0x02, 0x01, 0x01, 0xe5,
+0x06, 0x02, 0x02, 0x03, 0x02, 0x02, 0x05, 0x02,
+0x02, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02, 0x03,
+0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x04, 0x02,
+0x01, 0x01, 0xe5, 0x03, 0x01, 0x01, 0x02, 0x04,
+0x02, 0x01, 0x02, 0x01, 0x01, 0x02, 0x04, 0x04,
+0x04, 0x06, 0x02, 0x02, 0xe6, 0xe5, 0xe5, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/roms/u-boot/board/esd/ash405/Makefile b/roms/u-boot/board/esd/ash405/Makefile
new file mode 100644
index 00000000..aab8de44
--- /dev/null
+++ b/roms/u-boot/board/esd/ash405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ash405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/ash405/ash405.c b/roms/u-boot/board/esd/ash405/ash405.c
new file mode 100644
index 00000000..4460a19c
--- /dev/null
+++ b/roms/u-boot/board/esd/ash405/ash405.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming ASH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/ash405/flash.c b/roms/u-boot/board/esd/ash405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/ash405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/ash405/fpgadata.c b/roms/u-boot/board/esd/ash405/fpgadata.c
new file mode 100644
index 00000000..6e29053e
--- /dev/null
+++ b/roms/u-boot/board/esd/ash405/fpgadata.c
@@ -0,0 +1,4983 @@
+0x1f, 0x8b, 0x08, 0x08, 0x5c, 0xa1, 0x5d, 0x3f,
+0x00, 0x03, 0x61, 0x73, 0x68, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x32, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xec, 0xfd, 0x0f, 0x78, 0x1c, 0xe5,
+0x91, 0x2f, 0x0a, 0x57, 0xbf, 0xdd, 0x92, 0x5f,
+0x4d, 0x8f, 0x34, 0xad, 0x91, 0x4c, 0x14, 0x30,
+0xa6, 0x35, 0x92, 0xcd, 0x58, 0x19, 0xc9, 0xe3,
+0x91, 0x90, 0x85, 0x10, 0xa3, 0xb6, 0x24, 0x58,
+0x45, 0x36, 0x58, 0x71, 0xd8, 0x2c, 0x67, 0x97,
+0x93, 0x1d, 0x88, 0x93, 0xe3, 0xdd, 0x75, 0x72,
+0x1c, 0x36, 0x37, 0xc7, 0x21, 0x6c, 0xf2, 0x6a,
+0x24, 0xe3, 0xb1, 0x65, 0xe3, 0xc1, 0x38, 0xc1,
+0x04, 0x92, 0x3b, 0xfe, 0x43, 0x10, 0xe0, 0x24,
+0x63, 0xd9, 0x60, 0x19, 0x1b, 0x68, 0x09, 0x41,
+0xc6, 0xb6, 0xb0, 0x15, 0xc7, 0x9b, 0x35, 0xc4,
+0x0b, 0x63, 0x50, 0x88, 0x30, 0x82, 0xc8, 0xe0,
+0x24, 0xb2, 0x2d, 0xec, 0x5b, 0xd5, 0x23, 0xcd,
+0xf4, 0x38, 0x7b, 0xf6, 0xec, 0xde, 0xf3, 0xdc,
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+0x2b, 0xdd, 0xed, 0xa6, 0xfb, 0x9d, 0xb7, 0xab,
+0x7e, 0x55, 0xf5, 0xab, 0x2a, 0xc8, 0x73, 0x8d,
+0xa7, 0xfe, 0x1f, 0x80, 0x74, 0x37, 0x68, 0x77,
+0xff, 0xfd, 0x8a, 0x1a, 0xff, 0x0d, 0x7f, 0xbd,
+0xe0, 0xaf, 0xfd, 0x81, 0xaa, 0xaf, 0x7d, 0x69,
+0x39, 0xdc, 0x03, 0x6a, 0xe0, 0xef, 0x6f, 0xf0,
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+0x5f, 0xc2, 0xff, 0xe5, 0xf7, 0x57, 0xcf, 0xf7,
+0xdf, 0x88, 0xff, 0x1f, 0x96, 0x43, 0xde, 0x82,
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+0x32, 0x48, 0xd5, 0x3b, 0x2f, 0xe3, 0xdf, 0xd3,
+0x8f, 0xfe, 0xf9, 0x57, 0xfc, 0x20, 0x24, 0x00,
+0x98, 0xe1, 0x97, 0x42, 0xf4, 0x7f, 0x55, 0xbf,
+0xa4, 0x4b, 0x20, 0x1a, 0x2b, 0xfd, 0x60, 0xd2,
+0xff, 0x86, 0xa9, 0xf3, 0x79, 0x7e, 0xd0, 0xed,
+0xff, 0x5b, 0xf2, 0x83, 0x01, 0xed, 0x60, 0x6c,
+0x00, 0xb7, 0x1f, 0xfe, 0xd7, 0x7f, 0x86, 0x22,
+0xa6, 0xc5, 0x7f, 0xe7, 0xf5, 0x97, 0x0f, 0x8b,
+0xff, 0xe9, 0x55, 0x99, 0xbf, 0xc6, 0x8f, 0x62,
+0xd3, 0x22, 0xfb, 0x37, 0xdc, 0x5f, 0x32, 0x20,
+0x7d, 0xff, 0x37, 0xfe, 0x4d, 0xf7, 0xff, 0xc3,
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+0x4c, 0x34, 0x24, 0x67, 0xac, 0x92, 0x67, 0x19,
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+0x53, 0xe8, 0x81, 0x36, 0x14, 0x94, 0xbe, 0xc2,
+0xb9, 0x0a, 0x09, 0x2d, 0x11, 0x9b, 0xfe, 0xe4,
+0x66, 0x1e, 0x14, 0x41, 0xb1, 0x99, 0x43, 0xb4,
+0x72, 0x19, 0x05, 0x48, 0x59, 0x1b, 0x3c, 0x52,
+0x27, 0xdd, 0x9e, 0x12, 0xfc, 0x92, 0x91, 0xf9,
+0x07, 0xe8, 0xaa, 0xfe, 0x5f, 0xed, 0x9d, 0x41,
+0x6c, 0xdb, 0x54, 0x18, 0xc7, 0xbf, 0x97, 0xbc,
+0x66, 0x0e, 0x4a, 0x2b, 0x7b, 0xca, 0x84, 0x03,
+0x55, 0x95, 0x8c, 0x52, 0x76, 0x74, 0x24, 0x2a,
+0x15, 0x71, 0xd8, 0x4b, 0x53, 0x27, 0x61, 0x52,
+0xc1, 0x50, 0x40, 0x13, 0x27, 0x17, 0xf5, 0x30,
+0x26, 0x21, 0xa5, 0x08, 0xa4, 0x9d, 0x90, 0x53,
+0x02, 0x2a, 0x1c, 0x50, 0x56, 0x81, 0x68, 0x6f,
+0x39, 0x4c, 0x70, 0xe2, 0xc8, 0x3d, 0x2b, 0x62,
+0x62, 0xb7, 0x1d, 0xa2, 0x71, 0xa4, 0x93, 0xb8,
+0x70, 0x47, 0x42, 0x1c, 0xc6, 0xf8, 0x3e, 0x3f,
+0xc7, 0x7e, 0xcd, 0xa6, 0x48, 0xdb, 0x01, 0x24,
+0xf4, 0xfd, 0x4f, 0x7f, 0x3d, 0xbf, 0xba, 0xcf,
+0xf6, 0xf3, 0xdf, 0xbf, 0xcf, 0x96, 0x1d, 0x9b,
+0x2a, 0xe3, 0x00, 0xe8, 0xa3, 0xd0, 0x54, 0x89,
+0x62, 0xa4, 0xf9, 0xc4, 0x87, 0x81, 0x28, 0xc3,
+0x06, 0x38, 0x20, 0xaf, 0x89, 0xf4, 0xf6, 0x39,
+0xae, 0x5f, 0x57, 0xca, 0xd5, 0xaa, 0xae, 0x54,
+0xed, 0xb8, 0xc0, 0x94, 0x16, 0x21, 0xc2, 0xbe,
+0x7d, 0x5e, 0x5a, 0xbd, 0xf8, 0xe1, 0xbe, 0xd9,
+0x5f, 0x86, 0x3a, 0x24, 0xa3, 0x38, 0x2d, 0xd7,
+0x71, 0x6f, 0x17, 0x74, 0x8b, 0x13, 0x25, 0x8b,
+0xea, 0x51, 0xda, 0xdf, 0x16, 0x2a, 0x1f, 0xc2,
+0x21, 0xac, 0x54, 0x69, 0x8f, 0xe0, 0x6e, 0x5c,
+0x81, 0xe2, 0x3e, 0xec, 0x50, 0x8b, 0x2a, 0xd2,
+0x37, 0x84, 0x8e, 0x70, 0x11, 0x5e, 0x01, 0x27,
+0x52, 0xfe, 0xba, 0xec, 0x12, 0x14, 0x5d, 0xc1,
+0xeb, 0x1d, 0x61, 0xa1, 0xe6, 0xc3, 0xcf, 0xc9,
+0x0c, 0x8e, 0x97, 0x35, 0x1f, 0x0e, 0x46, 0xe9,
+0xf3, 0x74, 0xda, 0xf2, 0xea, 0x34, 0x1f, 0xaa,
+0x87, 0x4c, 0x5a, 0x91, 0x2b, 0xdc, 0x4a, 0x4f,
+0x43, 0xda, 0xde, 0xc4, 0xfc, 0x28, 0x13, 0x73,
+0xac, 0x5b, 0x4a, 0xf6, 0x28, 0x7d, 0x7e, 0xa4,
+0x7c, 0xa5, 0xf9, 0x8d, 0x1e, 0x05, 0xa0, 0x81,
+0x96, 0xe5, 0x7c, 0x42, 0x9b, 0x59, 0xd5, 0xdb,
+0x4b, 0x8b, 0xa4, 0x93, 0xf1, 0xa1, 0x12, 0x8f,
+0xe2, 0x43, 0x6f, 0xaa, 0x25, 0x1b, 0x4f, 0x20,
+0xd6, 0xf5, 0x4a, 0x70, 0x69, 0x62, 0x1c, 0x02,
+0xe3, 0xc4, 0xe8, 0x16, 0x7b, 0x94, 0xce, 0x08,
+0x1a, 0x0f, 0x1d, 0x48, 0x1f, 0x92, 0x23, 0xea,
+0x83, 0x83, 0x65, 0x40, 0x62, 0x92, 0x16, 0x58,
+0x4f, 0xc7, 0xd3, 0xc1, 0x69, 0xd0, 0x88, 0xca,
+0xe1, 0x9c, 0x2b, 0x0a, 0xb0, 0x1b, 0xd9, 0xa1,
+0x24, 0xd3, 0x98, 0x32, 0x20, 0xd2, 0xf7, 0x49,
+0xf1, 0x7c, 0x04, 0xfd, 0x82, 0x01, 0xdd, 0xc8,
+0x55, 0x31, 0x1f, 0x6a, 0x2c, 0x24, 0x50, 0x4c,
+0x4c, 0x36, 0xdd, 0x94, 0xff, 0x36, 0xd2, 0x60,
+0x3f, 0xac, 0xe1, 0x95, 0x1a, 0x41, 0xf1, 0xad,
+0x09, 0x1f, 0x8e, 0x4f, 0x19, 0x95, 0x5d, 0xdf,
+0x45, 0x4b, 0xee, 0xf6, 0x16, 0xc3, 0xb6, 0xed,
+0xdc, 0xd2, 0xc6, 0x75, 0x6e, 0x15, 0x3e, 0x12,
+0x68, 0x02, 0x67, 0x2c, 0x77, 0xc5, 0xa2, 0x6a,
+0x5f, 0xae, 0x8c, 0xb2, 0xf5, 0x8b, 0x16, 0x10,
+0x1f, 0x9e, 0x41, 0x1a, 0xcc, 0x91, 0x79, 0xc1,
+0x2d, 0x66, 0x26, 0xbf, 0x1d, 0x1b, 0x23, 0x4f,
+0x02, 0x5f, 0xf3, 0xe7, 0xd3, 0xae, 0xc8, 0xf8,
+0x13, 0x56, 0x63, 0x62, 0x3c, 0x77, 0x17, 0xf9,
+0x90, 0x8c, 0x73, 0x9c, 0x1d, 0x2f, 0xc4, 0xe0,
+0x38, 0x7f, 0x3a, 0xf2, 0x00, 0xcd, 0x2b, 0x3a,
+0x7f, 0x3e, 0xcc, 0x5a, 0x62, 0x63, 0x8c, 0x07,
+0x27, 0xf0, 0x76, 0xe4, 0x86, 0x85, 0x43, 0xf8,
+0x16, 0xcd, 0x33, 0x61, 0xc1, 0x15, 0x9f, 0xc9,
+0xb8, 0x05, 0x8d, 0x5e, 0xe4, 0x9a, 0xf9, 0xe3,
+0x87, 0x73, 0x17, 0x6a, 0x0b, 0x58, 0xa1, 0xc1,
+0xb0, 0xbf, 0x26, 0x96, 0xd0, 0x38, 0x27, 0x78,
+0x06, 0x2e, 0x41, 0x1b, 0x4d, 0x3f, 0x31, 0x23,
+0x63, 0xfe, 0xbc, 0x81, 0x34, 0x18, 0xff, 0xba,
+0xd8, 0x01, 0x96, 0x7a, 0x15, 0x2f, 0x87, 0x58,
+0x18, 0xed, 0x10, 0x16, 0x76, 0xc4, 0x81, 0x06,
+0xc5, 0x8e, 0x91, 0x3f, 0x38, 0xdf, 0x90, 0x06,
+0x63, 0x3e, 0xfc, 0xa2, 0x8f, 0x34, 0x38, 0x6c,
+0x9d, 0xe2, 0xc3, 0xc4, 0x18, 0xfd, 0xf1, 0xfc,
+0x52, 0x8d, 0xf2, 0x59, 0x1f, 0x06, 0x38, 0x7f,
+0x7a, 0x76, 0xd5, 0xb7, 0x1c, 0x3c, 0xd5, 0xe3,
+0xdf, 0xd1, 0xc1, 0x68, 0xd0, 0x46, 0x80, 0xb1,
+0x7f, 0xb0, 0xa4, 0x1c, 0x95, 0xbd, 0x39, 0x0b,
+0x2e, 0xd1, 0xaf, 0x97, 0x0f, 0x45, 0x49, 0x34,
+0x21, 0xa0, 0x16, 0xc3, 0xa8, 0x6c, 0x7e, 0x62,
+0x1e, 0x7a, 0xc8, 0x87, 0x1b, 0x34, 0x55, 0xf0,
+0x4f, 0x41, 0xd0, 0xb7, 0xe0, 0x34, 0x16, 0x36,
+0x26, 0xc6, 0xc8, 0x37, 0x1c, 0x4f, 0xf5, 0x2c,
+0xf2, 0x61, 0x88, 0xf1, 0x70, 0x1e, 0x69, 0x10,
+0x4b, 0x6c, 0xc2, 0xc2, 0x7d, 0xc2, 0xc2, 0xfd,
+0xdc, 0x10, 0x5b, 0x96, 0xd1, 0x18, 0xe3, 0x11,
+0x49, 0xfe, 0xe4, 0xb1, 0x2a, 0xc1, 0xfc, 0xb1,
+0xf4, 0x69, 0x58, 0xa7, 0xd8, 0xb9, 0x1e, 0x7d,
+0x15, 0x56, 0xc8, 0x54, 0xcc, 0xfd, 0xa3, 0x30,
+0x6d, 0x2a, 0xb0, 0xd2, 0xec, 0x0d, 0xf6, 0x42,
+0x71, 0x64, 0x61, 0xfe, 0x0c, 0x44, 0x77, 0x0d,
+0xf3, 0x27, 0x57, 0xc4, 0x16, 0x1b, 0x0d, 0x18,
+0xd7, 0x2f, 0xe5, 0x87, 0xd1, 0x1a, 0xd0, 0xf1,
+0x1a, 0xd1, 0xf1, 0xfa, 0x52, 0x62, 0x69, 0x7d,
+0x22, 0x2f, 0x58, 0xd8, 0xb2, 0x37, 0x38, 0xd9,
+0x59, 0x2b, 0x2e, 0xe4, 0x9a, 0x3d, 0xe3, 0x7c,
+0x0f, 0x40, 0xc8, 0x97, 0xc2, 0x85, 0xcb, 0xf9,
+0xaf, 0xe1, 0x3b, 0xfa, 0x16, 0x98, 0x9d, 0x97,
+0xf0, 0xd3, 0x43, 0xc6, 0x18, 0x0f, 0xf2, 0xe4,
+0xaa, 0x9a, 0xef, 0xe6, 0x83, 0xc1, 0x18, 0xea,
+0x6a, 0x5e, 0xe5, 0xcb, 0xf0, 0x8b, 0xac, 0x77,
+0x4a, 0x01, 0x19, 0x6c, 0x21, 0x63, 0x1f, 0x1b,
+0xe3, 0x69, 0xca, 0xed, 0x9b, 0x6e, 0x17, 0xf3,
+0x01, 0x63, 0x67, 0xe4, 0x7a, 0xad, 0x92, 0xf3,
+0x8d, 0x0c, 0x6f, 0x9e, 0x36, 0x66, 0xfe, 0x28,
+0xcd, 0x87, 0x65, 0xe4, 0xd5, 0x19, 0xf7, 0x11,
+0xb3, 0xfd, 0xd3, 0xd9, 0x48, 0xf8, 0x30, 0xda,
+0x79, 0xd7, 0x46, 0x53, 0x73, 0x0e, 0x65, 0x82,
+0x85, 0xa9, 0x89, 0xcc, 0xfc, 0xf1, 0xe5, 0xeb,
+0xe7, 0xa4, 0x8f, 0xb8, 0xbc, 0x11, 0xd8, 0x65,
+0xe9, 0x0b, 0x47, 0x29, 0x8c, 0x1d, 0xa9, 0xf3,
+0xc7, 0x21, 0x23, 0x94, 0x31, 0x7f, 0x68, 0x02,
+0xa6, 0xc9, 0x67, 0x63, 0xc9, 0x45, 0x53, 0x12,
+0xec, 0x3d, 0xa3, 0x70, 0xe8, 0x65, 0xf9, 0x03,
+0x44, 0x83, 0x3d, 0xba, 0x0d, 0x6c, 0x3f, 0xe5,
+0x10, 0x16, 0xc2, 0xa3, 0x40, 0xd1, 0x9c, 0x3f,
+0x9b, 0x62, 0xab, 0xd1, 0xbf, 0x53, 0x7b, 0xd1,
+0xdd, 0xcc, 0x6d, 0xa9, 0x31, 0x9a, 0xf9, 0xcd,
+0xfc, 0x96, 0x7a, 0xf3, 0xce, 0xaa, 0x36, 0x63,
+0x32, 0xc6, 0x78, 0x84, 0xb5, 0xfc, 0x41, 0x63,
+0x71, 0xd0, 0xae, 0x39, 0xb7, 0x3f, 0xed, 0xea,
+0xab, 0xff, 0xcf, 0x85, 0x18, 0x03, 0x20, 0x01,
+0x83, 0x76, 0xd5, 0xc8, 0x1f, 0xbc, 0x5e, 0x5f,
+0x6d, 0xdd, 0xbd, 0xfe, 0xc3, 0x8d, 0xf7, 0x8f,
+0x9e, 0xbd, 0x7a, 0x89, 0xf8, 0xf0, 0xfb, 0xf7,
+0x34, 0x1f, 0xde, 0xc8, 0xf8, 0xb0, 0x68, 0x74,
+0x87, 0x8b, 0x19, 0x1f, 0xbe, 0x46, 0x7c, 0xf8,
+0xe0, 0xbe, 0xe6, 0xc3, 0x3f, 0x32, 0x3e, 0x3c,
+0xc5, 0x63, 0x8f, 0xab, 0xe7, 0x09, 0x0b, 0x7f,
+0x1f, 0x3c, 0xb8, 0x7f, 0xf1, 0xaf, 0x04, 0x14,
+0x91, 0x18, 0x67, 0xf0, 0x61, 0xfc, 0xdf, 0xff,
+0xfc, 0x0d, 0xfb, 0xff, 0x3d, 0x01, 0xc5, 0x8f,
+0x67, 0xf1, 0xe1, 0xcb, 0x13, 0x3e, 0x7c, 0x6e,
+0xe9, 0xd5, 0x5f, 0x0f, 0xea, 0xd4, 0xff, 0xda,
+0x54, 0xff, 0x7b, 0x4f, 0x3e, 0x7a, 0x0f, 0xa1,
+0x81, 0xbe, 0xd8, 0xe8, 0x41, 0xb3, 0xf4, 0xe4,
+0x6b, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5,
+0x62, 0xb1, 0x58, 0xff, 0x77, 0xc5, 0xb5, 0x83,
+0xe4, 0xda, 0x81, 0xc5, 0x62, 0xb1, 0x58, 0x2c,
+0x16, 0x8b, 0xc5, 0x62, 0xcd, 0x56, 0x5c, 0x3b,
+0x14, 0xb8, 0x76, 0x60, 0xb1, 0x58, 0x2c, 0x16,
+0x8b, 0xc5, 0x62, 0xb1, 0x58, 0xb3, 0x15, 0xd7,
+0x0e, 0x56, 0x5c, 0x3b, 0xfc, 0xd7, 0x43, 0x61,
+0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1,
+0x58, 0xff, 0xa2, 0x3c, 0x7a, 0x81, 0x1c, 0x0a,
+0xb7, 0x3d, 0x88, 0xdf, 0x89, 0xc9, 0x7b, 0xa0,
+0x1e, 0xfb, 0x79, 0x42, 0xf2, 0xb7, 0x73, 0x1e,
+0x0c, 0x45, 0xb6, 0xce, 0x7b, 0xef, 0x4c, 0xf7,
+0xfb, 0x07, 0x18, 0x78, 0xae, 0x50, 0xf1, 0x33,
+0x01, 0x00,
diff --git a/roms/u-boot/board/esd/cms700/Makefile b/roms/u-boot/board/esd/cms700/Makefile
new file mode 100644
index 00000000..2bf50066
--- /dev/null
+++ b/roms/u-boot/board/esd/cms700/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+obj-y	= cms700.o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/cms700/cms700.c b/roms/u-boot/board/esd/cms700/cms700.c
new file mode 100644
index 00000000..40d7621f
--- /dev/null
+++ b/roms/u-boot/board/esd/cms700/cms700.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2005-2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
+int checkboard (void)
+{
+	char str[64];
+	int flashcnt;
+	int delay;
+
+	puts ("Board: ");
+
+	if (getenv_f("serial#", str, sizeof(str))  == -1) {
+		puts ("### No HW ID - assuming CMS700");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n",
+	       in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		out_8((void *)LED_REG, 0x00); /* LEDs off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		out_8((void *)LED_REG, 0x0f); /* LEDs on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	out_8((void *)LED_REG, 0x70);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/cms700/flash.c b/roms/u-boot/board/esd/cms700/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/cms700/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/common/auto_update.c b/roms/u-boot/board/esd/common/auto_update.c
new file mode 100644
index 00000000..85c3567b
--- /dev/null
+++ b/roms/u-boot/board/esd/common/auto_update.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <command.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <fat.h>
+#include <part.h>
+
+#include "auto_update.h"
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#if !defined(CONFIG_CMD_FAT)
+#error "must define CONFIG_CMD_FAT"
+#endif
+
+extern au_image_t au_image[];
+extern int N_AU_IMAGES;
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x100000)
+#define MAX_LOADSZ 0x1c00000
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+long do_fat_read (const char *filename, void *buffer,
+		  unsigned long maxsize, int dols);
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+
+extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+int au_check_cksum_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	if ((au_image[i].type == AU_FIRMWARE) &&
+	    (au_image[i].size != image_get_data_size (hdr))) {
+		printf ("Image %s has wrong size\n", au_image[i].name);
+		return -1;
+	}
+
+	if (nbytes != (image_get_image_size (hdr))) {
+		printf ("Image %s bad total SIZE\n", au_image[i].name);
+		return -1;
+	}
+
+	/* check the data CRC */
+	if (!image_check_dcrc (hdr)) {
+		printf ("Image %s bad data checksum\n", au_image[i].name);
+		return -1;
+	}
+	return 0;
+}
+
+int au_check_header_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	/* check the easy ones first */
+	if (nbytes < image_get_header_size ()) {
+		printf ("Image %s bad header SIZE\n", au_image[i].name);
+		return -1;
+	}
+	if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
+		printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
+		return -1;
+	}
+	if (!image_check_hcrc (hdr)) {
+		printf ("Image %s bad header checksum\n", au_image[i].name);
+		return -1;
+	}
+
+	/* check the type - could do this all in one gigantic if() */
+	if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) &&
+	    !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+	if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) &&
+	    !image_check_type (hdr, IH_TYPE_SCRIPT)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+
+	return 0;
+}
+
+int au_do_update(int i, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+	int k;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+		puts ("Non legacy image format not supported\n");
+		return -1;
+	}
+#endif
+
+	switch (au_image[i].type & AU_TYPEMASK) {
+	case AU_SCRIPT:
+		printf("Executing script %s\n", au_image[i].name);
+
+		/* execute a script */
+		if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
+			addr = (char *)((char *)hdr + image_get_header_size ());
+			/* stick a NULL at the end of the script, otherwise */
+			/* parse_string_outer() runs off the end. */
+			addr[image_get_data_size (hdr)] = 0;
+			addr += 8;
+
+			/*
+			 * Replace cr/lf with ;
+			 */
+			k = 0;
+			while (addr[k] != 0) {
+				if ((addr[k] == 10) || (addr[k] == 13)) {
+					addr[k] = ';';
+				}
+				k++;
+			}
+
+			run_command(addr, 0);
+			return 0;
+		}
+
+		break;
+
+	case AU_FIRMWARE:
+	case AU_NOR:
+	case AU_NAND:
+		start = au_image[i].start;
+		end = au_image[i].start + au_image[i].size - 1;
+
+		/*
+		 * do not update firmware when image is already in flash.
+		 */
+		if (au_image[i].type == AU_FIRMWARE) {
+			char *orig = (char*)start;
+			char *new  = (char *)((char *)hdr +
+					      image_get_header_size ());
+			nbytes = image_get_data_size (hdr);
+
+			while (--nbytes) {
+				if (*orig++ != *new++) {
+					break;
+				}
+			}
+			if (!nbytes) {
+				printf ("Skipping firmware update - "
+					"images are identical\n");
+				break;
+			}
+		}
+
+		/* unprotect the address range */
+		if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+		    (au_image[i].type == AU_FIRMWARE)) {
+			flash_sect_protect (0, start, end);
+		}
+
+		/*
+		 * erase the address range.
+		 */
+		if (au_image[i].type != AU_NAND) {
+			printf ("Updating NOR FLASH with image %s\n",
+				au_image[i].name);
+			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+			flash_sect_erase (start, end);
+		}
+
+		udelay(10000);
+
+		/* strip the header - except for the kernel and ramdisk */
+		if (au_image[i].type != AU_FIRMWARE) {
+			addr = (char *)hdr;
+			off = image_get_header_size ();
+			nbytes = image_get_image_size (hdr);
+		} else {
+			addr = (char *)((char *)hdr + image_get_header_size ());
+			off = 0;
+			nbytes = image_get_data_size (hdr);
+		}
+
+		/*
+		 * copy the data from RAM to FLASH
+		 */
+		if (au_image[i].type != AU_NAND) {
+			debug ("flash_write(%p, %lx, %x)\n",
+			       addr, start, nbytes);
+			rc = flash_write ((char *)addr, start,
+					  (nbytes + 1) & ~1);
+		} else {
+			rc = -1;
+		}
+		if (rc != 0) {
+			printf ("Flashing failed due to error %d\n", rc);
+			return -1;
+		}
+
+		/*
+		 * check the dcrc of the copy
+		 */
+		if (au_image[i].type != AU_NAND) {
+			rc = crc32 (0, (uchar *)(start + off),
+				    image_get_data_size (hdr));
+		}
+		if (rc != image_get_dcrc (hdr)) {
+			printf ("Image %s Bad Data Checksum After COPY\n",
+				au_image[i].name);
+			return -1;
+		}
+
+		/* protect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+		    (au_image[i].type == AU_FIRMWARE)) {
+			flash_sect_protect (1, start, end);
+		}
+
+		break;
+
+	default:
+		printf("Wrong image type selected!\n");
+	}
+
+	return 0;
+}
+
+static void process_macros (const char *input, char *output)
+{
+	char c, prev;
+	const char *varname_start = NULL;
+	int inputcnt  = strlen (input);
+	int outputcnt = CONFIG_SYS_CBSIZE;
+	int state = 0;	/* 0 = waiting for '$'	*/
+			/* 1 = waiting for '(' or '{' */
+			/* 2 = waiting for ')' or '}' */
+			/* 3 = waiting for '''  */
+#ifdef DEBUG_PARSER
+	char *output_start = output;
+
+	printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n",
+		strlen(input), input);
+#endif
+
+	prev = '\0';			/* previous character */
+
+	while (inputcnt && outputcnt) {
+	    c = *input++;
+	    inputcnt--;
+
+	    if (state != 3) {
+	    /* remove one level of escape characters */
+	    if ((c == '\\') && (prev != '\\')) {
+		if (inputcnt-- == 0)
+			break;
+		prev = c;
+		c = *input++;
+	    }
+	    }
+
+	    switch (state) {
+	    case 0:			/* Waiting for (unescaped) $ */
+		if ((c == '\'') && (prev != '\\')) {
+			state = 3;
+			break;
+		}
+		if ((c == '$') && (prev != '\\')) {
+			state++;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    case 1:			/* Waiting for ( */
+		if (c == '(' || c == '{') {
+			state++;
+			varname_start = input;
+		} else {
+			state = 0;
+			*(output++) = '$';
+			outputcnt--;
+
+			if (outputcnt) {
+				*(output++) = c;
+				outputcnt--;
+			}
+		}
+		break;
+	    case 2:			/* Waiting for )	*/
+		if (c == ')' || c == '}') {
+			int i;
+			char envname[CONFIG_SYS_CBSIZE], *envval;
+			/* Varname # of chars */
+			int envcnt = input - varname_start - 1;
+
+			/* Get the varname */
+			for (i = 0; i < envcnt; i++) {
+				envname[i] = varname_start[i];
+			}
+			envname[i] = 0;
+
+			/* Get its value */
+			envval = getenv (envname);
+
+			/* Copy into the line if it exists */
+			if (envval != NULL)
+				while ((*envval) && outputcnt) {
+					*(output++) = *(envval++);
+					outputcnt--;
+				}
+			/* Look for another '$' */
+			state = 0;
+		}
+		break;
+	    case 3:			/* Waiting for '	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 0;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    }
+	    prev = c;
+	}
+
+	if (outputcnt)
+		*output = 0;
+
+#ifdef DEBUG_PARSER
+	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
+		strlen (output_start), output_start);
+#endif
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev = NULL;
+	long sz;
+	int i, res, cnt, old_ctrlc;
+	char buffer[32];
+	char str[80];
+	int n;
+
+	if  (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) {
+		stor_dev = get_dev ("ide", 0);
+		if (stor_dev == NULL) {
+			debug ("ide: unknown device\n");
+			return -1;
+		}
+	}
+
+	if (fat_register_device (stor_dev, 1) != 0) {
+		debug ("Unable to register ide disk 0:1\n");
+		return -1;
+	}
+
+	/*
+	 * Check if magic file is present
+	 */
+	if ((n = do_fat_read (AU_MAGIC_FILE, buffer,
+			      sizeof(buffer), LS_NO)) <= 0) {
+		debug ("No auto_update magic file (n=%d)\n", n);
+		return -1;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show (1);
+#endif
+	puts("\nAutoUpdate Disk detected! Trying to update system...\n");
+
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc (0);
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < N_AU_IMAGES; i++) {
+		/*
+		 * Try to expand the environment var in the fname
+		 */
+		process_macros (au_image[i].name, str);
+		strcpy (au_image[i].name, str);
+
+		printf("Reading %s ...", au_image[i].name);
+		/* just read the header */
+		sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+				  image_get_header_size (), LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, image_get_header_size ());
+		if (sz <= 0 || sz < image_get_header_size ()) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_header_valid (i, sz) < 0) {
+			puts(" header not valid\n");
+			continue;
+		}
+		sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+				  MAX_LOADSZ, LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, image_get_header_size ());
+		if (sz <= 0 || sz <= image_get_header_size ()) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_cksum_valid (i, sz) < 0) {
+			puts(" checksum not valid\n");
+			continue;
+		}
+		puts(" done\n");
+
+		do {
+			res = au_do_update (i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc ()) {
+				clear_ctrlc ();
+				break;
+			}
+			cnt++;
+		} while (res < 0);
+	}
+
+	/* restore the old state */
+	disable_ctrlc (old_ctrlc);
+
+	puts("AutoUpdate finished\n\n");
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show (0);
+#endif
+
+	return 0;
+}
+
+int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	do_auto_update();
+
+	return 0;
+}
+U_BOOT_CMD(
+	autoupd,	1,	1,	auto_update,
+	"Automatically update images",
+	""
+);
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/roms/u-boot/board/esd/common/auto_update.h b/roms/u-boot/board/esd/common/auto_update.h
new file mode 100644
index 00000000..be8f439e
--- /dev/null
+++ b/roms/u-boot/board/esd/common/auto_update.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _AUTO_UPDATE_H_
+#define _AUTO_UPDATE_H_
+
+#define MBR_MAGIC       0x07081967
+#define MBR_MAGIC_ADDR  0x100           /* offset 0x100 should be free space */
+
+#define AU_MAGIC_FILE   "__auto_update"
+
+#define AU_TYPEMASK     0x000000ff
+#define AU_FLAGMASK     0xffff0000
+
+#define AU_PROTECT      0x80000000
+
+#define AU_SCRIPT       0x01
+#define AU_FIRMWARE     (0x02 | AU_PROTECT)
+#define AU_NOR          0x03
+#define AU_NAND         0x04
+
+struct au_image_s {
+	char name[80];
+	ulong start;
+	ulong size;
+	ulong type;
+};
+
+typedef struct au_image_s au_image_t;
+
+int do_auto_update(void);
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active);
+#endif
+
+#endif /* #ifndef _AUTO_UPDATE_H_ */
diff --git a/roms/u-boot/board/esd/common/cmd_loadpci.c b/roms/u-boot/board/esd/common/cmd_loadpci.c
new file mode 100644
index 00000000..803179a4
--- /dev/null
+++ b/roms/u-boot/board/esd/common/cmd_loadpci.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
+
+#if defined(CONFIG_CMD_BSP)
+
+extern int do_source (cmd_tbl_t *, int, int, char *[]);
+
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+	u32 la, ptm1la;
+
+#if defined(CONFIG_440)
+	ptm1la = in32r(PCIL0_PTM1LA);
+#else
+	ptm1la = in32r(PTM1LA);
+#endif
+	while(1) {
+		/*
+		 * Mark sync address
+		 */
+		ptr = (u32 *)ptm1la;
+		memset(ptr, 0, 0x20);
+
+		*ptr = 0xffffffff;
+		puts("\nWaiting for action from pci host -");
+
+		/*
+		 * Wait for host to write the start address
+		 */
+		while (*ptr == 0xffffffff) {
+			count++;
+			if (!(count % 100)) {
+				count2++;
+				putc(0x08); /* backspace */
+				putc(str[count2 % 4]);
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			udelay(1000);
+		}
+
+		printf("\nGot bootcode %08x: ", *ptr);
+		la = ptm1la + (*ptr & ADDRMASK);
+		sprintf(addr, "%08x", la);
+
+		switch (*ptr & ~ADDRMASK) {
+		case 0:
+			/*
+			 * Boot image via bootm
+			 */
+			printf("booting image at addr 0x%s ...\n", addr);
+			setenv("loadaddr", addr);
+			do_bootm(cmdtp, 0, 0, NULL);
+			break;
+
+		case 1:
+			/*
+			 * Boot image via "source" command
+			 */
+			printf("executing script at addr 0x%s ...\n", addr);
+			local_args[0] = addr;
+			local_args[1] = NULL;
+			do_source(cmdtp, 0, 1, local_args);
+			break;
+
+		case 2:
+			/*
+			 * Call run_cmd
+			 */
+			printf("running command at addr 0x%s ...\n", addr);
+			run_command((char *)la, 0);
+			break;
+
+		default:
+			printf("unhandled boot method\n");
+			break;
+		}
+	}
+}
+
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"Wait for pci bootcmd and boot it",
+	""
+);
+
+#endif
diff --git a/roms/u-boot/board/esd/common/esd405ep_nand.c b/roms/u-boot/board/esd/common/esd405ep_nand.c
new file mode 100644
index 00000000..f46936ca
--- /dev/null
+++ b/roms/u-boot/board/esd/common/esd405ep_nand.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
+		if ( ctrl & NAND_ALE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
+		if ( ctrl & NAND_NCE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+	if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
+		return 1;
+	return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+	/*
+	 * Set NAND-FLASH GPIO signals to defaults
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Initialize nand_chip structure
+	 */
+	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
+	nand->dev_ready = esd405ep_nand_device_ready;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->chip_delay = NAND_BIG_DELAY_US;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/esd/common/flash.c b/roms/u-boot/board/esd/common/flash.c
new file mode 100644
index 00000000..e3512c78
--- /dev/null
+++ b/roms/u-boot/board/esd/common/flash.c
@@ -0,0 +1,659 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#ifdef __PPC__
+#include <asm/ppc4xx.h>
+#endif
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST320:	printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST640:	printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CONFIG_SYS_FLASH_READ0];
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
+		info->flash_id += FLASH_SST320;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
+		info->flash_id += FLASH_SST640;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong *data_ptr = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/roms/u-boot/board/esd/common/fpga.c b/roms/u-boot/board/esd/common/fpga.c
new file mode 100644
index 00000000..5c70b474
--- /dev/null
+++ b/roms/u-boot/board/esd/common/fpga.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK	/* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA	/* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE	/* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT	/* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000	/* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000	/* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000	/* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000	/* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1	/* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2	/* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3	/* Timeout after programming     */
+
+#ifndef SET_FPGA
+# define SET_FPGA(data)         out_be32((void *)GPIO0_OR, data)
+#endif
+
+#ifdef FPGA_PROG_ACTIVE_HIGH
+# define FPGA_PRG_LOW           FPGA_PRG
+# define FPGA_PRG_HIGH          0
+#else
+# define FPGA_PRG_LOW           0
+# define FPGA_PRG_HIGH          FPGA_PRG
+#endif
+
+#define FPGA_CLK_LOW            0
+#define FPGA_CLK_HIGH           FPGA_CLK
+
+#define FPGA_DATA_LOW           0
+#define FPGA_DATA_HIGH          FPGA_DATA
+
+#define FPGA_WRITE_1 {                                                                   \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_LOW);   /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW);   /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
+
+#ifndef FPGA_DONE_STATE
+# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
+#endif
+#ifndef FPGA_INIT_STATE
+# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
+#endif
+
+
+static int fpga_boot (const unsigned char *fpgadata, int size)
+{
+	int i, index, len;
+	int count;
+	unsigned char b;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	int j;
+#else
+	int bit;
+#endif
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+#ifndef CONFIG_M5249
+	out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+	/* setup for output */
+	out_be32 ((void *)GPIO0_TCR,
+		  in_be32 ((void *)GPIO0_TCR) |
+		  FPGA_PRG | FPGA_CLK | FPGA_DATA);
+#endif
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set pins to high */
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog active */
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (FPGA_INIT_STATE) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog inactive */
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(FPGA_INIT_STATE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	DBG ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((b & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			b <<= 1;
+		}
+	}
+#else
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif
+
+	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(FPGA_DONE_STATE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG ("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/common/lcd.c b/roms/u-boot/board/esd/common/lcd.c
new file mode 100644
index 00000000..22a59e44
--- /dev/null
+++ b/roms/u-boot/board/esd/common/lcd.c
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "asm/io.h"
+#include "lcd.h"
+
+
+extern int video_display_bitmap (ulong, int, int);
+
+
+int palette_index;
+int palette_value;
+int lcd_depth;
+unsigned char *glob_lcd_reg;
+unsigned char *glob_lcd_mem;
+
+#if defined(CONFIG_SYS_LCD_ENDIAN)
+void lcd_setup(int lcd, int config)
+{
+	if (lcd == 0) {
+		/*
+		 * Set endianess and reset lcd controller 0 (small)
+		 */
+
+		/* set reset to low */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			/* big-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+		} else {
+			/* little-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+		}
+		udelay(10); /* wait 10us */
+		/* set reset to high */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
+	} else {
+		/*
+		 * Set endianess and reset lcd controller 1 (big)
+		 */
+
+		/* set reset to low */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			/* big-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+		} else {
+			/* little-endian */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+		}
+		udelay(10); /* wait 10us */
+		/* set reset to high */
+		out_be32((void*)GPIO0_OR,
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
+	}
+
+	/*
+	 * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+}
+#endif /* CONFIG_SYS_LCD_ENDIAN */
+
+
+int lcd_bmp(uchar *logo_bmp)
+{
+	int i;
+	uchar *ptr;
+	ushort *ptr2;
+	ushort val;
+	unsigned char *dst = NULL;
+	int x, y;
+	int width, height, bpp, colors, line_size;
+	int header_size;
+	unsigned char *bmp;
+	unsigned char r, g, b;
+	BITMAPINFOHEADER *bm_info;
+	ulong len;
+
+	/*
+	 * Check for bmp mark 'BM'
+	 */
+	if (*(ushort *)logo_bmp != 0x424d) {
+		/*
+		 * Decompress bmp image
+		 */
+		len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+		dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
+		if (dst == NULL) {
+			printf("Error: malloc for gunzip failed!\n");
+			return 1;
+		}
+		if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+			   (uchar *)logo_bmp, &len) != 0) {
+			free(dst);
+			return 1;
+		}
+		if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
+			printf("Image could be truncated"
+			       " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
+		}
+
+		/*
+		 * Check for bmp mark 'BM'
+		 */
+		if (*(ushort *)dst != 0x424d) {
+			printf("LCD: Unknown image format!\n");
+			free(dst);
+			return 1;
+		}
+	} else {
+		/*
+		 * Uncompressed BMP image, just use this pointer
+		 */
+		dst = (uchar *)logo_bmp;
+	}
+
+	/*
+	 * Get image info from bmp-header
+	 */
+	bm_info = (BITMAPINFOHEADER *)(dst + 14);
+	bpp = LOAD_SHORT(bm_info->biBitCount);
+	width = LOAD_LONG(bm_info->biWidth);
+	height = LOAD_LONG(bm_info->biHeight);
+	switch (bpp) {
+	case 1:
+		colors = 1;
+		line_size = width >> 3;
+		break;
+	case 4:
+		colors = 16;
+		line_size = width >> 1;
+		break;
+	case 8:
+		colors = 256;
+		line_size = width;
+		break;
+	case 24:
+		colors = 0;
+		line_size = width * 3;
+		break;
+	default:
+		printf("LCD: Unknown bpp (%d) im image!\n", bpp);
+		if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+			free(dst);
+		return 1;
+	}
+	printf(" (%d*%d, %dbpp)\n", width, height, bpp);
+
+	/*
+	 * Write color palette
+	 */
+	if ((colors <= 256) && (lcd_depth <= 8)) {
+		ptr = (unsigned char *)(dst + 14 + 40);
+		for (i = 0; i < colors; i++) {
+			b = *ptr++;
+			g = *ptr++;
+			r = *ptr++;
+			ptr++;
+			S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
+		}
+	}
+
+	/*
+	 * Write bitmap data into framebuffer
+	 */
+	ptr = glob_lcd_mem;
+	ptr2 = (ushort *)glob_lcd_mem;
+	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
+	for (y = 0; y < height; y++) {
+		bmp = &dst[(height-1-y)*line_size + header_size];
+		if (lcd_depth == 16) {
+			if (bpp == 24) {
+				for (x = 0; x < width; x++) {
+					/*
+					 * Generate epson 16bpp fb-format
+					 * from 24bpp image
+					 */
+					b = *bmp++ >> 3;
+					g = *bmp++ >> 2;
+					r = *bmp++ >> 3;
+					val = ((r & 0x1f) << 11) |
+						((g & 0x3f) << 5) |
+						(b & 0x1f);
+					*ptr2++ = val;
+				}
+			} else if (bpp == 8) {
+				for (x = 0; x < line_size; x++) {
+					/* query rgb value from palette */
+					ptr = (unsigned char *)(dst + 14 + 40);
+					ptr += (*bmp++) << 2;
+					b = *ptr++ >> 3;
+					g = *ptr++ >> 2;
+					r = *ptr++ >> 3;
+					val = ((r & 0x1f) << 11) |
+						((g & 0x3f) << 5) |
+						(b & 0x1f);
+					*ptr2++ = val;
+				}
+			}
+		} else {
+			for (x = 0; x < line_size; x++)
+				*ptr++ = *bmp++;
+		}
+	}
+
+	if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+		free(dst);
+	return 0;
+}
+
+
+int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+	     uchar *logo_bmp, ulong len)
+{
+	int i;
+	ushort s1dReg;
+	uchar s1dValue;
+	int reg_byte_swap;
+
+	/*
+	 * Detect epson
+	 */
+	out_8(&lcd_reg[0], 0x00);
+	out_8(&lcd_reg[1], 0x00);
+
+	if (in_8(&lcd_reg[0]) == 0x1c) {
+		/*
+		 * Big epson detected
+		 */
+		reg_byte_swap = false;
+		palette_index = 0x1e2;
+		palette_value = 0x1e4;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806");
+	} else if (in_8(&lcd_reg[1]) == 0x1c) {
+		/*
+		 * Big epson detected (with register swap bug)
+		 */
+		reg_byte_swap = true;
+		palette_index = 0x1e3;
+		palette_value = 0x1e5;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806S");
+	} else if (in_8(&lcd_reg[0]) == 0x18) {
+		/*
+		 * Small epson detected (704)
+		 */
+		reg_byte_swap = false;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		puts("LCD:   S1D13704");
+	} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
+		/*
+		 * Small epson detected (705)
+		 */
+		reg_byte_swap = false;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		lcd_reg += 0x10000; /* add offset for 705 regs */
+		puts("LCD:   S1D13705");
+	} else {
+		out_8(&lcd_reg[0x1a], 0x00);
+		udelay(1000);
+		if (in_8(&lcd_reg[1]) == 0x0c) {
+			/*
+			 * S1D13505 detected
+			 */
+			reg_byte_swap = true;
+			palette_index = 0x25;
+			palette_value = 0x27;
+			lcd_depth = 16;
+
+			puts("LCD:   S1D13505");
+		} else {
+			puts("LCD:   No controller detected!\n");
+			return 1;
+		}
+	}
+
+	/*
+	 * Setup lcd controller regs
+	 */
+	for (i = 0; i < reg_count; i++) {
+		s1dReg = regs[i].Index;
+		if (reg_byte_swap) {
+			if ((s1dReg & 0x0001) == 0)
+				s1dReg |= 0x0001;
+			else
+				s1dReg &= ~0x0001;
+		}
+		s1dValue = regs[i].Value;
+		out_8(&lcd_reg[s1dReg], s1dValue);
+	}
+
+	/*
+	 * Save reg & mem pointer for later usage (e.g. bmp command)
+	 */
+	glob_lcd_reg = lcd_reg;
+	glob_lcd_mem = lcd_mem;
+
+	/*
+	 * Display bmp image
+	 */
+	return lcd_bmp(logo_bmp);
+}
+
+int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+#ifdef CONFIG_VIDEO_SM501
+	char *str;
+#endif
+	if (argc != 2)
+		return cmd_usage(cmdtp);
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+#ifdef CONFIG_VIDEO_SM501
+	str = getenv("bd_type");
+	if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
+		/*
+		 * SM501 available, use standard bmp command
+		 */
+		return video_display_bitmap(addr, 0, 0);
+	} else {
+		/*
+		 * No SM501 available, use esd epson bmp command
+		 */
+		return lcd_bmp((uchar *)addr);
+	}
+#else
+	return lcd_bmp((uchar *)addr);
+#endif
+}
+
+U_BOOT_CMD(
+	esdbmp,	2,	1,	do_esdbmp,
+	"display BMP image",
+	"<imageAddr> - display image"
+);
diff --git a/roms/u-boot/board/esd/common/lcd.h b/roms/u-boot/board/esd/common/lcd.h
new file mode 100644
index 00000000..5b14bf92
--- /dev/null
+++ b/roms/u-boot/board/esd/common/lcd.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Neutralize little endians.
+ */
+#define SWAP_LONG(data) ((unsigned long)                                  \
+			 (((unsigned long)(data) >> 24)                 | \
+			  ((unsigned long)(data)  << 24)                | \
+			  (((unsigned long)(data) >> 8) & 0x0000ff00 )  | \
+			   (((unsigned long)(data) << 8) & 0x00ff0000 )))
+#define SWAP_SHORT(data) ((unsigned short)                                \
+			  (((unsigned short)(data) >> 8 )  |              \
+			   ((unsigned short)(data) << 8 )))
+#define LOAD_LONG(data)   SWAP_LONG(data)
+#define LOAD_SHORT(data)  SWAP_SHORT(data)
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)					\
+	{								\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(i));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(r));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(g));	\
+		out_8(&((uchar*)(p))[palette_index], (uchar)(b));	\
+	}
+
+typedef struct
+{
+    ushort Index;
+    uchar  Value;
+} S1D_REGS;
+
+typedef struct                       /**** BMP file info structure ****/
+{
+	unsigned int   biSize;           /* Size of info header */
+	int            biWidth;          /* Width of image */
+	int            biHeight;         /* Height of image */
+	unsigned short biPlanes;         /* Number of color planes */
+	unsigned short biBitCount;       /* Number of bits per pixel */
+	unsigned int   biCompression;    /* Type of compression to use */
+	unsigned int   biSizeImage;      /* Size of image data */
+	int            biXPelsPerMeter;  /* X pixels per meter */
+	int            biYPelsPerMeter;  /* Y pixels per meter */
+	unsigned int   biClrUsed;        /* Number of colors used */
+	unsigned int   biClrImportant;   /* Number of important colors */
+} BITMAPINFOHEADER;
diff --git a/roms/u-boot/board/esd/common/misc.c b/roms/u-boot/board/esd/common/misc.c
new file mode 100644
index 00000000..79cd6127
--- /dev/null
+++ b/roms/u-boot/board/esd/common/misc.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+	unsigned short reg;
+
+	miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
+	reg &= ~0x0040;                  /* disable sleep mode */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/roms/u-boot/board/esd/common/pci.c b/roms/u-boot/board/esd/common/pci.c
new file mode 100644
index 00000000..faebdb18
--- /dev/null
+++ b/roms/u-boot/board/esd/common/pci.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+				 CONFIG_SYS_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init_board(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/roms/u-boot/board/esd/common/s1d13505_640_480_16bpp.h b/roms/u-boot/board/esd/common/s1d13505_640_480_16bpp.h
new file mode 100644
index 00000000..ca11683a
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13505_640_480_16bpp.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Panel:  640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
+ * Memory:  DRAM (MCLK=40.000 MHz)
+ */
+static S1D_REGS regs_13505_640_480_16bpp[] =
+{
+	{0x1B,0x00},   /* Miscellaneous Register */
+	{0x23,0x20},   /* Performance Enhancement Register 1 */
+	{0x01,0x30},   /* Memory Configuration Register */
+	{0x22,0x24},   /* Performance Enhancement Register 0 */
+	{0x02,0x25},   /* Panel Type Register */
+	{0x03,0x00},   /* MOD Rate Register */
+	{0x04,0x4F},   /* Horizontal Display Width Register */
+	{0x05,0x0c},   /* Horizontal Non-Display Period Register */
+	{0x06,0x00},   /* HRTC/FPLINE Start Position Register */
+	{0x07,0x01},   /* HRTC/FPLINE Pulse Width Register */
+	{0x08,0xDF},   /* Vertical Display Height Register 0 */
+	{0x09,0x01},   /* Vertical Display Height Register 1 */
+	{0x0A,0x3E},   /* Vertical Non-Display Period Register */
+	{0x0B,0x00},   /* VRTC/FPFRAME Start Position Register */
+	{0x0C,0x01},   /* VRTC/FPFRAME Pulse Width Register */
+	{0x0E,0xFF},   /* Screen 1 Line Compare Register 0 */
+	{0x0F,0x03},   /* Screen 1 Line Compare Register 1 */
+	{0x10,0x00},   /* Screen 1 Display Start Address Register 0 */
+	{0x11,0x00},   /* Screen 1 Display Start Address Register 1 */
+	{0x12,0x00},   /* Screen 1 Display Start Address Register 2 */
+	{0x13,0x00},   /* Screen 2 Display Start Address Register 0 */
+	{0x14,0x00},   /* Screen 2 Display Start Address Register 1 */
+	{0x15,0x00},   /* Screen 2 Display Start Address Register 2 */
+	{0x16,0x80},   /* Memory Address Offset Register 0 */
+	{0x17,0x02},   /* Memory Address Offset Register 1 */
+	{0x18,0x00},   /* Pixel Panning Register */
+	{0x19,0x01},   /* Clock Configuration Register */
+	{0x1A,0x00},   /* Power Save Configuration Register */
+	{0x1C,0x00},   /* MD Configuration Readback Register 0 */
+	{0x1E,0x06},   /* General IO Pins Configuration Register 0 */
+	{0x1F,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x20,0x00},   /* General IO Pins Control Register 0 */
+	{0x21,0x00},   /* General IO Pins Control Register 1 */
+	{0x23,0x20},   /* Performance Enhancement Register 1 */
+	{0x0D,0x15},   /* Display Mode Register */
+};
diff --git a/roms/u-boot/board/esd/common/s1d13704_320_240_4bpp.h b/roms/u-boot/board/esd/common/s1d13704_320_240_4bpp.h
new file mode 100644
index 00000000..bd910e8b
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13704_320_240_4bpp.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13704_320_240_4bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x04 }, /*00*/      /* Mode Register 0 Register */
+	{ 0x02,             0xA4 }, /*a0*/      /* Mode Register 1 Register */
+	{ 0x03,             0x83 }, /*03*/      /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x00 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xA0 },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/roms/u-boot/board/esd/common/s1d13705_320_240_8bpp.h b/roms/u-boot/board/esd/common/s1d13705_320_240_8bpp.h
new file mode 100644
index 00000000..041b4a93
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13705_320_240_8bpp.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13705_320_240_8bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x23 },       /* Mode Register 0 Register */
+	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
+	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xFF },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/roms/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h b/roms/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h
new file mode 100644
index 00000000..615fa33a
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13806_1024_768_8bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_1024_768_8bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x00},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x55},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x7F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/roms/u-boot/board/esd/common/s1d13806_320_240_4bpp.h b/roms/u-boot/board/esd/common/s1d13806_320_240_4bpp.h
new file mode 100644
index 00000000..2531f474
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13806_320_240_4bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_320_240_4bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x08},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x08},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x08},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x32},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x00},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x27},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x03},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xEF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x00},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x02},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x50},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x00},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/roms/u-boot/board/esd/common/s1d13806_640_480_16bpp.h b/roms/u-boot/board/esd/common/s1d13806_640_480_16bpp.h
new file mode 100644
index 00000000..38fc1a7e
--- /dev/null
+++ b/roms/u-boot/board/esd/common/s1d13806_640_480_16bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_640_480_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x05},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/lenval.c b/roms/u-boot/board/esd/common/xilinx_jtag/lenval.c
new file mode 100644
index 00000000..5405efbc
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/lenval.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: lenval.c                                      */
+/* abstract:  This file contains routines for using    */
+/*            the lenVal data structure.               */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "lenval.h"
+#include "ports.h"
+
+
+/*****************************************************************************
+ * Function:     value
+ * Description:  Extract the long value from the lenval array.
+ * Parameters:   plvValue    - ptr to lenval.
+ * Returns:      long        - the extracted value.
+ *****************************************************************************/
+long value( lenVal*     plvValue )
+{
+	long    lValue;         /* result to hold the accumulated result */
+	short   sIndex;
+
+	lValue  = 0;
+	for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
+	{
+		lValue <<= 8;                       /* shift the accumulated result */
+		lValue |= plvValue->val[ sIndex];   /* get the last byte first */
+	}
+
+	return( lValue );
+}
+
+/*****************************************************************************
+ * Function:     initLenVal
+ * Description:  Initialize the lenval array with the given value.
+ *               Assumes lValue is less than 256.
+ * Parameters:   plv         - ptr to lenval.
+ *               lValue      - the value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void initLenVal( lenVal*    plv,
+		 long       lValue )
+{
+	plv->len    = 1;
+	plv->val[0] = (unsigned char)lValue;
+}
+
+/*****************************************************************************
+ * Function:     EqualLenVal
+ * Description:  Compare two lenval arrays with an optional mask.
+ * Parameters:   plvTdoExpected  - ptr to lenval #1.
+ *               plvTdoCaptured  - ptr to lenval #2.
+ *               plvTdoMask      - optional ptr to mask (=0 if no mask).
+ * Returns:      short   - 0 = mismatch; 1 = equal.
+ *****************************************************************************/
+short EqualLenVal( lenVal*  plvTdoExpected,
+		   lenVal*  plvTdoCaptured,
+		   lenVal*  plvTdoMask )
+{
+	short           sEqual;
+	short           sIndex;
+	unsigned char   ucByteVal1;
+	unsigned char   ucByteVal2;
+	unsigned char   ucByteMask;
+
+	sEqual  = 1;
+	sIndex  = plvTdoExpected->len;
+
+	while ( sEqual && sIndex-- )
+	{
+		ucByteVal1  = plvTdoExpected->val[ sIndex ];
+		ucByteVal2  = plvTdoCaptured->val[ sIndex ];
+		if ( plvTdoMask )
+		{
+			ucByteMask  = plvTdoMask->val[ sIndex ];
+			ucByteVal1  &= ucByteMask;
+			ucByteVal2  &= ucByteMask;
+		}
+		if ( ucByteVal1 != ucByteVal2 )
+		{
+			sEqual  = 0;
+		}
+	}
+
+	return( sEqual );
+}
+
+
+/*****************************************************************************
+ * Function:     RetBit
+ * Description:  return the (byte, bit) of lv (reading from left to right).
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb)
+ * Returns:      short   - the bit value.
+ *****************************************************************************/
+short RetBit( lenVal*   plv,
+	      int       iByte,
+	      int       iBit )
+{
+	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
+	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
+	return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
+}
+
+/*****************************************************************************
+ * Function:     SetBit
+ * Description:  set the (byte, bit) of lv equal to val
+ * Example:      SetBit("00000000",byte, 1) equals "01000000".
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb).
+ *               sVal    - the bit value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void SetBit( lenVal*    plv,
+	     int        iByte,
+	     int        iBit,
+	     short      sVal )
+{
+	unsigned char   ucByteVal;
+	unsigned char   ucBitMask;
+
+	ucBitMask   = (unsigned char)(1 << ( 7 - iBit ));
+	ucByteVal   = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
+
+	if ( sVal )
+	{
+		ucByteVal   |= ucBitMask;
+	}
+	plv->val[ iByte ]   = ucByteVal;
+}
+
+/*****************************************************************************
+ * Function:     AddVal
+ * Description:  add val1 to val2 and store in resVal;
+ *               assumes val1 and val2  are of equal length.
+ * Parameters:   plvResVal   - ptr to result.
+ *               plvVal1     - ptr of addendum.
+ *               plvVal2     - ptr of addendum.
+ * Returns:      void.
+ *****************************************************************************/
+void addVal( lenVal*    plvResVal,
+	     lenVal*    plvVal1,
+	     lenVal*    plvVal2 )
+{
+	unsigned char   ucCarry;
+	unsigned short  usSum;
+	unsigned short  usVal1;
+	unsigned short  usVal2;
+	short           sIndex;
+
+	plvResVal->len  = plvVal1->len;         /* set up length of result */
+
+	/* start at least significant bit and add bytes    */
+	ucCarry = 0;
+	sIndex  = plvVal1->len;
+	while ( sIndex-- )
+	{
+		usVal1  = plvVal1->val[ sIndex ];   /* i'th byte of val1 */
+		usVal2  = plvVal2->val[ sIndex ];   /* i'th byte of val2 */
+
+		/* add the two bytes plus carry from previous addition */
+		usSum   = (unsigned short)( usVal1 + usVal2 + ucCarry );
+
+		/* set up carry for next byte */
+		ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
+
+		/* set the i'th byte of the result */
+		plvResVal->val[ sIndex ]    = (unsigned char)usSum;
+	}
+}
+
+/*****************************************************************************
+ * Function:     readVal
+ * Description:  read from XSVF numBytes bytes of data into x.
+ * Parameters:   plv         - ptr to lenval in which to put the bytes read.
+ *               sNumBytes   - the number of bytes to read.
+ * Returns:      void.
+ *****************************************************************************/
+void readVal( lenVal*   plv,
+	      short     sNumBytes )
+{
+	unsigned char*  pucVal;
+
+	plv->len    = sNumBytes;        /* set the length of the lenVal        */
+	for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
+	{
+		/* read a byte of data into the lenVal */
+		readByte( pucVal );
+	}
+}
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/lenval.h b/roms/u-boot/board/esd/common/xilinx_jtag/lenval.h
new file mode 100644
index 00000000..3273eec4
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/lenval.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: lenval.h                                      */
+/* abstract:  This file contains a description of the  */
+/*            data structure "lenval".                 */
+/*******************************************************/
+
+#ifndef lenval_dot_h
+#define lenval_dot_h
+
+/* the lenVal structure is a byte oriented type used to store an */
+/* arbitrary length binary value. As an example, the hex value   */
+/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes   */
+/* and val[0]=0e and val[1]=3d.  val[2-MAX_LEN] are undefined    */
+
+/* maximum length (in bytes) of value to read in        */
+/* this needs to be at least 4, and longer than the     */
+/* length of the longest SDR instruction.  If there is, */
+/* only 1 device in the chain, MAX_LEN must be at least */
+/* ceil(27/8) == 4.  For 6 devices in a chain, MAX_LEN  */
+/* must be 5, for 14 devices MAX_LEN must be 6, for 20  */
+/* devices MAX_LEN must be 7, etc..                     */
+/* You can safely set MAX_LEN to a smaller number if you*/
+/* know how many devices will be in your chain.         */
+#define MAX_LEN 7000
+
+
+typedef struct var_len_byte
+{
+	short len;   /* number of chars in this value */
+	unsigned char val[MAX_LEN+1];  /* bytes of data */
+} lenVal;
+
+
+/* return the long representation of a lenVal */
+extern long value(lenVal *x);
+
+/* set lenVal equal to value */
+extern void initLenVal(lenVal *x, long value);
+
+/* check if expected equals actual (taking the mask into account) */
+extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
+
+/* add val1+val2 and put the result in resVal */
+extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
+
+/* return the (byte, bit) of lv (reading from left to right) */
+extern short RetBit(lenVal *lv, int byte, int bit);
+
+/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
+   equals "01000000" */
+extern void SetBit(lenVal *lv, int byte, int bit, short val);
+
+/* read from XSVF numBytes bytes of data into x */
+extern void  readVal(lenVal *x, short numBytes);
+
+#endif
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/micro.c b/roms/u-boot/board/esd/common/xilinx_jtag/micro.c
new file mode 100644
index 00000000..556636c5
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/micro.c
@@ -0,0 +1,1854 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*****************************************************************************
+ * file:         micro.c
+ * abstract:     This file contains the function, xsvfExecute(),
+ *               call for interpreting the XSVF commands.
+ * Usage:        Call xsvfExecute() to process XSVF data.
+ *               The XSVF data is retrieved by readByte() in ports.c
+ *               Remove the main function if you already have one.
+ * Options:      XSVF_SUPPORT_COMPRESSION
+ *                   This define supports the XC9500/XL compression scheme.
+ *                   This define adds support for XSDRINC and XSETSDRMASKS.
+ *               XSVF_SUPPORT_ERRORCODES
+ *                   This define causes the xsvfExecute function to return
+ *                   an error code for specific errors.  See error codes below.
+ *                   If this is not defined, the return value defaults to the
+ *                   legacy values for backward compatibility:
+ *                   1 = success;  0 = failure.
+ * Debugging:    DEBUG_MODE (Legacy name)
+ *               Define DEBUG_MODE to compile with debugging features.
+ *               Both micro.c and ports.c must be compiled with the DEBUG_MODE
+ *               defined to enable the standalone main implementation in
+ *               micro.c that reads XSVF from a file.
+ * History:      v2.00   - Original XSVF implementation.
+ *               v4.04   - Added delay at end of XSIR for XC18v00 support.
+ *                         Added new commands for CoolRunner support:
+ *                         XSTATE, XENDIR, XENDDR
+ *               v4.05   - Cleanup micro.c but leave ports.c intact.
+ *               v4.06   - Fix xsvfGotoTapState for retry transition.
+ *               v4.07   - Update example waitTime implementations for
+ *                         compatibility with Virtex-II.
+ *               v4.10   - Add new XSIR2 command that supports a 2-byte
+ *                         IR-length parameter for IR shifts > 255 bits.
+ *               v4.11   - No change.  Update version to match SVF2XSVF xlator.
+ *               v4.14   - Added XCOMMENT.
+ *               v5.00   - Improve XSTATE support.
+ *                         Added XWAIT.
+ *****************************************************************************/
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "micro.h"
+#include "lenval.h"
+#include "ports.h"
+
+const unsigned char *xsvfdata;
+
+/*============================================================================
+ * XSVF #define
+ ============================================================================*/
+
+#define XSVF_VERSION    "5.00"
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_COMPRESSION
+ * Description:  Define this to support the XC9500/XL XSVF data compression
+ *               scheme.
+ *               Code size can be reduced by NOT supporting this feature.
+ *               However, you must use the -nc (no compress) option when
+ *               translating SVF to XSVF using the SVF2XSVF translator.
+ *               Corresponding, uncompressed XSVF may be larger.
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_COMPRESSION
+#define XSVF_SUPPORT_COMPRESSION    1
+#endif
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_ERRORCODES
+ * Description:  Define this to support the new XSVF error codes.
+ *               (The original XSVF player just returned 1 for success and
+ *               0 for an unspecified failure.)
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_ERRORCODES
+#define XSVF_SUPPORT_ERRORCODES     1
+#endif
+
+#ifdef  XSVF_SUPPORT_ERRORCODES
+#define XSVF_ERRORCODE(errorCode)   errorCode
+#else   /* Use legacy error code */
+#define XSVF_ERRORCODE(errorCode)   ((errorCode==XSVF_ERROR_NONE)?1:0)
+#endif  /* XSVF_SUPPORT_ERRORCODES */
+
+
+/*============================================================================
+ * DEBUG_MODE #define
+ ============================================================================*/
+#define DEBUG_MODE
+
+#ifdef  DEBUG_MODE
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat ); }
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1 ); }
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2 ); }
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2, arg3 ); }
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    xsvfPrintLenVal(plenVal); }
+#else   /* !DEBUG_MODE */
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
+#endif  /* DEBUG_MODE */
+
+
+/*============================================================================
+ * XSVF Type Declarations
+ ============================================================================*/
+
+/*****************************************************************************
+ * Struct:       SXsvfInfo
+ * Description:  This structure contains all of the data used during the
+ *               execution of the XSVF.  Some data is persistent, predefined
+ *               information (e.g. lRunTestTime).  The bulk of this struct's
+ *               size is due to the lenVal structs (defined in lenval.h)
+ *               which contain buffers for the active shift data.  The MAX_LEN
+ *               #define in lenval.h defines the size of these buffers.
+ *               These buffers must be large enough to store the longest
+ *               shift data in your XSVF file.  For example:
+ *                   MAX_LEN >= ( longest_shift_data_in_bits / 8 )
+ *               Because the lenVal struct dominates the space usage of this
+ *               struct, the rough size of this struct is:
+ *                   sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
+ *               xsvfInitialize() contains initialization code for the data
+ *               in this struct.
+ *               xsvfCleanup() contains cleanup code for the data in this
+ *               struct.
+ *****************************************************************************/
+typedef struct tagSXsvfInfo
+{
+	/* XSVF status information */
+	unsigned char   ucComplete;         /* 0 = running; 1 = complete */
+	unsigned char   ucCommand;          /* Current XSVF command byte */
+	long            lCommandCount;      /* Number of commands processed */
+	int             iErrorCode;         /* An error code. 0 = no error. */
+
+	/* TAP state/sequencing information */
+	unsigned char   ucTapState;         /* Current TAP state */
+	unsigned char   ucEndIR;            /* ENDIR TAP state (See SVF) */
+	unsigned char   ucEndDR;            /* ENDDR TAP state (See SVF) */
+
+	/* RUNTEST information */
+	unsigned char   ucMaxRepeat;        /* Max repeat loops (for xc9500/xl) */
+	long            lRunTestTime;       /* Pre-specified RUNTEST time (usec) */
+
+	/* Shift Data Info and Buffers */
+	long            lShiftLengthBits;   /* Len. current shift data in bits */
+	short           sShiftLengthBytes;  /* Len. current shift data in bytes */
+
+	lenVal          lvTdi;              /* Current TDI shift data */
+	lenVal          lvTdoExpected;      /* Expected TDO shift data */
+	lenVal          lvTdoCaptured;      /* Captured TDO shift data */
+	lenVal          lvTdoMask;          /* TDO mask: 0=dontcare; 1=compare */
+
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	/* XSDRINC Data Buffers */
+	lenVal          lvAddressMask;      /* Address mask for XSDRINC */
+	lenVal          lvDataMask;         /* Data mask for XSDRINC */
+	lenVal          lvNextData;         /* Next data for XSDRINC */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+} SXsvfInfo;
+
+/* Declare pointer to functions that perform XSVF commands */
+typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
+
+/*============================================================================
+ * XSVF Command Bytes
+ ============================================================================*/
+
+/* encodings of xsvf instructions */
+#define XCOMPLETE        0
+#define XTDOMASK         1
+#define XSIR             2
+#define XSDR             3
+#define XRUNTEST         4
+/* Reserved              5 */
+/* Reserved              6 */
+#define XREPEAT          7
+#define XSDRSIZE         8
+#define XSDRTDO          9
+#define XSETSDRMASKS     10
+#define XSDRINC          11
+#define XSDRB            12
+#define XSDRC            13
+#define XSDRE            14
+#define XSDRTDOB         15
+#define XSDRTDOC         16
+#define XSDRTDOE         17
+#define XSTATE           18         /* 4.00 */
+#define XENDIR           19         /* 4.04 */
+#define XENDDR           20         /* 4.04 */
+#define XSIR2            21         /* 4.10 */
+#define XCOMMENT         22         /* 4.14 */
+#define XWAIT            23         /* 5.00 */
+/* Insert new commands here */
+/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
+#define XLASTCMD         24         /* Last command marker */
+
+
+/*============================================================================
+ * XSVF Command Parameter Values
+ ============================================================================*/
+
+#define XSTATE_RESET     0          /* 4.00 parameter for XSTATE */
+#define XSTATE_RUNTEST   1          /* 4.00 parameter for XSTATE */
+
+#define XENDXR_RUNTEST   0          /* 4.04 parameter for XENDIR/DR */
+#define XENDXR_PAUSE     1          /* 4.04 parameter for XENDIR/DR */
+
+/* TAP states */
+#define XTAPSTATE_RESET     0x00
+#define XTAPSTATE_RUNTEST   0x01    /* a.k.a. IDLE */
+#define XTAPSTATE_SELECTDR  0x02
+#define XTAPSTATE_CAPTUREDR 0x03
+#define XTAPSTATE_SHIFTDR   0x04
+#define XTAPSTATE_EXIT1DR   0x05
+#define XTAPSTATE_PAUSEDR   0x06
+#define XTAPSTATE_EXIT2DR   0x07
+#define XTAPSTATE_UPDATEDR  0x08
+#define XTAPSTATE_IRSTATES  0x09    /* All IR states begin here */
+#define XTAPSTATE_SELECTIR  0x09
+#define XTAPSTATE_CAPTUREIR 0x0A
+#define XTAPSTATE_SHIFTIR   0x0B
+#define XTAPSTATE_EXIT1IR   0x0C
+#define XTAPSTATE_PAUSEIR   0x0D
+#define XTAPSTATE_EXIT2IR   0x0E
+#define XTAPSTATE_UPDATEIR  0x0F
+
+/*============================================================================
+ * XSVF Function Prototypes
+ ============================================================================*/
+
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo );   /* Illegal command function */
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
+/* Insert new command functions here */
+
+/*============================================================================
+ * XSVF Global Variables
+ ============================================================================*/
+
+/* Array of XSVF command functions.  Must follow command byte value order! */
+/* If your compiler cannot take this form, then convert to a switch statement*/
+TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
+{
+	xsvfDoXCOMPLETE,        /*  0 */
+	xsvfDoXTDOMASK,         /*  1 */
+	xsvfDoXSIR,             /*  2 */
+	xsvfDoXSDR,             /*  3 */
+	xsvfDoXRUNTEST,         /*  4 */
+	xsvfDoIllegalCmd,       /*  5 */
+	xsvfDoIllegalCmd,       /*  6 */
+	xsvfDoXREPEAT,          /*  7 */
+	xsvfDoXSDRSIZE,         /*  8 */
+	xsvfDoXSDRTDO,          /*  9 */
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	xsvfDoXSETSDRMASKS,     /* 10 */
+	xsvfDoXSDRINC,          /* 11 */
+#else
+	xsvfDoIllegalCmd,       /* 10 */
+	xsvfDoIllegalCmd,       /* 11 */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+	xsvfDoXSDRBCE,          /* 12 */
+	xsvfDoXSDRBCE,          /* 13 */
+	xsvfDoXSDRBCE,          /* 14 */
+	xsvfDoXSDRTDOBCE,       /* 15 */
+	xsvfDoXSDRTDOBCE,       /* 16 */
+	xsvfDoXSDRTDOBCE,       /* 17 */
+	xsvfDoXSTATE,           /* 18 */
+	xsvfDoXENDXR,           /* 19 */
+	xsvfDoXENDXR,           /* 20 */
+	xsvfDoXSIR2,            /* 21 */
+	xsvfDoXCOMMENT,         /* 22 */
+	xsvfDoXWAIT             /* 23 */
+/* Insert new command functions here */
+};
+
+#ifdef  DEBUG_MODE
+char* xsvf_pzCommandName[]  =
+{
+	"XCOMPLETE",
+	"XTDOMASK",
+	"XSIR",
+	"XSDR",
+	"XRUNTEST",
+	"Reserved5",
+	"Reserved6",
+	"XREPEAT",
+	"XSDRSIZE",
+	"XSDRTDO",
+	"XSETSDRMASKS",
+	"XSDRINC",
+	"XSDRB",
+	"XSDRC",
+	"XSDRE",
+	"XSDRTDOB",
+	"XSDRTDOC",
+	"XSDRTDOE",
+	"XSTATE",
+	"XENDIR",
+	"XENDDR",
+	"XSIR2",
+	"XCOMMENT",
+	"XWAIT"
+};
+
+char*   xsvf_pzErrorName[]  =
+{
+	"No error",
+	"ERROR:  Unknown",
+	"ERROR:  TDO mismatch",
+	"ERROR:  TDO mismatch and exceeded max retries",
+	"ERROR:  Unsupported XSVF command",
+	"ERROR:  Illegal state specification",
+	"ERROR:  Data overflows allocated MAX_LEN buffer size"
+};
+
+char*   xsvf_pzTapState[] =
+{
+	"RESET",        /* 0x00 */
+	"RUNTEST/IDLE", /* 0x01 */
+	"DRSELECT",     /* 0x02 */
+	"DRCAPTURE",    /* 0x03 */
+	"DRSHIFT",      /* 0x04 */
+	"DREXIT1",      /* 0x05 */
+	"DRPAUSE",      /* 0x06 */
+	"DREXIT2",      /* 0x07 */
+	"DRUPDATE",     /* 0x08 */
+	"IRSELECT",     /* 0x09 */
+	"IRCAPTURE",    /* 0x0A */
+	"IRSHIFT",      /* 0x0B */
+	"IREXIT1",      /* 0x0C */
+	"IRPAUSE",      /* 0x0D */
+	"IREXIT2",      /* 0x0E */
+	"IRUPDATE"      /* 0x0F */
+};
+#endif  /* DEBUG_MODE */
+
+/*#ifdef DEBUG_MODE	*/
+/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
+int xsvf_iDebugLevel;
+/*#endif /XXX* DEBUG_MODE */
+
+/*============================================================================
+ * Utility Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfPrintLenVal
+ * Description:  Print the lenval value in hex.
+ * Parameters:   plv     - ptr to lenval.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  DEBUG_MODE
+void xsvfPrintLenVal( lenVal *plv )
+{
+	int i;
+
+	if ( plv )
+	{
+		printf( "0x" );
+		for ( i = 0; i < plv->len; ++i )
+		{
+			printf( "%02x", ((unsigned int)(plv->val[ i ])) );
+		}
+	}
+}
+#endif  /* DEBUG_MODE */
+
+
+/*****************************************************************************
+ * Function:     xsvfInfoInit
+ * Description:  Initialize the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF1( 4, "    sizeof( SXsvfInfo ) = %d bytes\n",
+			 sizeof( SXsvfInfo ) );
+
+	pXsvfInfo->ucComplete       = 0;
+	pXsvfInfo->ucCommand        = XCOMPLETE;
+	pXsvfInfo->lCommandCount    = 0;
+	pXsvfInfo->iErrorCode       = XSVF_ERROR_NONE;
+	pXsvfInfo->ucMaxRepeat      = 0;
+	pXsvfInfo->ucTapState       = XTAPSTATE_RESET;
+	pXsvfInfo->ucEndIR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->ucEndDR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->lShiftLengthBits = 0L;
+	pXsvfInfo->sShiftLengthBytes= 0;
+	pXsvfInfo->lRunTestTime     = 0L;
+
+	return( 0 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfInfoCleanup
+ * Description:  Cleanup the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
+{
+}
+
+/*****************************************************************************
+ * Function:     xsvfGetAsNumBytes
+ * Description:  Calculate the number of bytes the given number of bits
+ *               consumes.
+ * Parameters:   lNumBits    - the number of bits.
+ * Returns:      short       - the number of bytes to store the number of bits.
+ *****************************************************************************/
+short xsvfGetAsNumBytes( long lNumBits )
+{
+	return( (short)( ( lNumBits + 7L ) / 8L ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfTmsTransition
+ * Description:  Apply TMS and transition TAP controller by applying one TCK
+ *               cycle.
+ * Parameters:   sTms    - new TMS value.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfTmsTransition( short sTms )
+{
+	setPort( TMS, sTms );
+	setPort( TCK, 0 );
+	setPort( TCK, 1 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfGotoTapState
+ * Description:  From the current TAP state, go to the named TAP state.
+ *               A target state of RESET ALWAYS causes TMS reset sequence.
+ *               All SVF standard stable state paths are supported.
+ *               All state transitions are supported except for the following
+ *               which cause an XSVF_ERROR_ILLEGALSTATE:
+ *                   - Target==DREXIT2;  Start!=DRPAUSE
+ *                   - Target==IREXIT2;  Start!=IRPAUSE
+ * Parameters:   pucTapState     - Current TAP state; returns final TAP state.
+ *               ucTargetState   - New target TAP state.
+ * Returns:      int             - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfGotoTapState( unsigned char*   pucTapState,
+		      unsigned char    ucTargetState )
+{
+	int i;
+	int iErrorCode;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	if ( ucTargetState == XTAPSTATE_RESET )
+	{
+		/* If RESET, always perform TMS reset sequence to reset/sync TAPs */
+		xsvfTmsTransition( 1 );
+		for ( i = 0; i < 5; ++i )
+		{
+			setPort( TCK, 0 );
+			setPort( TCK, 1 );
+		}
+		*pucTapState    = XTAPSTATE_RESET;
+		XSVFDBG_PRINTF( 3, "   TMS Reset Sequence -> Test-Logic-Reset\n" );
+		XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+				 xsvf_pzTapState[ *pucTapState ] );
+	} else if ( ( ucTargetState != *pucTapState ) &&
+		  ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
+		    ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
+	{
+		/* Trap illegal TAP state path specification */
+		iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+	} else {
+		if ( ucTargetState == *pucTapState )
+		{
+			/* Already in target state.  Do nothing except when in DRPAUSE
+			   or in IRPAUSE to comply with SVF standard */
+			if ( ucTargetState == XTAPSTATE_PAUSEDR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+			else if ( ucTargetState == XTAPSTATE_PAUSEIR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+		}
+
+		/* Perform TAP state transitions to get to the target state */
+		while ( ucTargetState != *pucTapState )
+		{
+			switch ( *pucTapState )
+			{
+			case XTAPSTATE_RESET:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_RUNTEST;
+				break;
+			case XTAPSTATE_RUNTEST:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_SELECTDR;
+				break;
+			case XTAPSTATE_SELECTDR:
+				if ( ucTargetState >= XTAPSTATE_IRSTATES )
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_CAPTUREDR;
+				}
+				break;
+			case XTAPSTATE_CAPTUREDR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1DR;
+				}
+				break;
+			case XTAPSTATE_SHIFTDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1DR;
+				break;
+			case XTAPSTATE_EXIT1DR:
+				if ( ucTargetState == XTAPSTATE_PAUSEDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_PAUSEDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				break;
+			case XTAPSTATE_EXIT2DR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_UPDATEDR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			case XTAPSTATE_SELECTIR:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_CAPTUREIR;
+				break;
+			case XTAPSTATE_CAPTUREIR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1IR;
+				}
+				break;
+			case XTAPSTATE_SHIFTIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1IR;
+				break;
+			case XTAPSTATE_EXIT1IR:
+				if ( ucTargetState == XTAPSTATE_PAUSEIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_PAUSEIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				break;
+			case XTAPSTATE_EXIT2IR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_UPDATEIR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			default:
+				iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+				*pucTapState    = ucTargetState;    /* Exit while loop */
+				break;
+			}
+			XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+					 xsvf_pzTapState[ *pucTapState ] );
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfShiftOnly
+ * Description:  Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Optionally, save the TDO data shifted out of the scan chain.
+ *               Last shift cycle is special:  capture last TDO, set last TDI,
+ *               but does not pulse TCK.  Caller must pulse TCK and optionally
+ *               set TMS=1 to exit shift state.
+ * Parameters:   lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing captured TDO data.
+ *               iExitShift      - 1=exit at end of shift; 0=stay in Shift-DR.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfShiftOnly( long    lNumBits,
+		    lenVal* plvTdi,
+		    lenVal* plvTdoCaptured,
+		    int     iExitShift )
+{
+	unsigned char*  pucTdi;
+	unsigned char*  pucTdo;
+	unsigned char   ucTdiByte;
+	unsigned char   ucTdoByte;
+	unsigned char   ucTdoBit;
+	int             i;
+
+	/* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
+
+	/* Initialize TDO storage len == TDI len */
+	pucTdo  = 0;
+	if ( plvTdoCaptured )
+	{
+		plvTdoCaptured->len = plvTdi->len;
+		pucTdo              = plvTdoCaptured->val + plvTdi->len;
+	}
+
+	/* Shift LSB first.  val[N-1] == LSB.  val[0] == MSB. */
+	pucTdi  = plvTdi->val + plvTdi->len;
+	while ( lNumBits )
+	{
+		/* Process on a byte-basis */
+		ucTdiByte   = (*(--pucTdi));
+		ucTdoByte   = 0;
+		for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
+		{
+			--lNumBits;
+			if ( iExitShift && !lNumBits )
+			{
+				/* Exit Shift-DR state */
+				setPort( TMS, 1 );
+			}
+
+			/* Set the new TDI value */
+			setPort( TDI, (short)(ucTdiByte & 1) );
+			ucTdiByte   >>= 1;
+
+			/* Set TCK low */
+			setPort( TCK, 0 );
+
+			if ( pucTdo )
+			{
+				/* Save the TDO value */
+				ucTdoBit    = readTDOBit();
+				ucTdoByte   |= ( ucTdoBit << i );
+			}
+
+			/* Set TCK high */
+			setPort( TCK, 1 );
+		}
+
+		/* Save the TDO byte value */
+		if ( pucTdo )
+		{
+			(*(--pucTdo))   = ucTdoByte;
+		}
+	}
+}
+
+/*****************************************************************************
+ * Function:     xsvfShift
+ * Description:  Goes to the given starting TAP state.
+ *               Calls xsvfShiftOnly to shift in the given TDI data and
+ *               optionally capture the TDO data.
+ *               Compares the TDO captured data against the TDO expected
+ *               data.
+ *               If a data mismatch occurs, then executes the exception
+ *               handling loop upto ucMaxRepeat times.
+ * Parameters:   pucTapState     - Ptr to current TAP state.
+ *               ucStartState    - Starting shift state: Shift-DR or Shift-IR.
+ *               lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing TDO data.
+ *               plvTdoExpected  - ptr to expected TDO data.
+ *               plvTdoMask      - ptr to TDO mask.
+ *               ucEndState      - state in which to end the shift.
+ *               lRunTestTime    - amount of time to wait after the shift.
+ *               ucMaxRepeat     - Maximum number of retries on TDO mismatch.
+ * Returns:      int             - 0 = success; otherwise TDO mismatch.
+ * Notes:        XC9500XL-only Optimization:
+ *               Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
+ *               is NOT all zeros and sMatch==1.
+ *****************************************************************************/
+int xsvfShift( unsigned char*   pucTapState,
+	       unsigned char    ucStartState,
+	       long             lNumBits,
+	       lenVal*          plvTdi,
+	       lenVal*          plvTdoCaptured,
+	       lenVal*          plvTdoExpected,
+	       lenVal*          plvTdoMask,
+	       unsigned char    ucEndState,
+	       long             lRunTestTime,
+	       unsigned char    ucMaxRepeat )
+{
+	int             iErrorCode;
+	int             iMismatch;
+	unsigned char   ucRepeat;
+	int             iExitShift;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	iMismatch   = 0;
+	ucRepeat    = 0;
+	iExitShift  = ( ucStartState != ucEndState );
+
+	XSVFDBG_PRINTF1( 3, "   Shift Length = %ld\n", lNumBits );
+	XSVFDBG_PRINTF( 4, "    TDI          = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdi );
+	XSVFDBG_PRINTF( 4, "\n");
+	XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+	XSVFDBG_PRINTF( 4, "\n");
+
+	if ( !lNumBits )
+	{
+		/* Compatibility with XSVF2.00:  XSDR 0 = no shift, but wait in RTI */
+		if ( lRunTestTime )
+		{
+			/* Wait for prespecified XRUNTEST time */
+			xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+			XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+			waitTime( lRunTestTime );
+		}
+	}
+	else
+	{
+		do
+		{
+			/* Goto Shift-DR or Shift-IR */
+			xsvfGotoTapState( pucTapState, ucStartState );
+
+			/* Shift TDI and capture TDO */
+			xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
+
+			if ( plvTdoExpected )
+			{
+				/* Compare TDO data to expected TDO data */
+				iMismatch   = !EqualLenVal( plvTdoExpected,
+							    plvTdoCaptured,
+							    plvTdoMask );
+			}
+
+			if ( iExitShift )
+			{
+				/* Update TAP state:  Shift->Exit */
+				++(*pucTapState);
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+
+				if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
+				{
+					XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Captured = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF1( 3, "   Retry #%d\n", ( ucRepeat + 1 ) );
+					/* Do exception handling retry - ShiftDR only */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
+					/* Shift 1 extra bit */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
+					/* Increment RUNTEST time by an additional 25% */
+					lRunTestTime    += ( lRunTestTime >> 2 );
+				}
+				else
+				{
+					/* Do normal exit from Shift-XR */
+					xsvfGotoTapState( pucTapState, ucEndState );
+				}
+
+				if ( lRunTestTime )
+				{
+					/* Wait for prespecified XRUNTEST time */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+					XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+					waitTime( lRunTestTime );
+				}
+			}
+		} while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
+	}
+
+	if ( iMismatch )
+	{
+		XSVFDBG_PRINTF( 1, " TDO Expected = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Captured = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Mask     = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
+		XSVFDBG_PRINTF( 1, "\n");
+		if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
+		{
+			iErrorCode  = XSVF_ERROR_MAXRETRIES;
+		}
+		else
+		{
+			iErrorCode  = XSVF_ERROR_TDOMISMATCH;
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfBasicXSDRTDO
+ * Description:  Get the XSDRTDO parameters and execute the XSDRTDO command.
+ *               This is the common function for all XSDRTDO commands.
+ * Parameters:   pucTapState         - Current TAP state.
+ *               lShiftLengthBits    - number of bits to shift.
+ *               sShiftLengthBytes   - number of bytes to read.
+ *               plvTdi              - ptr to lenval for TDI data.
+ *               lvTdoCaptured       - ptr to lenval for storing TDO data.
+ *               iEndState           - state in which to end the shift.
+ *               lRunTestTime        - amount of time to wait after the shift.
+ *               ucMaxRepeat         - maximum xc9500/xl retries.
+ * Returns:      int                 - 0 = success; otherwise TDO mismatch.
+ *****************************************************************************/
+int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
+		      long              lShiftLengthBits,
+		      short             sShiftLengthBytes,
+		      lenVal*           plvTdi,
+		      lenVal*           plvTdoCaptured,
+		      lenVal*           plvTdoExpected,
+		      lenVal*           plvTdoMask,
+		      unsigned char     ucEndState,
+		      long              lRunTestTime,
+		      unsigned char     ucMaxRepeat )
+{
+	readVal( plvTdi, sShiftLengthBytes );
+	if ( plvTdoExpected )
+	{
+		readVal( plvTdoExpected, sShiftLengthBytes );
+	}
+	return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
+			   plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
+			   ucEndState, lRunTestTime, ucMaxRepeat ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoSDRMasking
+ * Description:  Update the data value with the next XSDRINC data and address.
+ * Example:      dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
+ *               dataMask=0x00ff, should set dataVal to 0x02ab
+ * Parameters:   plvTdi          - The current TDI value.
+ *               plvNextData     - the next data value.
+ *               plvAddressMask  - the address mask.
+ *               plvDataMask     - the data mask.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+void xsvfDoSDRMasking( lenVal*  plvTdi,
+		       lenVal*  plvNextData,
+		       lenVal*  plvAddressMask,
+		       lenVal*  plvDataMask )
+{
+	int             i;
+	unsigned char   ucTdi;
+	unsigned char   ucTdiMask;
+	unsigned char   ucDataMask;
+	unsigned char   ucNextData;
+	unsigned char   ucNextMask;
+	short           sNextData;
+
+	/* add the address Mask to dataVal and return as a new dataVal */
+	addVal( plvTdi, plvTdi, plvAddressMask );
+
+	ucNextData  = 0;
+	ucNextMask  = 0;
+	sNextData   = plvNextData->len;
+	for ( i = plvDataMask->len - 1; i >= 0; --i )
+	{
+		/* Go through data mask in reverse order looking for mask (1) bits */
+		ucDataMask  = plvDataMask->val[ i ];
+		if ( ucDataMask )
+		{
+			/* Retrieve the corresponding TDI byte value */
+			ucTdi       = plvTdi->val[ i ];
+
+			/* For each bit in the data mask byte, look for 1's */
+			ucTdiMask   = 1;
+			while ( ucDataMask )
+			{
+				if ( ucDataMask & 1 )
+				{
+					if ( !ucNextMask )
+					{
+						/* Get the next data byte */
+						ucNextData  = plvNextData->val[ --sNextData ];
+						ucNextMask  = 1;
+					}
+
+					/* Set or clear the data bit according to the next data */
+					if ( ucNextData & ucNextMask )
+					{
+						ucTdi   |= ucTdiMask;       /* Set bit */
+					}
+					else
+					{
+						ucTdi   &= ( ~ucTdiMask );  /* Clear bit */
+					}
+
+					/* Update the next data */
+					ucNextMask  <<= 1;
+				}
+				ucTdiMask   <<= 1;
+				ucDataMask  >>= 1;
+			}
+
+			/* Update the TDI value */
+			plvTdi->val[ i ]    = ucTdi;
+		}
+	}
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*============================================================================
+ * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
+ * These functions update pXsvfInfo->iErrorCode only on an error.
+ * Otherwise, the error code is left alone.
+ * The function returns the error code from the function.
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfDoIllegalCmd
+ * Description:  Function place holder for illegal/unsupported commands.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF2( 0, "ERROR:  Encountered unsupported command #%d (%s)\n",
+			 ((unsigned int)(pXsvfInfo->ucCommand)),
+			 ((pXsvfInfo->ucCommand < XLASTCMD)
+			  ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
+			  : "Unknown") );
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_ILLEGALCMD;
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMPLETE
+ * Description:  XCOMPLETE (no parameters)
+ *               Update complete status for XSVF player.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
+{
+	pXsvfInfo->ucComplete   = 1;
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXTDOMASK
+ * Description:  XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
+ *               Prespecify the TDO compare mask.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
+	XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
+	XSVFDBG_PRINTF( 4, "\n");
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR
+ * Description:  XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readByte( &ucShiftIrBits );
+	sShiftIrBytes   = xsvfGetAsNumBytes( ucShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR length = %d\n",
+			 ((unsigned int)ucShiftIrBits) );
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 ucShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR2
+ * Description:  XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
+{
+	long            lShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readVal( &(pXsvfInfo->lvTdi), 2 );
+	lShiftIrBits    = value( &(pXsvfInfo->lvTdi) );
+	sShiftIrBytes   = xsvfGetAsNumBytes( lShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR2 length = %d\n", (int)lShiftIrBits);
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 lShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDR
+ * Description:  XSDR <lenVal.TDI[XSDRSIZE]>
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare the captured TDO with the expected TDO from the
+ *               previous XSDRTDO command using the previously specified
+ *               XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	/* use TDOExpected from last XSDRTDO instruction */
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
+				 &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXRUNTEST
+ * Description:  XRUNTEST <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF1( 3, "   XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXREPEAT
+ * Description:  XREPEAT <byte>
+ *               Prespecify the maximum number of XC9500/XL retries.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
+{
+	readByte( &(pXsvfInfo->ucMaxRepeat) );
+	XSVFDBG_PRINTF1( 3, "   XREPEAT = %d\n",
+			 ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRSIZE
+ * Description:  XSDRSIZE <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = XSVF_ERROR_NONE;
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
+	pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
+	XSVFDBG_PRINTF1( 3, "   XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
+	if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDO
+ * Description:  XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               Get the TDI and expected TDO values.  Then, shift.
+ *               Compare the expected TDO with the captured TDO using the
+ *               prespecified XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					&(pXsvfInfo->lvTdoMask),
+					pXsvfInfo->ucEndDR,
+					pXsvfInfo->lRunTestTime,
+					pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSETSDRMASKS
+ * Description:  XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
+ *                            <lenVal.DataMask[XSDRSIZE]>
+ *               Get the prespecified address and data mask for the XSDRINC
+ *               command.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
+{
+	/* read the addressMask */
+	readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
+	/* read the dataMask    */
+	readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
+
+	XSVFDBG_PRINTF( 4, "    Address Mask = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+	XSVFDBG_PRINTF( 4, "    Data Mask    = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+
+	return( XSVF_ERROR_NONE );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRINC
+ * Description:  XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
+ *                       <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
+ *               Get the XSDRINC parameters and execute the XSDRINC command.
+ *               XSDRINC starts by loading the first TDI shift value.
+ *               Then, for numTimes, XSDRINC gets the next piece of data,
+ *               replaces the bits from the starting TDI as defined by the
+ *               XSETSDRMASKS.dataMask, adds the address mask from
+ *               XSETSDRMASKS.addressMask, shifts the new TDI value,
+ *               and compares the TDO to the expected TDO from the previous
+ *               XSDRTDO command using the XTDOMASK.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	int             iDataMaskLen;
+	unsigned char   ucDataMask;
+	unsigned char   ucNumTimes;
+	unsigned char   i;
+
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits,
+				 &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( !iErrorCode )
+	{
+		/* Calculate number of data mask bits */
+		iDataMaskLen    = 0;
+		for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
+		{
+			ucDataMask  = pXsvfInfo->lvDataMask.val[ i ];
+			while ( ucDataMask )
+			{
+				iDataMaskLen    += ( ucDataMask & 1 );
+				ucDataMask      >>= 1;
+			}
+		}
+
+		/* Get the number of data pieces, i.e. number of times to shift */
+		readByte( &ucNumTimes );
+
+		/* For numTimes, get data, fix TDI, and shift */
+		for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
+		{
+			readVal( &(pXsvfInfo->lvNextData),
+				 xsvfGetAsNumBytes( iDataMaskLen ) );
+			xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
+					  &(pXsvfInfo->lvNextData),
+					  &(pXsvfInfo->lvAddressMask),
+					  &(pXsvfInfo->lvDataMask) );
+			iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState),
+						 XTAPSTATE_SHIFTDR,
+						 pXsvfInfo->lShiftLengthBits,
+						 &(pXsvfInfo->lvTdi),
+						 &(pXsvfInfo->lvTdoCaptured),
+						 &(pXsvfInfo->lvTdoExpected),
+						 &(pXsvfInfo->lvTdoMask),
+						 pXsvfInfo->ucEndDR,
+						 pXsvfInfo->lRunTestTime,
+						 pXsvfInfo->ucMaxRepeat );
+		}
+	}
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Ignore TDO.
+ *               If cmd==XSDRE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRB, XSDRC, and XSDRE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					/*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDOBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare TDO, but do NOT use XTDOMASK.
+ *               If cmd==XSDRTDOE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSTATE
+ * Description:  XSTATE <byte>
+ *               <byte> == XTAPSTATE;
+ *               Get the state parameter and transition the TAP to that state.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucNextState;
+	int             iErrorCode;
+	readByte( &ucNextState );
+	iErrorCode  = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXENDXR
+ * Description:  XENDIR/XENDDR <byte>
+ *               <byte>:  0 = RUNTEST;  1 = PAUSE.
+ *               Get the prespecified XENDIR or XENDDR.
+ *               Both XENDIR and XENDDR use the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	unsigned char   ucEndState;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	readByte( &ucEndState );
+	if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
+	{
+		iErrorCode  = XSVF_ERROR_ILLEGALSTATE;
+	}
+	else
+	{
+
+		if ( pXsvfInfo->ucCommand == XENDIR )
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_PAUSEIR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDIR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
+		}
+		else    /* XENDDR */
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_PAUSEDR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDDR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
+		}
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMMENT
+ * Description:  XCOMMENT <text string ending in \0>
+ *               <text string ending in \0> == text comment;
+ *               Arbitrary comment embedded in the XSVF.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
+{
+	/* Use the comment for debugging */
+	/* Otherwise, read through the comment to the end '\0' and ignore */
+	unsigned char   ucText;
+
+	if ( xsvf_iDebugLevel > 0 )
+	{
+		putc( ' ' );
+	}
+
+	do
+	{
+		readByte( &ucText );
+		if ( xsvf_iDebugLevel > 0 )
+		{
+			putc( ucText ? ucText : '\n' );
+		}
+	} while ( ucText );
+
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_NONE;
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXWAIT
+ * Description:  XWAIT <wait_state> <end_state> <wait_time>
+ *               If not already in <wait_state>, then go to <wait_state>.
+ *               Wait in <wait_state> for <wait_time> microseconds.
+ *               Finally, if not already in <end_state>, then goto <end_state>.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucWaitState;
+	unsigned char   ucEndState;
+	long            lWaitTime;
+
+	/* Get Parameters */
+	/* <wait_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucWaitState = pXsvfInfo->lvTdi.val[0];
+
+	/* <end_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucEndState = pXsvfInfo->lvTdi.val[0];
+
+	/* <wait_time> */
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	lWaitTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF2( 3, "   XWAIT:  state = %s; time = %ld\n",
+			 xsvf_pzTapState[ ucWaitState ], lWaitTime );
+
+	/* If not already in <wait_state>, go to <wait_state> */
+	if ( pXsvfInfo->ucTapState != ucWaitState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
+	}
+
+	/* Wait for <wait_time> microseconds */
+	waitTime( lWaitTime );
+
+	/* If not already in <end_state>, go to <end_state> */
+	if ( pXsvfInfo->ucTapState != ucEndState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
+	}
+
+	return( XSVF_ERROR_NONE );
+}
+
+
+/*============================================================================
+ * Execution Control Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfInitialize
+ * Description:  Initialize the xsvf player.
+ *               Call this before running the player to initialize the data
+ *               in the SXsvfInfo struct.
+ *               xsvfCleanup is called to clean up the data in SXsvfInfo
+ *               after the XSVF is played.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInitialize( SXsvfInfo* pXsvfInfo )
+{
+	/* Initialize values */
+	pXsvfInfo->iErrorCode   = xsvfInfoInit( pXsvfInfo );
+
+	if ( !pXsvfInfo->iErrorCode )
+	{
+		/* Initialize the TAPs */
+		pXsvfInfo->iErrorCode   = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
+							    XTAPSTATE_RESET );
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfRun
+ * Description:  Run the xsvf player for a single command and return.
+ *               First, call xsvfInitialize.
+ *               Then, repeatedly call this function until an error is detected
+ *               or until the pXsvfInfo->ucComplete variable is non-zero.
+ *               Finally, call xsvfCleanup to cleanup any remnants.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfRun( SXsvfInfo* pXsvfInfo )
+{
+	/* Process the XSVF commands */
+	if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
+	{
+		/* read 1 byte for the instruction */
+		readByte( &(pXsvfInfo->ucCommand) );
+		++(pXsvfInfo->lCommandCount);
+
+		if ( pXsvfInfo->ucCommand < XLASTCMD )
+		{
+			/* Execute the command.  Func sets error code. */
+			XSVFDBG_PRINTF1( 2, "  %s\n",
+					 xsvf_pzCommandName[pXsvfInfo->ucCommand] );
+			/* If your compiler cannot take this form,
+			   then convert to a switch statement */
+#if 0 /* test-only */
+			xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
+#else
+			switch (pXsvfInfo->ucCommand) {
+			case 0:
+				xsvfDoXCOMPLETE(pXsvfInfo);        /*  0 */
+				break;
+			case 1:
+				xsvfDoXTDOMASK(pXsvfInfo);         /*  1 */
+				break;
+			case 2:
+				xsvfDoXSIR(pXsvfInfo);             /*  2 */
+				break;
+			case 3:
+				xsvfDoXSDR(pXsvfInfo);             /*  3 */
+				break;
+			case 4:
+				xsvfDoXRUNTEST(pXsvfInfo);         /*  4 */
+				break;
+			case 5:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  5 */
+				break;
+			case 6:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  6 */
+				break;
+			case 7:
+				xsvfDoXREPEAT(pXsvfInfo);          /*  7 */
+				break;
+			case 8:
+				xsvfDoXSDRSIZE(pXsvfInfo);         /*  8 */
+				break;
+			case 9:
+				xsvfDoXSDRTDO(pXsvfInfo);          /*  9 */
+				break;
+#ifdef  XSVF_SUPPORT_COMPRESSION
+			case 10:
+				xsvfDoXSETSDRMASKS(pXsvfInfo);     /* 10 */
+				break;
+			case 11:
+				xsvfDoXSDRINC(pXsvfInfo);          /* 11 */
+				break;
+#else
+			case 10:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 10 */
+				break;
+			case 11:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 11 */
+				break;
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+			case 12:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 12 */
+				break;
+			case 13:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 13 */
+				break;
+			case 14:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 14 */
+				break;
+			case 15:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 15 */
+				break;
+			case 16:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 16 */
+				break;
+			case 17:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 17 */
+				break;
+			case 18:
+				xsvfDoXSTATE(pXsvfInfo);           /* 18 */
+				break;
+			case 19:
+				xsvfDoXENDXR(pXsvfInfo);           /* 19 */
+				break;
+			case 20:
+				xsvfDoXENDXR(pXsvfInfo);           /* 20 */
+				break;
+			case 21:
+				xsvfDoXSIR2(pXsvfInfo);            /* 21 */
+				break;
+			case 22:
+				xsvfDoXCOMMENT(pXsvfInfo);         /* 22 */
+				break;
+			case 23:
+				xsvfDoXWAIT(pXsvfInfo);             /* 23 */
+				break;
+			}
+#endif
+		}
+		else
+		{
+			/* Illegal command value.  Func sets error code. */
+			xsvfDoIllegalCmd( pXsvfInfo );
+		}
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfCleanup
+ * Description:  cleanup remnants of the xsvf player.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfCleanup( SXsvfInfo* pXsvfInfo )
+{
+	xsvfInfoCleanup( pXsvfInfo );
+}
+
+
+/*============================================================================
+ * xsvfExecute() - The primary entry point to the XSVF player
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - Legacy result values:  1 == success;  0 == failed.
+ *****************************************************************************/
+int xsvfExecute(void)
+{
+	SXsvfInfo   xsvfInfo;
+
+	xsvfInitialize( &xsvfInfo );
+
+	while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
+	{
+		xsvfRun( &xsvfInfo );
+	}
+
+	if ( xsvfInfo.iErrorCode )
+	{
+		XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
+					 ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
+					 ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
+		XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld.  See line #%ld in the XSVF ASCII file.\n",
+				 xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
+	}
+	else
+	{
+		XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
+	}
+
+	xsvfCleanup( &xsvfInfo );
+
+	return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
+}
+
+
+/*****************************************************************************
+ * Function:     do_cpld
+ * Description:  main function.
+ *               Specified here for creating stand-alone debug executable.
+ *               Embedded users should call xsvfExecute() directly.
+ * Parameters:   iArgc    - number of command-line arguments.
+ *               ppzArgv  - array of ptrs to strings (command-line arguments).
+ * Returns:      int      - Legacy return value:  1 = success; 0 = error.
+ *****************************************************************************/
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int     iErrorCode;
+	unsigned long duration;
+	unsigned long long startClock, endClock;
+
+	if (argc == 2)
+		xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16);
+	else {
+#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR
+		xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR;
+#else
+		printf("Usage:\ncpld %s\n", cmdtp->help);
+		return -1;
+#endif
+	}
+
+	iErrorCode          = XSVF_ERRORCODE( XSVF_ERROR_NONE );
+	xsvf_iDebugLevel    = 0;
+
+	printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
+	printf("Reading XSVF data @ %p\n", xsvfdata);
+
+	/* Initialize the I/O.  SetPort initializes I/O on first call */
+	setPort( TMS, 1 );
+
+	/* Execute the XSVF in the file */
+	startClock  = get_ticks();
+	iErrorCode  = xsvfExecute();
+	endClock    = get_ticks();
+	duration    = (unsigned long)(endClock - startClock);
+	printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
+
+	return( iErrorCode );
+}
+U_BOOT_CMD(
+	cpld,	2,	1,	do_cpld,
+	"program onboard CPLD",
+	"<xsvf-addr>"
+);
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/micro.h b/roms/u-boot/board/esd/common/xilinx_jtag/micro.h
new file mode 100644
index 00000000..e9a76128
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/micro.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/ports.c b/roms/u-boot/board/esd/common/xilinx_jtag/ports.c
new file mode 100644
index 00000000..d79dbd1e
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/ports.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: ports.c                                       */
+/* abstract:  This file contains the routines to       */
+/*            output values on the JTAG ports, to read */
+/*            the TDO bit, and to read a byte of data  */
+/*            from the prom                            */
+/*                                                     */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "ports.h"
+
+static unsigned long output = 0;
+static int filepos = 0;
+static int oldstate = 0;
+static int newstate = 0;
+static int readptr = 0;
+
+extern const unsigned char *xsvfdata;
+
+/* if in debugging mode, then just set the variables */
+void setPort(short p,short val)
+{
+	if (p==TMS) {
+		if (val) {
+			output |= JTAG_TMS;
+		} else {
+			output &= ~JTAG_TMS;
+		}
+	}
+	if (p==TDI) {
+		if (val) {
+			output |= JTAG_TDI;
+		} else {
+			output &= ~JTAG_TDI;
+		}
+	}
+	if (p==TCK) {
+		if (val) {
+			output |= JTAG_TCK;
+		} else {
+			output &= ~JTAG_TCK;
+		}
+		out_be32((void *)GPIO0_OR, output);
+	}
+}
+
+
+/* toggle tck LH */
+void pulseClock(void)
+{
+	setPort(TCK,0);  /* set the TCK port to low  */
+	setPort(TCK,1);  /* set the TCK port to high */
+}
+
+
+/* read in a byte of data from the prom */
+void readByte(unsigned char *data)
+{
+	/* pretend reading using a file */
+	*data = xsvfdata[readptr++];
+	newstate = filepos++ >> 10;
+	if (newstate != oldstate) {
+		printf("%4d kB\r\r\r\r", newstate);
+		oldstate = newstate;
+	}
+}
+
+/* read the TDO bit from port */
+unsigned char readTDOBit(void)
+{
+	unsigned long inputs;
+
+	inputs = in_be32((void *)GPIO0_IR);
+	if (inputs & JTAG_TDO)
+		return 1;
+	else
+		return 0;
+}
+
+
+/* Wait at least the specified number of microsec.                           */
+/* Use a timer if possible; otherwise estimate the number of instructions    */
+/* necessary to be run based on the microcontroller speed.  For this example */
+/* we pulse the TCK port a number of times based on the processor speed.     */
+void waitTime(long microsec)
+{
+	udelay(microsec); /* esd */
+}
diff --git a/roms/u-boot/board/esd/common/xilinx_jtag/ports.h b/roms/u-boot/board/esd/common/xilinx_jtag/ports.h
new file mode 100644
index 00000000..8ee7de92
--- /dev/null
+++ b/roms/u-boot/board/esd/common/xilinx_jtag/ports.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: ports.h                                       */
+/* abstract:  This file contains extern declarations   */
+/*            for providing stimulus to the JTAG ports.*/
+/*******************************************************/
+
+#ifndef ports_dot_h
+#define ports_dot_h
+
+/* these constants are used to send the appropriate ports to setPort */
+/* they should be enumerated types, but some of the microcontroller  */
+/* compilers don't like enumerated types */
+#define TCK (short) 0
+#define TMS (short) 1
+#define TDI (short) 2
+
+/*
+ * Use CONFIG_SYS_FPGA_xxx defines from board include file.
+ */
+#define JTAG_TMS   CONFIG_SYS_FPGA_PRG     /* output */
+#define JTAG_TCK   CONFIG_SYS_FPGA_CLK     /* output */
+#define JTAG_TDI   CONFIG_SYS_FPGA_DATA    /* output */
+#define JTAG_TDO   CONFIG_SYS_FPGA_DONE    /* input */
+
+/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
+void setPort(short p, short val);
+
+/* read the TDO bit and store it in val */
+unsigned char readTDOBit(void);
+
+/* make clock go down->up->down*/
+void pulseClock(void);
+
+/* read the next byte of data from the xsvf file */
+void readByte(unsigned char *data);
+
+void waitTime(long microsec);
+
+#endif
diff --git a/roms/u-boot/board/esd/cpci2dp/Makefile b/roms/u-boot/board/esd/cpci2dp/Makefile
new file mode 100644
index 00000000..ce2c6dd9
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci2dp/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/roms/u-boot/board/esd/cpci2dp/cpci2dp.c b/roms/u-boot/board/esd/cpci2dp/cpci2dp.c
new file mode 100644
index 00000000..336c5512
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci2dp/cpci2dp.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * Setup GPIO pins
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg |
+	      ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
+		CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
+
+	/* set output pins to high */
+	out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
+	/* setup for output (LED=off) */
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) unused
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming CPCI2DP");
+	} else {
+		puts(str);
+	}
+
+	printf(" (Ver 1.0)");
+
+	putc ('\n');
+
+	return 0;
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	   <state>     -1: deliver current state
+ *		       0: disable write
+ *		       1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(
+	eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/roms/u-boot/board/esd/cpci2dp/flash.c b/roms/u-boot/board/esd/cpci2dp/flash.c
new file mode 100644
index 00000000..34bdc053
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci2dp/flash.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	/*          printf("PB1CR = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/cpci405/Makefile b/roms/u-boot/board/esd/cpci405/Makefile
new file mode 100644
index 00000000..b1405717
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpci405.o flash.o ../common/misc.o ../common/auto_update.o
+obj-y	+= ../common/cmd_loadpci.o
diff --git a/roms/u-boot/board/esd/cpci405/cpci405.c b/roms/u-boot/board/esd/cpci405/cpci405.c
new file mode 100644
index 00000000..63cd862d
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/cpci405.c
@@ -0,0 +1,767 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
+#  include "fpgadata_cpci405ab.c"
+# else
+#  include "fpgadata_cpci4052.c"
+# endif
+#else
+# include "fpgadata_cpci405.c"
+#endif
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+#include "../common/auto_update.h"
+
+#if defined(CONFIG_CPCI405AB)
+au_image_t au_image[] = {
+	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#if defined(CONFIG_CPCI405_VER2)
+au_image_t au_image[] = {
+	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+	{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+	{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+	{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+/* Prototypes */
+int cpci405_version(void);
+void lxt971_no_sleep(void);
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index, len, i;
+	int status;
+#endif
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void)get_clocks();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	console_init_f();
+#endif
+
+	/*
+	 * First pull fpga-prg pin low,
+	 * to disable fpga logic (on version 2 board)
+	 */
+	out_be32((void *)GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+	out_be32((void *)GPIO0_OR, 0);		     /* pull prg low		*/
+
+	/*
+	 * Boot onboard FPGA
+	 */
+#ifndef CONFIG_CPCI405_VER2
+	if (cpci405_version() == 1) {
+		status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			/* set up serial port with default baudrate */
+			(void)get_clocks();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init();
+			console_init_f();
+#endif
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r",i);
+				for (index = 0; index < 1000; index++)
+					udelay(1000);
+			}
+			putc('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+#endif /* !CONFIG_CPCI405_VER2 */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
+#if defined(CONFIG_CPCI405_6U)
+	if (cpci405_version() == 3) {
+		mtdcr(UIC0PR, 0xFFFFFF99);	/* set int polarities */
+	} else {
+		mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	}
+#else
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
+#endif
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,
+					 * INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int ctermm2(void)
+{
+#if defined(CONFIG_CPCI405_VER2)
+	return 0;			/* no, board is cpci405 */
+#else
+	if ((in_8((void*)0xf0000400) == 0x00) &&
+	    (in_8((void*)0xf0000401) == 0x01))
+		return 0;		/* no, board is cpci405 */
+	else
+		return -1;		/* yes, board is cterm-m2 */
+#endif
+}
+
+int cpci405_host(void)
+{
+	if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
+		return -1;		/* yes, board is cpci405 host */
+	else
+		return 0;		/* no, board is cpci405 adapter */
+}
+
+int cpci405_version(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
+	udelay(1000); /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version 1 */
+		return 1;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 2 */
+		return 2;
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 3 or 6U board */
+		return 3;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 4 */
+		return 4;
+	default:
+		/* should not be reached! */
+		return 2;
+	}
+}
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_CPCI405_VER2)
+	{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/*
+	 * On CPCI-405 version 2 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+	if (cpci405_version() >= 2) {
+		/*
+		 * Setup GPIO pins (CS6+CS7 as GPIO)
+		 */
+		CPC0_CR0Reg = mfdcr(CPC0_CR0);
+		mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+			   (uchar *)fpgadata, &len) != 0) {
+			printf("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		status = fpga_boot(dst, len);
+		if (status != 0) {
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = dst[index];
+				printf("FPGA: %s\n", &(dst[index + 1]));
+				index += len + 3;
+			}
+			putc('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay(1000);
+			}
+			putc('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* restore gpio/cs settings */
+		mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+		puts("FPGA:  ");
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = dst[index];
+			printf("%s ", &(dst[index + 1]));
+			index += len + 3;
+		}
+		putc('\n');
+
+		free(dst);
+
+		/*
+		 * Reset FPGA via FPGA_DATA pin
+		 */
+		SET_FPGA(FPGA_PRG | FPGA_CLK);
+		udelay(1000); /* wait 1ms */
+		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+		udelay(1000); /* wait 1ms */
+
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
+		if (cpci405_version() == 3) {
+			/*
+			 * Enable outputs in fpga on version 3 board
+			 */
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
+
+			/*
+			 * Set outputs to 0
+			 */
+			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
+
+			/*
+			 * Reset external DUART
+			 */
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
+			udelay(100);
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
+		}
+#endif
+	}
+	else {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Version 1.x detected!\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI405 instead of CPCI4052)!\n\n");
+	}
+	}
+#else /* CONFIG_CPCI405_VER2 */
+	if (cpci405_version() >= 2) {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Board Version 2.x detected!\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI4052 instead of CPCI405)!\n\n");
+	}
+#endif /* CONFIG_CPCI405_VER2 */
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index;
+	int len;
+#endif
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	unsigned short ver;
+
+	puts("Board: ");
+
+	if (i == -1)
+		puts("### No HW ID - assuming CPCI405");
+	else
+		puts(str);
+
+	ver = cpci405_version();
+	printf(" (Ver %d.x, ", ver);
+
+	if (ctermm2()) {
+		char str[4];
+
+		/*
+		 * Read board-id and save in env-variable
+		 */
+		sprintf(str, "%d", *(unsigned char *)0xf0000400);
+		setenv("boardid", str);
+		printf("CTERM-M2 - Id=%s)", str);
+	} else {
+		if (cpci405_host())
+			puts("PCI Host Version)");
+		else
+			puts("PCI Adapter Version)");
+	}
+
+#ifndef CONFIG_CPCI405_VER2
+	puts("\nFPGA:	");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+#endif
+
+	putc('\n');
+	return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {	/* assert RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+	} else {	/* release RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+			 CONFIG_SYS_FPGA_MODE_CF_RESET);
+	}
+}
+
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
+
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = 0xff;
+
+	/*
+	 * Write pci interrupt line register (cpci405 specific)
+	 */
+	switch (PCI_DEV(dev) & 0x03) {
+	case 0:
+		int_line = 27 + 2;
+		break;
+	case 1:
+		int_line = 27 + 3;
+		break;
+	case 2:
+		int_line = 27 + 0;
+		break;
+	case 3:
+		int_line = 27 + 1;
+		break;
+	}
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = cpci405_pci_fixup_irq;
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in adapter mode.
+	 */
+	if (!cpci405_host()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) | \
+					  CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_SET	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) & \
+					  ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_GET	 (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+					  CONFIG_SYS_FPGA_STATUS)) &  \
+			  CONFIG_SYS_FPGA_MODE_1WIRE)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(480);
+	ONE_WIRE_SET;
+	udelay(70);
+
+	result = ONE_WIRE_GET;
+
+	udelay(410);
+	return result;
+}
+
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
+{
+	if (bit) {
+		/*
+		 * write '1' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(6);
+		ONE_WIRE_SET;
+		udelay(64);
+	} else {
+		/*
+		 * write '0' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(60);
+		ONE_WIRE_SET;
+		udelay(10);
+	}
+}
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(6);
+	ONE_WIRE_SET;
+	udelay(9);
+
+	result = ONE_WIRE_GET;
+
+	udelay(55);
+	return result;
+}
+
+void OWWriteByte(int data)
+{
+	int loop;
+
+	for (loop = 0; loop < 8; loop++) {
+		OWWriteBit(data & 0x01);
+		data >>= 1;
+	}
+}
+
+int OWReadByte(void)
+{
+	int loop, result = 0;
+
+	for (loop = 0; loop < 8; loop++) {
+		result >>= 1;
+		if (OWReadBit())
+			result |= 0x80;
+	}
+
+	return result;
+}
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned short val;
+	int result;
+	int i;
+	unsigned char ow_id[6];
+	char str[32];
+
+	/*
+	 * Clear 1-wire bit (open drain with pull-up)
+	 */
+	val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			      CONFIG_SYS_FPGA_MODE));
+	val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+	out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			 CONFIG_SYS_FPGA_MODE), val);
+
+	result = OWTouchReset();
+	if (result != 0)
+		puts("No 1-wire device detected!\n");
+
+	OWWriteByte(0x33); /* send read rom command */
+	OWReadByte(); /* skip family code ( == 0x01) */
+	for (i = 0; i < 6; i++)
+		ow_id[i] = OWReadByte();
+	OWReadByte(); /* read crc */
+
+	sprintf(str, "%02X%02X%02X%02X%02X%02X",
+		ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
+	printf("Setting environment variable 'ow_id' to %s\n", str);
+	setenv("ow_id", str);
+
+	return 0;
+}
+U_BOOT_CMD(
+	onewire,	1,	1,	do_onewire,
+	"Read 1-write ID",
+	""
+);
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *buf;
+	ulong crc;
+	char str[32];
+	char *ptr;
+	IPaddr_t ipaddr;
+
+	buf = malloc(CONFIG_ENV_SIZE_2);
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+			(uchar *)buf, CONFIG_ENV_SIZE_2))
+		puts("\nError reading backplane EEPROM!\n");
+	else {
+		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+		if (crc != *(ulong *)buf) {
+			printf("ERROR: crc mismatch %08lx %08lx\n",
+			       crc, *(ulong *)buf);
+			return -1;
+		}
+
+		/*
+		 * Find bp_ip
+		 */
+		ptr = strstr(buf+4, "bp_ip=");
+		if (ptr == NULL) {
+			printf("ERROR: bp_ip not found!\n");
+			return -1;
+		}
+		ptr += 6;
+		ipaddr = string_to_ip(ptr);
+
+		/*
+		 * Update whole ip-addr
+		 */
+		sprintf(str, "%pI4", &ipaddr);
+		setenv("ipaddr", str);
+		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getbpip,	1,	1,	do_get_bpip,
+	"Update IP-Address with Backplane IP-Address",
+	""
+);
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *buf;
+	char str[32];
+	ulong crc;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	printf("Setting bp_ip to %s\n", argv[1]);
+	buf = malloc(CONFIG_ENV_SIZE_2);
+	memset(buf, 0, CONFIG_ENV_SIZE_2);
+	sprintf(str, "bp_ip=%s", argv[1]);
+	strcpy(buf+4, str);
+	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+	*(ulong *)buf = crc;
+
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+			 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
+		puts("\nError writing backplane EEPROM!\n");
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setbpip,	2,	1,	do_set_bpip,
+	"Write Backplane IP-Address",
+	""
+);
+
+#endif /* CONFIG_CPCI405AB */
diff --git a/roms/u-boot/board/esd/cpci405/flash.c b/roms/u-boot/board/esd/cpci405/flash.c
new file mode 100644
index 00000000..091652b6
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/flash.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long calc_size(unsigned long size)
+{
+	switch (size) {
+	case 1 << 20:
+		return 0;
+	case 2 << 20:
+		return 1;
+	case 4 << 20:
+		return 2;
+	case 8 << 20:
+		return 3;
+	case 16 << 20:
+		return 4;
+	default:
+		return 0;
+	}
+}
+
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		if (size_b1 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b1 = 1 << 20;
+		}
+		base_b1 = -size_b1;
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+		printf("size_b1=%x base_b1=%x PB1CR = %x\n",
+		       size_b1, base_b1, pbcr); /* test-only */
+#endif
+	}
+
+	if (size_b0) {
+		if (size_b0 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b0 = 1 << 20;
+		}
+		base_b0 = base_b1 - size_b0;
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+		printf("size_b0=%x base_b0=%x PB0CR = %x\n",
+		       size_b0, base_b0, pbcr); /* test-only */
+#endif
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/roms/u-boot/board/esd/cpci405/fpgadata_cpci405.c b/roms/u-boot/board/esd/cpci405/fpgadata_cpci405.c
new file mode 100644
index 00000000..46c2feda
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/fpgadata_cpci405.c
@@ -0,0 +1,683 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
+0x63, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35, 0x32,
+0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
+0x73, 0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31,
+0x30, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
+0x30, 0x31, 0x2f, 0x30, 0x35, 0x2f, 0x31, 0x30,
+0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x31,
+0x35, 0x3a, 0x32, 0x33, 0x00, 0x65, 0xe2, 0x01,
+0x00, 0x00, 0x15, 0x08, 0xff, 0x30, 0xe8, 0x01,
+0x01, 0x01, 0x01, 0xe7, 0xe6, 0x04, 0x01, 0x02,
+0x11, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
+0x03, 0x04, 0x04, 0x0b, 0x02, 0x02, 0x01, 0x04,
+0x02, 0x01, 0x0b, 0x07, 0x01, 0x01, 0x0d, 0x03,
+0x05, 0x09, 0x03, 0x05, 0x03, 0x05, 0x03, 0x0b,
+0x13, 0x01, 0x06, 0xe5, 0xe5, 0x02, 0x03, 0x0c,
+0x01, 0xe6, 0x11, 0x08, 0x13, 0x16, 0x08, 0x1e,
+0x0b, 0xe5, 0xe6, 0x0e, 0x09, 0x09, 0x09, 0x09,
+0x0b, 0x07, 0xe6, 0x08, 0x02, 0xe5, 0x04, 0x01,
+0xe6, 0x04, 0x0e, 0x01, 0x01, 0x14, 0x09, 0x09,
+0x09, 0x09, 0x05, 0x05, 0xe5, 0xe6, 0x04, 0x03,
+0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0x0c, 0xe5,
+0x5b, 0x01, 0x01, 0x05, 0x01, 0x11, 0x02, 0xe5,
+0xe5, 0x48, 0x13, 0x1a, 0x01, 0xe6, 0x3e, 0x0b,
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diff --git a/roms/u-boot/board/esd/cpci405/fpgadata_cpci4052.c b/roms/u-boot/board/esd/cpci405/fpgadata_cpci4052.c
new file mode 100644
index 00000000..bedbb1f7
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/fpgadata_cpci4052.c
@@ -0,0 +1,1529 @@
+0x1f, 0x8b, 0x08, 0x08, 0xe9, 0xf4, 0x75, 0x3e,
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+0x6e, 0x9e, 0xeb, 0xff, 0x01, 0x51, 0x16, 0x5f,
+0xd0, 0xd5, 0x60, 0x00, 0x00,
diff --git a/roms/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c b/roms/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c
new file mode 100644
index 00000000..acbc6965
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci405/fpgadata_cpci405ab.c
@@ -0,0 +1,2569 @@
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+0x9b, 0xff, 0xc6, 0x4f, 0xfd, 0xd8, 0xd8, 0x98,
+0x79, 0x71, 0xe3, 0xff, 0xd3, 0x6d, 0x48, 0xf6,
+0x12, 0x1e, 0x6f, 0x64, 0x1a, 0x89, 0xa5, 0x37,
+0xf1, 0x5d, 0x1d, 0xbf, 0x06, 0xff, 0x0b, 0x6b,
+0x59, 0xbb, 0x88, 0xe1, 0x7c, 0xbe, 0x74, 0x2d,
+0xdb, 0x0d, 0xbe, 0x7c, 0x05, 0x66, 0x5a, 0xa9,
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+0x3f, 0xb6, 0x96, 0x9d, 0x36, 0x7f, 0xe4, 0xf9,
+0x8c, 0x5b, 0xcb, 0xc0, 0xd7, 0xb2, 0xb5, 0x84,
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+0x0c, 0x71, 0xbe, 0xc8, 0xe7, 0xab, 0xb5, 0xfc,
+0xff, 0xbe, 0x36, 0xff, 0xf9, 0x27, 0x04, 0xba,
+0x44, 0xf8, 0xff, 0x46, 0xae, 0xff, 0x2f, 0xfe,
+0xd3, 0xaf, 0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c,
+0xf5, 0xf9, 0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf,
+0x57, 0x9f, 0xff, 0x5f, 0x7c, 0x78, 0xbc, 0x44,
+0x78, 0xbc, 0x64, 0xfc, 0x3f, 0xdd, 0x97, 0xaf,
+0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c, 0xf5, 0xf9,
+0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf, 0x57, 0x9f,
+0xff, 0xbb, 0x3f, 0x21, 0x2e, 0x0c, 0x7b, 0xa3,
+0x36, 0x04, 0xbc, 0xa8, 0x2b, 0x87, 0xc0, 0xc8,
+0xfb, 0xd3, 0xfe, 0x1d, 0x6f, 0xef, 0x0a, 0x41,
+0x42, 0xca, 0xdc, 0xa7, 0xe7, 0x1f, 0x27, 0xf6,
+0xf5, 0xff, 0x02, 0xd6, 0x2c, 0x67, 0x26, 0xbd,
+0xa4, 0x00, 0x00,
diff --git a/roms/u-boot/board/esd/cpci5200/Makefile b/roms/u-boot/board/esd/cpci5200/Makefile
new file mode 100644
index 00000000..8421f548
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci5200/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
+
+# obj-y	= cpci5200.o flash.o $(CPLD)
+obj-y	= cpci5200.o strataflash.o
diff --git a/roms/u-boot/board/esd/cpci5200/cpci5200.c b/roms/u-boot/board/esd/cpci5200/cpci5200.c
new file mode 100644
index 00000000..8bded0bb
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci5200/cpci5200.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_ata_reset();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPCI5200 (cpci5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+	}
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_ata_reset(void)
+{
+	debug("init_ata_reset\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "Write some data to pcibus",
+	   "<addr> <size>\n"
+	   ""
+);
diff --git a/roms/u-boot/board/esd/cpci5200/mt46v16m16-75.h b/roms/u-boot/board/esd/cpci5200/mt46v16m16-75.h
new file mode 100644
index 00000000..63a40323
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/roms/u-boot/board/esd/cpci5200/strataflash.c b/roms/u-boot/board/esd/cpci5200/strataflash.c
new file mode 100644
index 00000000..7dc2e58c
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci5200/strataflash.c
@@ -0,0 +1,786 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+			 uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+			       cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 8) |
+		addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 24) |
+		(addr[(info->portwidth) - 1] << 16) |
+		(addr[(4 * info->portwidth) - 1] << 8) |
+		addr[(3 * info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+	unsigned long address;
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CONFIG_SYS_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CONFIG_SYS_FLASH_INCREMENT;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, flash_info[0].size, flash_info[i].size << 20);
+		}
+	}
+
+#if 0				/* test-only */
+	/* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for (i = 0;
+	     flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
+	     i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth << 3), (info->chipwidth << 3));
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	printf
+	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	     info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+	     info->buffer_size);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n");
+		printf(" %08lX%5s",
+		       info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif				/* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check(info, sector, info->erase_blk_tout,
+				     prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+			      char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt,
+			       info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,
+		       info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf("Command Sequence Error.\n");
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *) cmdbuf;
+	for (i = 0; i < info->portwidth; i++)
+		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+					FLASH_CMD_CFI);
+			if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+					     'R')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+					     'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio = 0;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+#if 0
+	invalidate_dcache_range(base, base + 0x400);
+#endif
+	if (flash_detect_cfi(info)) {
+
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions =
+		    flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp =
+			    flash_read_long(info, 0,
+					    FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size =
+			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) + 1;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+				    flash_isset(info, sect_cnt,
+						FLASH_OFFSET_PROTECT,
+						FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+		    size_ratio;
+		info->buffer_size =
+		    (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+		    1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+#ifdef DEBUG_FLASH
+	printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t cptr;
+	int flag;
+
+	cptr.cp = (uchar *)dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t * info, ulong addr)
+{
+	int sector;
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					  "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0,
+				FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+		    flash_full_status_check(info, sector,
+					    info->buffer_write_tout,
+					    "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif				/* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/roms/u-boot/board/esd/cpci750/64360.h b/roms/u-boot/board/esd/cpci750/64360.h
new file mode 100644
index 00000000..92133f0b
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/64360.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ * for cpci750 Reinhard Arlt
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * main board support/init for the cpci750.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
diff --git a/roms/u-boot/board/esd/cpci750/Makefile b/roms/u-boot/board/esd/cpci750/Makefile
new file mode 100644
index 00000000..a3300c9f
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= misc.o
+obj-y	+= cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
+	  mv_eth.o  mpsc.o i2c.o \
+	  sdram_init.o ide.o
diff --git a/roms/u-boot/board/esd/cpci750/cpci750.c b/roms/u-boot/board/esd/cpci750/cpci750.c
new file mode 100644
index 00000000..fcaf3e67
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/cpci750.c
@@ -0,0 +1,1088 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ */
+
+/*
+ * cpci750.c - main board support/init for the esd cpci750.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
+				     {"PCI0DLL_1     "},  /* 30 */
+				     {"PCI0DLL_0     "},  /* 29 */
+				     {"PCI1DLL_2     "},  /* 28 */
+				     {"PCI1DLL_1     "},  /* 27 */
+				     {"PCI1DLL_0     "},  /* 26 */
+				     {"BbEP2En       "},  /* 25 */
+				     {"SDRAMRdDataDel"},  /* 24 */
+				     {"SDRAMRdDel    "},  /* 23 */
+				     {"SDRAMSync     "},  /* 22 */
+				     {"SDRAMPipeSel_1"},  /* 21 */
+				     {"SDRAMPipeSel_0"},  /* 20 */
+				     {"SDRAMAddDel   "},  /* 19 */
+				     {"SDRAMClkSel   "},  /* 18 */
+				     {"Reserved(1!)  "},  /* 17 */
+				     {"PCIRty        "},  /* 16 */
+				     {"BootCSWidth_1 "},  /* 15 */
+				     {"BootCSWidth_0 "},  /* 14 */
+				     {"PCI1PadsCal   "},  /* 13 */
+				     {"PCI0PadsCal   "},  /* 12 */
+				     {"MultiMVId_1   "},  /* 11 */
+				     {"MultiMVId_0   "},  /* 10 */
+				     {"MultiGTEn     "},  /* 09 */
+				     {"Int60xArb     "},  /* 08 */
+				     {"CPUBusConfig_1"},  /* 07 */
+				     {"CPUBusConfig_0"},  /* 06 */
+				     {"DefIntSpc     "},  /* 05 */
+				     {0               },  /* 04 */
+				     {"SROMAdd_1     "},  /* 03 */
+				     {"SROMAdd_0     "},  /* 02 */
+				     {"DRAMPadCal    "},  /* 01 */
+				     {"SInitEn       "},  /* 00 */
+				     {0               },  /* 31 */
+				     {0               },  /* 30 */
+				     {0               },  /* 29 */
+				     {0               },  /* 28 */
+				     {0               },  /* 27 */
+				     {0               },  /* 26 */
+				     {0               },  /* 25 */
+				     {0               },  /* 24 */
+				     {0               },  /* 23 */
+				     {0               },  /* 22 */
+				     {"JTAGCalBy     "},  /* 21 */
+				     {"GB2Sel        "},  /* 20 */
+				     {"GB1Sel        "},  /* 19 */
+				     {"DRAMPLL_MDiv_5"},  /* 18 */
+				     {"DRAMPLL_MDiv_4"},  /* 17 */
+				     {"DRAMPLL_MDiv_3"},  /* 16 */
+				     {"DRAMPLL_MDiv_2"},  /* 15 */
+				     {"DRAMPLL_MDiv_1"},  /* 14 */
+				     {"DRAMPLL_MDiv_0"},  /* 13 */
+				     {"GB0Sel        "},  /* 12 */
+				     {"DRAMPLLPU     "},  /* 11 */
+				     {"DRAMPLL_HIKVCO"},  /* 10 */
+				     {"DRAMPLLNP     "},  /* 09 */
+				     {"DRAMPLL_NDiv_7"},  /* 08 */
+				     {"DRAMPLL_NDiv_6"},  /* 07 */
+				     {"CPUPadCal     "},  /* 06 */
+				     {"DRAMPLL_NDiv_5"},  /* 05 */
+				     {"DRAMPLL_NDiv_4"},  /* 04 */
+				     {"DRAMPLL_NDiv_3"},  /* 03 */
+				     {"DRAMPLL_NDiv_2"},  /* 02 */
+				     {"DRAMPLL_NDiv_1"},  /* 01 */
+				     {"DRAMPLL_NDiv_0"}}; /* 00 */
+
+extern flash_info_t flash_info[];
+
+extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+int display_mem_map (void);
+
+/*
+ * Skip video initialization on slave variant.
+ * This function will overwrite the weak default in cfb_console.c
+ */
+int board_video_skip(void)
+{
+	return CPCI750_SLAVE_TEST;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int data;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++) {
+		data = pciReadConfigReg(stat,
+					PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+					SELF);
+		data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, data);
+	}
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+
+	memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+
+	/* configure device timing */
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
+
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CONFIG_SYS_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CONFIG_SYS_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
+		unsigned int flash_offset;
+		unsigned int l;
+
+		flash_offset =  CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
+		for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
+			if (flash_info[3].start[l] != 0) {
+			      flash_info[3].start[l] += flash_offset;
+			}
+		}
+		flash_protect (FLAG_PROTECT_SET,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len  - 1,
+			       &flash_info[3]);
+	}
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
+			      CONFIG_SYS_BOOT_SIZE);
+
+	display_mem_map ();
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- FLASH\n");
+		else if (i == 1)
+			printf ("\t- FLASH\n");
+		else if (i == 2)
+			printf ("\t- FLASH\n");
+		else
+			printf ("\t- RTC/REGS/CAN\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	volatile unsigned int *ptr;
+	int count = 0;
+	int count2 = 0;
+	int status = 0;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	ptr[0] = 0xffffffff;
+	ptr[1] = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	sprintf(addr, "%08x", *ptr);
+	printf("\nBooting Image at addr 0x%s ...\n", addr);
+	setenv("loadaddr", addr);
+
+	switch (ptr[1] == 0) {
+	case 0:
+		/*
+		 * Boot image via bootm
+		 */
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootm (cmdtp, 0, 1, local_args);
+		break;
+	case 1:
+		/*
+		 * Boot image via bootvx
+		 */
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootvx (cmdtp, 0, 1, local_args);
+		break;
+	}
+
+	return status;
+}
+
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"loadpci - Wait for pci-image and boot it\n",
+	NULL
+	);
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CONFIG_SYS_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0		*/
+	return;
+}
+
+
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaLL,
+	0xccccccccccccccccLL,
+	0xf0f0f0f0f0f0f0f0LL,
+	0xff00ff00ff00ff00LL,
+	0xffff0000ffff0000LL,
+	0xffffffff00000000LL,
+	0x00000000ffffffffLL,
+	0x0000ffff0000ffffLL,
+	0x00ff00ff00ff00ffLL,
+	0x0f0f0f0f0f0f0f0fLL,
+	0x3333333333333333LL,
+	0x5555555555555555LL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;		*/
+		/* lo = temp64 & 0xffffffff;			*/
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo);	*/
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
+
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
+
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	rundata = getenv_yesno("testdramdata") == 1;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	runaddress = getenv_yesno("testdramaddress") == 1;
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	runwalk = getenv_yesno("testdramwalk") == 1;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+	}
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function		*/
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.						*/
+/*  - we diable and invalidate the icache and dcache.			*/
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+/*	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
+/*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
+
+	icache_disable ();
+	dcache_disable ();
+}
+
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int reset_sample_low;
+	unsigned int reset_sample_high;
+	unsigned int l, l1, l2;
+
+	GT_REG_READ(0x3c4, &reset_sample_low);
+	GT_REG_READ(0x3d4, &reset_sample_high);
+	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+
+	l2 = 0;
+	for (l=0; l<63; l++) {
+		if (show_config_tab[l][0] != 0) {
+			printf("%14s:%1x ", show_config_tab[l],
+			       ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+			l2++;
+			if ((l2 % 4) == 0)
+				printf("\n");
+		} else {
+			l1++;
+		}
+		if (l == 32)
+			reset_sample_low = reset_sample_high;
+	}
+	printf("\n");
+
+	return(0);
+}
+
+U_BOOT_CMD(
+	show_config,	1,	1,	do_show_config,
+	"Show Marvell strapping register",
+	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
+);
+
+int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pldver, 1, 1, do_pldver,
+	"Show PLD version",
+	"Show PLD version)");
+
+int board_eth_init(bd_t *bis)
+{
+	return mv6436x_eth_initialize(bis);
+}
diff --git a/roms/u-boot/board/esd/cpci750/eth.h b/roms/u-boot/board/esd/cpci750/eth.h
new file mode 100644
index 00000000..4e427683
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/eth.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+int mv6436x_eth_initialize(bd_t *);
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/roms/u-boot/board/esd/cpci750/i2c.c b/roms/u-boot/board/esd/cpci750/i2c.c
new file mode 100644
index 00000000..bad0dac0
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/i2c.c
@@ -0,0 +1,475 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ * for cpci750 by reinhard.arlt@esd-electronics.com
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <i2c.h>
+#include "../../Marvell/include/mv_gen_reg.h"
+#include "../../Marvell/include/core.h"
+
+#define I2C_DELAY	    100
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CONFIG_SYS_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+	/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+	asm(" sync");
+	GT_REG_WRITE (I2C_CONTROL, 0);
+	asm(" sync");
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	asm(" sync");
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+	asm(" sync");
+}
+
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	unsigned int control;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |=  (0x1 << 2);
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+
+	count = 0;
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to set startbit: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			asm(" sync");
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	DP (puts ("i2c_select_device:write addr byte\n"));
+
+	/* assert the address */
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write address: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		asm(" sync");
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		RESET_REG_BITS (I2C_CONTROL, BIT3);
+		asm(" sync");
+
+		/* Get and return the data */
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			if (count > 20) {
+#ifdef DEBUG_I2C
+				printf ("Failed to get data len status: 0x%02x\n", status);
+#endif
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	asm(" sync");
+	count = 0;
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	while ((status & 0xff) != 0x58) {
+		if (count > 2000) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+	asm(" sync");
+
+	return (0);
+}
+
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		count = 0;
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		count = 0;
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+	table[1] = (offset     ) & 0x0ff;	/* low byte */
+	table[0] = (offset >> 8) & 0x0ff;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+22		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+int
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device for data read: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not read: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+	asm(" sync");
+}
+
+
+int
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+		}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+		}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+
+int i2c_probe (uchar chip)
+{
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	/* set the i2c frequency */
+	i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
diff --git a/roms/u-boot/board/esd/cpci750/i2c.h b/roms/u-boot/board/esd/cpci750/i2c.h
new file mode 100644
index 00000000..a879ea93
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/i2c.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/roms/u-boot/board/esd/cpci750/ide.c b/roms/u-boot/board/esd/cpci750/ide.c
new file mode 100644
index 00000000..f555c084
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/ide.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/* ide.c - ide support functions */
+
+
+#include <common.h>
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+int cpci_hd_type;
+
+int ata_device(int dev)
+{
+	int retval;
+
+	retval = (dev & 1) << 4;
+	if (cpci_hd_type == 2)
+		retval ^= 1 << 4;
+	return retval;
+}
+
+
+int ide_preinit (void)
+{
+	int status;
+	pci_dev_t devbusfn;
+	int l;
+
+	status = 1;
+	cpci_hd_type = 0;
+	if (CPCI750_SLAVE_TEST != 0)
+		return status;
+	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
+		ide_bus_offset[l] = -ATA_STATUS;
+	}
+	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn != -1) {
+		cpci_hd_type = 1;
+	} else {
+		devbusfn = pci_find_device (0x1095, 0x3114, 0);
+		if (devbusfn != -1) {
+			cpci_hd_type = 2;
+		}
+	}
+	if (devbusfn != -1) {
+		ulong *ide_bus_offset_ptr;
+
+		status = 0;
+
+		ide_bus_offset_ptr = &ide_bus_offset[0];
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+				       (u32 *)ide_bus_offset_ptr);
+		ide_bus_offset[0] &= 0xfffffffe;
+		ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
+		ide_bus_offset_ptr = &ide_bus_offset[1];
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+				       (u32 *)ide_bus_offset_ptr);
+		ide_bus_offset[1] &= 0xfffffffe;
+		ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
+	}
+	return status;
+}
+
+void ide_set_reset (int flag) {
+	return;
+}
+
+#endif /* of CONFIG_CMDS_IDE */
diff --git a/roms/u-boot/board/esd/cpci750/local.h b/roms/u-boot/board/esd/cpci750/local.h
new file mode 100644
index 00000000..084f99f7
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/local.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells PPCBoot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! PPCBOOT figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+#define CONFIG_750FX       /* The 750FX doesn't support as many things in L2CR like 750CX*/
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CONFIG_SYS_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+/* #define CONFIG_ETHADDR          86:06:2d:7e:c6:53 */
+#define CONFIG_ETHADDR          64:36:00:00:00:01
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
diff --git a/roms/u-boot/board/esd/cpci750/misc.S b/roms/u-boot/board/esd/cpci750/misc.S
new file mode 100644
index 00000000..233fd83b
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CONFIG_SYS_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
+	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
diff --git a/roms/u-boot/board/esd/cpci750/mpsc.c b/roms/u-boot/board/esd/cpci750/mpsc.c
new file mode 100644
index 00000000..a1587745
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/mpsc.c
@@ -0,0 +1,1002 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../../Marvell/include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64360 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       true for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/roms/u-boot/board/esd/cpci750/mpsc.h b/roms/u-boot/board/esd/cpci750/mpsc.h
new file mode 100644
index 00000000..241f28a3
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/mpsc.h
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../../Marvell/include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/roms/u-boot/board/esd/cpci750/mv_eth.c b/roms/u-boot/board/esd/cpci750/mv_eth.c
new file mode 100644
index 00000000..cbdcfe33
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/mv_eth.c
@@ -0,0 +1,3131 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64360_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64360_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64360_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64360_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64360 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64360_eth_real_open (struct eth_device *eth);
+static int mv64360_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64360_eth_update_stat (struct eth_device *dev);
+bool db64360_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64360_eth_receive (struct eth_device *dev);
+
+int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64360_eth_print_stat (struct eth_device *dev);
+#endif
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64360_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64360_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64360_eth
+ *
+ **********************************************************************/
+int db64360_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64360_eth_start (dev));
+}
+
+int db64360_eth_poll (struct eth_device *dev)
+{
+	return mv64360_eth_receive (dev);
+}
+
+int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
+{
+	mv64360_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64360_eth_disable (struct eth_device *dev)
+{
+	mv64360_eth_stop (dev);
+}
+
+
+void mv6436x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than sizeof(dev->name) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64360_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64360_eth_transmit;
+		dev->recv = (void *) db64360_eth_poll;
+
+		ethernet_private =
+			calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *) ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private =
+			calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64360_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64360_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_f(s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64360_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64360_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64360_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64360_eth_open (struct eth_device *dev)
+{
+	return (mv64360_eth_real_open (dev));
+}
+
+/* Helper function for mv64360_eth_open */
+static int mv64360_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	u32 phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64360_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64360_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64360_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64360_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64360_eth_stop (struct eth_device *dev)
+{
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64360_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64360_eth_stop */
+
+static int mv64360_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64360_eth_free_tx_rings (dev);
+	mv64360_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64360_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64360_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64360_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64360_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64360_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+
+	mv64360_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	(void)eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	(void)eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64360_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64360_eth_start (struct eth_device *dev)
+{
+	return (mv64360_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4) {
+		(void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+	}
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/roms/u-boot/board/esd/cpci750/mv_eth.h b/roms/u-boot/board/esd/cpci750/mv_eth.h
new file mode 100644
index 00000000..c04fb58a
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/mv_eth.h
@@ -0,0 +1,819 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include <asm/errno.h>
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */
diff --git a/roms/u-boot/board/esd/cpci750/mv_regs.h b/roms/u-boot/board/esd/cpci750/mv_regs.h
new file mode 100644
index 00000000..9a54a976
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/mv_regs.h
@@ -0,0 +1,1108 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/********************************************************************************
+* gt64360r.h - GT-64360 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64360
+
+/* Supported by the Atlantis */
+#define MV64360_INCLUDE_PCI_1
+#define MV64360_INCLUDE_PCI_0_ARBITER
+#define MV64360_INCLUDE_PCI_1_ARBITER
+#define MV64360_INCLUDE_SNOOP_SUPPORT
+#define MV64360_INCLUDE_P2P
+#define MV64360_INCLUDE_ETH_PORT_2
+#define MV64360_INCLUDE_CPU_MAPPING
+#define MV64360_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64360_CS_0_BASE_ADDR					    0x008
+#define MV64360_CS_0_SIZE					    0x010
+#define MV64360_CS_1_BASE_ADDR					    0x208
+#define MV64360_CS_1_SIZE					    0x210
+#define MV64360_CS_2_BASE_ADDR					    0x018
+#define MV64360_CS_2_SIZE					    0x020
+#define MV64360_CS_3_BASE_ADDR					    0x218
+#define MV64360_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64360_PCI_0_IO_SIZE					    0x050
+#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64360_PCI_1_IO_SIZE					    0x098
+#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64360_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64360_CPU_CONFIG					    0x000
+#define MV64360_CPU_MODE					    0x120
+#define MV64360_CPU_MASTER_CONTROL				    0x160
+#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64360_SMP_WHO_AM_I					    0x200
+#define MV64360_SMP_CPU0_DOORBELL				    0x214
+#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64360_SMP_CPU1_DOORBELL				    0x224
+#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64360_SMP_SEMAPHOR0					    0x244
+#define MV64360_SMP_SEMAPHOR1					    0x24c
+#define MV64360_SMP_SEMAPHOR2					    0x254
+#define MV64360_SMP_SEMAPHOR3					    0x25c
+#define MV64360_SMP_SEMAPHOR4					    0x264
+#define MV64360_SMP_SEMAPHOR5					    0x26c
+#define MV64360_SMP_SEMAPHOR6					    0x274
+#define MV64360_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64360_CPU_ERROR_DATA_LOW				    0x128
+#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64360_CPU_ERROR_PARITY				    0x138
+#define MV64360_CPU_ERROR_CAUSE					    0x140
+#define MV64360_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64360_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64360_SRAM_CONFIG					    0x380
+#define MV64360_SRAM_TEST_MODE					    0X3F4
+#define MV64360_SRAM_ERROR_CAUSE				    0x388
+#define MV64360_SRAM_ERROR_ADDR					    0x390
+#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64360_SDRAM_CONFIG					    0x1400
+#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64360_SDRAM_OPERATION					    0x1418
+#define MV64360_SDRAM_MODE					    0x141c
+#define MV64360_EXTENDED_DRAM_MODE				    0x1420
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64360_SDRAM_ERROR_ADDR				    0x1450
+#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64360_SDRAM_ECC_CONTROL				    0x1454
+#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64360_DFCDL_CONFIG0					    0x1480
+#define MV64360_DFCDL_CONFIG1					    0x1484
+#define MV64360_DLL_WRITE					    0x1488
+#define MV64360_DLL_READ					    0x148c
+#define MV64360_SRAM_ADDR					    0x1490
+#define MV64360_SRAM_DATA0					    0x1494
+#define MV64360_SRAM_DATA1					    0x1498
+#define MV64360_SRAM_DATA2					    0x149c
+#define MV64360_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64360_DUNIT_DEBUG_LOW					    0x1460
+#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64360_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64360_DEVICE_ERROR_DATA				    0x4dc
+#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64360_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64360_PCI_0_COMMAND					    0xc00
+#define MV64360_PCI_1_COMMAND					    0xc80
+#define MV64360_PCI_0_MODE					    0xd00
+#define MV64360_PCI_1_MODE					    0xd80
+#define MV64360_PCI_0_RETRY					    0xc04
+#define MV64360_PCI_1_RETRY					    0xc84
+#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_SERR_MASK					    0xc28
+#define MV64360_PCI_1_SERR_MASK					    0xca8
+#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_MMASK					    0X1D24
+#define MV64360_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64360_PCI_VPD_ADDR					    0x048
+#define MV64360_PCI_VPD_DATA					    0x04c
+#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64360_PCI_X_COMMAND					    0x060
+#define MV64360_PCI_X_STATUS					    0x064
+#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64360_ETH_PHY_ADDR_REG				    0x2000
+#define MV64360_ETH_SMI_REG					    0x2004
+#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64360_ETH_BAR_0					    0x2200
+#define MV64360_ETH_BAR_1					    0x2208
+#define MV64360_ETH_BAR_2					    0x2210
+#define MV64360_ETH_BAR_3					    0x2218
+#define MV64360_ETH_BAR_4					    0x2220
+#define MV64360_ETH_BAR_5					    0x2228
+#define MV64360_ETH_SIZE_REG_0					    0x2204
+#define MV64360_ETH_SIZE_REG_1					    0x220c
+#define MV64360_ETH_SIZE_REG_2					    0x2214
+#define MV64360_ETH_SIZE_REG_3					    0x221c
+#define MV64360_ETH_SIZE_REG_4					    0x2224
+#define MV64360_ETH_SIZE_REG_5					    0x222c
+#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64360_CUNIT_SIZE0					    0xf204
+#define MV64360_CUNIT_SIZE1					    0xf20c
+#define MV64360_CUNIT_SIZE2					    0xf214
+#define MV64360_CUNIT_SIZE3					    0xf21c
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64360_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64360_CUNIT_CONFIG_REG				    0xb40c
+#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64360_CUNIT_DEBUG_LOW					    0xf340
+#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64360_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64360_MPSC_ROUTING_REG				    0xb400
+#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64360_SDMA_CAUSE_REG					    0xb800
+#define MV64360_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64360_SDMA_SRAM_TARGET				    0x0003
+#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64360_PCI_0_TARGET					    0x0003
+#define MV64360_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64360_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64360_BRG_CAUSE_REG					    0xb834
+#define MV64360_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64360_DMA_SIZE_REG0					    0xa04
+#define MV64360_DMA_SIZE_REG1					    0xa0c
+#define MV64360_DMA_SIZE_REG2					    0xa14
+#define MV64360_DMA_SIZE_REG3					    0xa1c
+#define MV64360_DMA_SIZE_REG4					    0xa24
+#define MV64360_DMA_SIZE_REG5					    0xa2c
+#define MV64360_DMA_SIZE_REG6					    0xa34
+#define MV64360_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64360_DMA_ARBITER_CONTROL				    0x860
+#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64360_DMA_ERROR_ADDR					    0x8c8
+#define MV64360_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64360_DMA_DEBUG_LOW					    0x8e0
+#define MV64360_DMA_DEBUG_HIGH					    0x8e4
+#define MV64360_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64360_TIMER_COUNTER0					    0x850
+#define MV64360_TIMER_COUNTER1					    0x854
+#define MV64360_TIMER_COUNTER2					    0x858
+#define MV64360_TIMER_COUNTER3					    0x85C
+#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64360_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64360_I2C_SLAVE_ADDR					    0xc000
+#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64360_I2C_DATA					    0xc004
+#define MV64360_I2C_CONTROL					    0xc008
+#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64360_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_GPP_IO_CONTROL					    0xf100
+#define MV64360_GPP_LEVEL_CONTROL				    0xf110
+#define MV64360_GPP_VALUE					    0xf104
+#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64360_GPP_VALUE_SET					    0xf118
+#define MV64360_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_MPP_CONTROL0					    0xf000
+#define MV64360_MPP_CONTROL1					    0xf004
+#define MV64360_MPP_CONTROL2					    0xf008
+#define MV64360_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64360_SERIAL_INIT_CONTROL				    0xf328
+#define MV64360_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64360rh */
diff --git a/roms/u-boot/board/esd/cpci750/pci.c b/roms/u-boot/board/esd/cpci750/pci.c
new file mode 100644
index 00000000..59f170a0
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/pci.c
@@ -0,0 +1,1028 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+
+#include "../../Marvell/include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+	unsigned int base;
+	unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*		    - Make sure the GT is configured as a master before writing
+*		      to another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*		   (or any other PCI device spec)
+*	    pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*		    - Make sure the GT is configured as a master before reading
+*		      from another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			spec)
+*	    pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*				the agent is placed on another Bus. For more
+*				information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*	    GT spec (or any other PCI device spec).
+*	    unsigned int pciDevNum - The device number needs to be addressed.
+*	    unsigned int busNum - On which bus does the Target agent connect
+*				  to.
+*	    unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*				the agent target locate on another PCI bus.
+*			      - Make sure the GT is configured as a master
+*				before reading from another device on the PCI.
+*			      - The function takes care of Big/Little endian
+*				conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			 spec). (configuration register offset.)
+*	    pciDevNum: The device number needs to be addressed.
+*	    busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*	    - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*			  feature bits given as an input.
+*			- Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*	  unsigned int features - See file: pci.h there are defintion for those
+*				  region features.
+*	  unsigned int baseAddress - The region base Address.
+*	  unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*			    to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*		       disable the park on last mechanism for each agent.
+*		       disabling this option for all agents results parking
+*		       on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*			respond to grant assertion within a window specified in
+*			the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*			grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*			    Detection mechanism.
+*			    NOTE: This operation may cause a dead lock on the
+*			    pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*		  For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*				       Boundry.
+*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*				       Boundry.
+*	   unsigned int busNum - The CPI bus number to which the PCI interface
+*				       is connected.
+*	   unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*			   supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*	  snoopType - There is four optional Types:
+*			 1. No Snoop.
+*			 2. Snoop to WT region.
+*			 3. Snoop to WB region.
+*			 4. Snoop & Invalidate to WB region.
+*	  baseAddress - Base Address of this region.
+*	  regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
+					   offset | (PCI_FUNC(dev) << 8),
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr,
+						     offset | (PCI_FUNC(dev) << 8),
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+				   offset | (PCI_FUNC(dev) << 8),
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset | (PCI_FUNC(dev) << 8),
+					     PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					     0x0);
+		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					    &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					     bar_value);
+	}
+}
+
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *entry)
+{
+	u32		  bar_value, pci_response;
+
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
+	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+	gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+	unsigned char	  data;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return(0);
+		}
+	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+	return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+	unsigned int	  off;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return;
+	}
+	off = data;
+	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+	in8(off);
+	return;
+}
+#endif
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+	unsigned int slave;
+#ifdef CONFIG_PCI_PNP
+	unsigned int bar;
+#endif
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+#ifdef CONFIG_USE_CPCIDVI
+	gt_cpcidvi_rom.init = 0;
+	gt_cpcidvi_rom.base = 0;
+#endif
+
+	slave = CPCI750_SLAVE_TEST;
+
+	pci0_hose.config_table = gt_config_table;
+	pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+	gt_config_table[0].config_device =  gt_setup_cpcidvi;
+#endif
+	gt_config_table[1].config_device =  gt_setup_ide;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	if (slave == 0) {
+		pciArbiterEnable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+		pciauto_config_init(&pci0_hose);
+		pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+#endif
+#ifdef CONFIG_PCI_SCAN_SHOW
+		printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+		pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
+							  pci0_hose.first_busno);
+
+#ifdef DEBUG
+		gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	} else {
+		pciArbiterDisable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		pci0_hose.last_busno = pci0_hose.first_busno;
+	}
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci1_hose);
+	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
+#endif
+	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
+#endif /* of CONFIG_PCI */
diff --git a/roms/u-boot/board/esd/cpci750/sdram_init.c b/roms/u-boot/board/esd/cpci750/sdram_init.c
new file mode 100644
index 00000000..89f94aa6
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/sdram_init.c
@@ -0,0 +1,1702 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64360 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ *
+ * adaption for the cpci750 Board
+ * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
+ *************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../../Marvell/common/i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int set_dfcdlInit(void);	/* setup delay line of Mv64360 */
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank(unsigned int bankNo,
+		unsigned int bankBase,
+		unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf("mapping bank %d at %08x - %08x\n",
+		       bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank(bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
+		const int features=
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 |
+			PCI_NO_SWAP;
+
+		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
+				bankLength);
+
+		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB	   (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
+
+typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+				SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+			       } VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;			/* ECC , PARITY.. */
+	unsigned int sdramWidth;			/* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;		/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;		/* measured in ns */
+
+	int addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;			/* (measured in ns/100) */
+	int dataInputSetupTime;				/* LoP left of point (measured in ns) */
+	int dataInputHoldTime;				/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;		/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;			/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;					/* DRAM size in n*64Mbit */
+	uchar slot;					/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];			/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];				/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];				/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;			/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;			/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;			/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;				/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NS10to10PS(unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return(ns*100 + ns10*10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NSto10PS(unsigned char spd_byte)
+{
+	return(spd_byte*100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, tras_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	memset (data, 0, sizeof (data));
+
+
+	ret = 0;
+
+	debug("before i2c read\n");
+
+	ret = i2c_read (addr, 0, 2, data, 128);
+
+	debug("after i2c read\n");
+
+	if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
+	    || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
+	    || (data[70] != 'b') || (data[71] != 'h')) {
+		ret = -1;
+	}
+
+	if ((ret != 0) && (slot == 0)) {
+		memset (data, 0, sizeof (data));
+		data[0] = 0x80;
+		data[1] = 0x08;
+		data[2] = 0x07;
+		data[3] = 0x0c;
+		data[4] = 0x09;
+		data[5] = 0x01;
+		data[6] = 0x48;
+		data[7] = 0x00;
+		data[8] = 0x04;
+		data[9] = 0x75;
+		data[10] = 0x80;
+		data[11] = 0x02;
+		data[12] = 0x80;
+		data[13] = 0x10;
+		data[14] = 0x08;
+		data[15] = 0x01;
+		data[16] = 0x0e;
+		data[17] = 0x04;
+		data[18] = 0x0c;
+		data[19] = 0x01;
+		data[20] = 0x02;
+		data[21] = 0x20;
+		data[22] = 0x00;
+		data[23] = 0xa0;
+		data[24] = 0x80;
+		data[25] = 0x00;
+		data[26] = 0x00;
+		data[27] = 0x50;
+		data[28] = 0x3c;
+		data[29] = 0x50;
+		data[30] = 0x32;
+		data[31] = 0x10;
+		data[32] = 0xb0;
+		data[33] = 0xb0;
+		data[34] = 0x60;
+		data[35] = 0x60;
+		data[64] = 'e';
+		data[65] = 's';
+		data[66] = 'd';
+		data[67] = '-';
+		data[68] = 'g';
+		data[69] = 'm';
+		data[70] = 'b';
+		data[71] = 'h';
+		ret = 0;
+	}
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		debug("No DIMM in slot %d [err = %x]\n", slot, ret);
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+	/* find Manufacturer of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by:		%s\n",
+		dimmInfo->manufactura);
+
+	/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is:		%s\n",
+		dimmInfo->modul_id);
+
+	/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is:		%s\n",
+		dimmInfo->vendor_data);
+
+	/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+	/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+	/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+	/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is:		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+#if 0				/* test-only */
+	spd_checksum = 0;
+
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+#endif /* test-only */
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2:	/* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				debug("Dram_type in slot %d is:			SDRAM\n",
+				     dimmInfo->slot);
+			if (dimmInfo->memoryType == 1)
+				debug("Dram_type in slot %d is:			DDRAM\n",
+				     dimmInfo->slot);
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3:	/* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			debug("Module Number of row addresses:		%d\n",
+			     dimmInfo->numOfRowAddresses);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4:	/* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			debug("Module Number of col addresses:		%d\n",
+			     dimmInfo->numOfColAddresses);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5:	/* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			debug("Number of Banks on Mod. : 				%d\n",
+			     dimmInfo->numOfModuleBanks);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6:	/* Data Width */
+			dimmInfo->dataWidth = data[i];
+			debug("Module Data Width:				%d\n",
+			     dimmInfo->dataWidth);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8:	/* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				debug("Module is 					TTL_5V_TOLERANT\n");
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				debug("Module is 					LVTTL\n");
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				debug("Module is 					TTL_5V_TOLERANT\n");
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				debug("Module is 					HSTL_1_5V\n");
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				debug("Module is 					SSTL_2_5V\n");
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				debug("Module is 					VOLTAGE_UNKNOWN\n");
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9:	/* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			debug("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			debug("Clock To Data Out:				%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+#ifdef CONFIG_MV64360_ECC
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			debug("Error Check Type (0=NONE):			%d\n",
+			     dimmInfo->errorCheckType);
+			break;
+#endif /* of ifdef CONFIG_MV64360_ECC */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			debug("Sdram Width:					%d\n",
+			     dimmInfo->sdramWidth);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			debug("Error Check Data Width:			%d\n",
+			     dimmInfo->errorCheckDataWidth);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			debug("Minimum Clock Delay:				%d\n",
+			     dimmInfo->minClkDelay);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8   |  4	 |   2	|   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			debug("Burst Length Supported:			");
+			if (dimmInfo->burstLengthSupported & 0x01)
+				debug("1, ");
+			if (dimmInfo->burstLengthSupported & 0x02)
+				debug("2, ");
+			if (dimmInfo->burstLengthSupported & 0x04)
+				debug("4, ");
+			if (dimmInfo->burstLengthSupported & 0x08)
+				debug("8, ");
+			debug(" Bit \n");
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			debug("Number Of Banks On Each Chip:			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	| TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	|  7   |  6   |  5   |	4   |  3   |   2  |   1  *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			debug("Suported Cas Latencies: (CL)			");
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						debug("%d,			",
+						     k + 1);
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					debug("1, ");
+				if (dimmInfo->suportedCasLatencies & 2)
+					debug("1.5, ");
+				if (dimmInfo->suportedCasLatencies & 4)
+					debug("2, ");
+				if (dimmInfo->suportedCasLatencies & 8)
+					debug("2.5, ");
+				if (dimmInfo->suportedCasLatencies & 16)
+					debug("3, ");
+				if (dimmInfo->suportedCasLatencies & 32)
+					debug("3.5, ");
+
+			}
+			debug("\n");
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							debug("Max. Cas Latencies (DDR): 			ERROR !!!\n");
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							debug("Max. Cas Latencies (DDR): 			ERROR !!!\n");
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							debug("Max. Cas Latencies (DDR): 			3.5 clk's\n");
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							debug("Max. Cas Latencies (DDR): 			3 clk's \n");
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							debug("Max. Cas Latencies (DDR): 			2.5 clk's \n");
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							debug("Max. Cas Latencies (DDR): 			2 clk's \n");
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							debug("Max. Cas Latencies (DDR): 			1.5 clk's \n");
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						debug("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP);
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
+						debug("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD);
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP);
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			debug("\nModul Attributes (SPD Byte 21): \n");
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				debug(" - Buffered Address/Control Input:		Yes \n");
+			else
+				debug(" - Buffered Address/Control Input:		No \n");
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				debug(" - Registered Address/Control Input:		Yes \n");
+			else
+				debug(" - Registered Address/Control Input:		No \n");
+
+			if (dimmInfo->onCardPLL == 1)
+				debug(" - On-Card PLL (clock):				Yes \n");
+			else
+				debug(" - On-Card PLL (clock):				No \n");
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				debug(" - Bufferd DQMB Inputs:				Yes \n");
+			else
+				debug(" - Bufferd DQMB Inputs:				No \n");
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				debug(" - Registered DQMB Inputs:			Yes \n");
+			else
+				debug(" - Registered DQMB Inputs:			No \n");
+
+			if (dimmInfo->differentialClockInput == 1)
+				debug(" - Differential Clock Input:			Yes \n");
+			else
+				debug(" - Differential Clock Input:			No \n");
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				debug(" - redundant Row Addressing:			Yes \n");
+			else
+				debug(" - redundant Row Addressing:			No \n");
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			debug("\nModul Attributes (SPD Byte 22): \n");
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				debug(" - Early Ras Precharge:			Yes \n");
+			else
+				debug(" -  Early Ras Precharge:			No \n");
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				debug(" - AutoPreCharge:				Yes \n");
+			else
+				debug(" -  AutoPreCharge:				No \n");
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				debug(" - Precharge All:				Yes \n");
+			else
+				debug(" -  Precharge All:				No \n");
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				debug(" - Write 1/ReadBurst:				Yes \n");
+			else
+				debug(" -  Write 1/ReadBurst:				No \n");
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				debug(" - lower VCC tolerance:			5 Percent \n");
+			else
+				debug("	- lower VCC tolerance:			10 Percent \n");
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				debug(" - upper VCC tolerance:			5 Percent \n");
+			else
+				debug(" -  upper VCC tolerance:			10 Percent \n");
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			debug("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			debug("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			debug("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100);
+			debug("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			debug("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			debug("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			debug("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks);
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			debug("Module Bank Density:				%d\n",
+			     dimmInfo->moduleBankDensity);
+#ifdef DEBUG
+			debug("*** Offered Densities (more than 1 = Multisize-Module): ");
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					debug("4MB, ");
+				if (dimmInfo->moduleBankDensity & 2)
+					debug("8MB, ");
+				if (dimmInfo->moduleBankDensity & 4)
+					debug("16MB, ");
+				if (dimmInfo->moduleBankDensity & 8)
+					debug("32MB, ");
+				if (dimmInfo->moduleBankDensity & 16)
+					debug("64MB, ");
+				if (dimmInfo->moduleBankDensity & 32)
+					debug("128MB, ");
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					debug("ERROR, ");
+					hang ();
+				}
+			}
+			debug("\n");
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			debug("Address And Command Setup Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			debug("Address And Command Hold Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			debug("Data Input Setup Time [ns]:			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			debug("Data Input Hold Time [ns]:			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint);
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices - devicesForErrCheck);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
+	dimmInfo->drb_size = (uchar) tmp;
+	debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 8) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 6;
+	}
+	if (supp_cal & 4) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 5;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 4;
+	}
+
+	debug("cal_val = %d\n", cal_val * 5);
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		debug("Couldn't find a good CAS latency\n");
+		hang ();
+		return 0;
+	}
+
+	return true;
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
+	int i;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+
+	/* Program the GT with the discovered data */
+	if (info->registeredAddrAndControlInputs == true)
+		debug("Module is registered, but we do not support registered Modules !!!\n");
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	debug("Delay line set done\n");
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
+	}
+
+#ifdef CONFIG_MV64360_ECC
+	if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg |= BIT18;
+		debug("Enabling ECC\n");
+	}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+	/* SDRAM configuration */
+	GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
+	debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
+
+	/* SDRAM open pages controll keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	debug("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		debug("Core Signals are sync (by HW-Setting)!!!\n");
+	else
+		debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
+
+	/* SDRAM set CAS Lentency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		debug("### SD-RAM not supported yet !!!\n");
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+
+	case DDR:
+		debug("### SET-CL for DDR-RAM\n");
+
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_dunit_control_low = 0x3c000000;	/* Read-Data sampled on falling edge of Clk */
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+			     tmp_sdram_mode, tmp_dunit_control_low);
+			break;
+
+		case DDR_CL_2_5:
+			if (tmp == 1) {	/* clocks sync */
+				tmp_dunit_control_low = 0x24000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			} else {	/* clk sync. bypassed	  */
+
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			}
+			break;
+
+		case DDR_CL_2:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			} else {	/* Not sync.	  */
+
+				tmp_dunit_control_low = 0x3b000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			}
+			break;
+
+		case DDR_CL_1_5:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x23000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			} else {	/* not sync */
+
+				tmp_dunit_control_low = 0x1a000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low);
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}
+		break;
+	}
+
+	/* Write results of CL detection procedure */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
+	}
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp != 1) {		/*clocks are not sync */
+		/* asyncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x18110780 | tmp_dunit_control_low);
+	} else {
+		/* syncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x00110000 | tmp_dunit_control_low);
+	}
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
+	}
+
+/*------------------------------------------------------------------------------ */
+
+
+	/* bank parameters */
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = 0x02;
+
+
+	debug("drb_size (n*64Mbit): %d\n", info->drb_size);
+	switch (info->drb_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		debug("RAM-Device_size 64Mbit or 128Mbit)\n");
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		debug("RAM-Device_size 256Mbit or 512Mbit)\n");
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		debug("RAM-Device_size 1Gbit or 2Gbit)\n");
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
+		tmp |= (0x02 << 4);
+		return 1;
+	}
+
+	/* SDRAM bank parameters */
+	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+	debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+
+/* ------------------------------------------------------------------------------ */
+
+	debug("setting up sdram_timing_control_low with: %08x \n",
+	     0x11511220);
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs);
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV64360 */
+	tmp |= (1 << 26);
+	debug("Before Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG));
+	debug("After Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG));
+
+	/* SDRAM timing To_do: */
+
+
+	tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
+	debug("# sdram_timing_control_high is : %08lx \n", tmp);
+
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
+	debug("SDRAM address control (before: decode): %08x  ",
+	     GTREGREAD (SDRAM_ADDR_CONTROL));
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
+	debug("SDRAM address control (after: decode): %08x\n",
+	     GTREGREAD (SDRAM_ADDR_CONTROL));
+
+	/* set the SDRAM configuration for each bank */
+
+/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		int l, l1;
+
+		i = info->slot;
+		debug("\n*** Running a MRS cycle for bank %d ***\n", i);
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+#if 1				/* test only */
+
+		tmp = GTREGREAD (SDRAM_MODE);
+		GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x4);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
+		}
+
+		GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
+		}
+		l1 = 0;
+		for (l=0;l<200;l++)
+			l1 += GTREGREAD (SDRAM_OPERATION);
+
+		GT_REG_WRITE (SDRAM_MODE, tmp);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
+		}
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+			debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
+		}
+
+#endif /* test only */
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int
+dram_size(long int *base, long int maxsize)
+{
+    volatile long int	 *addr, *b=base;
+    long int	 cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
+	    addr = base + cnt;	/* pointer arith! */
+
+	    save1 = *addr;		/* save contents of addr */
+	    save2 = *b;		/* save contents of base */
+
+	    *addr=cnt;		/* write cnt to addr */
+	    *b=0;			/* put null at base */
+
+	    /* check at base address */
+	    if ((*b) != 0) {
+		*addr=save1;	/* restore *addr */
+		*b=save2;	/* restore *b */
+		return (0);
+	    }
+	    val = *addr;		/* read *addr */
+	    val = *addr;		/* read *addr */
+
+	    *addr=save1;
+	    *b=save2;
+
+	    if (val != cnt) {
+		    debug("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
+		    /* fix boundary condition.. STARTVAL means zero */
+		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
+		    return (cnt * sizeof(long));
+	    }
+    }
+    return maxsize;
+}
+
+#ifdef CONFIG_MV64360_ECC
+/*
+ * mv_dma_is_channel_active:
+ * Checks if a engine is busy.
+ */
+int mv_dma_is_channel_active(int engine)
+{
+	ulong data;
+
+	data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14)	/* activity status */
+		return 1;
+
+	return 0;
+}
+
+/*
+ * mv_dma_set_memory_space:
+ * Set a DMA memory window for the DMA's address decoding map.
+ */
+int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
+			    ulong mem_space_attr, ulong base_address,
+			    ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (base_address % size != 0)
+		return 0;
+
+	if (size >= 0x10000) {
+		size &= 0xffff0000;
+		base_address = (base_address & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
+			     (base_address | mem_space_target |
+			      mem_space_attr));
+		GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
+			     (size - 1) & 0xffff0000);
+		temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
+			     (temp & ~(BIT0 << mem_space)));
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ * mv_dma_transfer:
+ * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
+ */
+int mv_dma_transfer(int engine, ulong source_addr,
+		    ulong dest_addr, ulong bytes, ulong command)
+{
+	ulong eng_off_reg;	/* Engine Offset Register */
+
+	if (bytes > 0xffff)
+		command = command | BIT31;	 /* DMA_16M_DESCRIPTOR_MODE */
+
+	command = command | ((command >> 6) & 0x7);
+	eng_off_reg = engine * 4;
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
+		     bytes);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
+		     source_addr);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
+		     dest_addr);
+	command |= BIT12	/* DMA_CHANNEL_ENABLE */
+		| BIT9;		/* DMA_NON_CHAIN_MODE */
+
+	/* Activate DMA engine By writting to mv_dma_control_register */
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
+
+	return 1;
+}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t
+initdram(int board_type)
+{
+	int checkbank[4] = { [0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int bank_no, nhr;
+#ifdef CONFIG_MV64360_ECC
+	ulong dest, mem_space_attr;
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0() & (1 << 16);
+
+	if (nhr) {
+		printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		(void)check_dimm(0, &dimmInfo1);
+
+		/* DIMM1 */
+		(void)check_dimm(1, &dimmInfo2);
+
+		memory_map_bank(0, 0, 0);
+		memory_map_bank(1, 0, 0);
+		memory_map_bank(2, 0, 0);
+		memory_map_bank(3, 0, 0);
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
+			printf("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
+			printf("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0(get_hid0() | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB/4;
+	if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
+	if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM1 has >2 banks\n");
+
+	if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
+	if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM2 has >2 banks\n");
+
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (! checkbank[bank_no])
+			continue;
+
+		if ((total + check) > CONFIG_SYS_GT_REGS)
+			check = CONFIG_SYS_GT_REGS - total;
+
+		memory_map_bank(bank_no, total, check);
+		realsize = dram_size((long int *)total, check);
+		memory_map_bank(bank_no, total, realsize);
+
+#ifdef CONFIG_MV64360_ECC
+		if (((dimmInfo1.errorCheckType != 0) &&
+		     ((dimmInfo2.errorCheckType != 0) ||
+		      (dimmInfo2.numOfModuleBanks == 0))) &&
+		    (CPCI750_ECC_TEST)) {
+			printf("ECC Initialization of Bank %d:", bank_no);
+			mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mv_dma_set_memory_space(0, 0, mem_space_attr, total,
+						realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mv_dma_transfer(0, total, dest, _8M,
+						BIT8 |	/* DMA_DTL_128BYTES */
+						BIT3 |	/* DMA_HOLD_SOURCE_ADDR */
+						BIT11);	/* DMA_BLOCK_TRANSFER_MODE */
+				while (mv_dma_is_channel_active(0))
+					;
+			}
+			printf(" PASS\n");
+		}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
+		total += realsize;
+	}
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	return(total);
+}
+
+/* ***************************************************************************************
+! *				SDRAM INIT						*
+! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+! *		  This procedure fits only the Atlantis				       *
+! *											*
+! *************************************************************************************** */
+
+
+/* ***************************************************************************************
+! *				DFCDL initialize MV643xx Design Considerations		   *
+! *											*
+! *************************************************************************************** */
+int set_dfcdlInit (void)
+{
+	int i;
+	unsigned int dfcdl_word = 0x0000014f;
+
+	for (i = 0; i < 64; i++) {
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
+	}
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+
+	return (0);
+}
+
+int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int ecc_counter;
+	unsigned int ecc_addr;
+
+	GT_REG_READ(0x1458, &ecc_counter);
+	GT_REG_READ(0x1450, &ecc_addr);
+	GT_REG_WRITE(0x1450, 0);
+
+	printf("Error Counter since Reset:  %8d\n", ecc_counter);
+	printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
+	if (ecc_addr & 0x01)
+		printf("double");
+	else
+		printf("single");
+	printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	show_ecc, 1, 1, do_show_ecc,
+	"Show Marvell MV64360 ECC Info",
+	"Show Marvell MV64360 ECC Counter and last error."
+);
diff --git a/roms/u-boot/board/esd/cpci750/serial.c b/roms/u-boot/board/esd/cpci750/serial.c
new file mode 100644
index 00000000..6c2cf215
--- /dev/null
+++ b/roms/u-boot/board/esd/cpci750/serial.c
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * modified for cpci750 board by
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * serial.c - serial support for esd cpci750 board
+ */
+
+/* supports the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
+#include "../../Marvell/include/memory.h"
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cpci750_serial_init(void)
+{
+	mpsc_init (gd->baudrate);
+
+	return (0);
+}
+
+static void cpci750_serial_putc(const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+static int cpci750_serial_getc(void)
+{
+	return mpsc_getchar ();
+}
+
+static int cpci750_serial_tstc(void)
+{
+	return mpsc_test_char ();
+}
+
+static void cpci750_serial_setbrg(void)
+{
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+static struct serial_device cpci750_serial_drv = {
+	.name	= "cpci750_serial",
+	.start	= cpci750_serial_init,
+	.stop	= NULL,
+	.setbrg	= cpci750_serial_setbrg,
+	.putc	= cpci750_serial_putc,
+	.puts	= default_serial_puts,
+	.getc	= cpci750_serial_getc,
+	.tstc	= cpci750_serial_tstc,
+};
+
+void cpci750_serial_initialize(void)
+{
+	serial_register(&cpci750_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+	return &cpci750_serial_drv;
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif
diff --git a/roms/u-boot/board/esd/cpciiser4/Makefile b/roms/u-boot/board/esd/cpciiser4/Makefile
new file mode 100644
index 00000000..b8d6bea6
--- /dev/null
+++ b/roms/u-boot/board/esd/cpciiser4/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpciiser4.o flash.o ../common/misc.o
diff --git a/roms/u-boot/board/esd/cpciiser4/cpciiser4.c b/roms/u-boot/board/esd/cpciiser4/cpciiser4.c
new file mode 100644
index 00000000..e61cd5b1
--- /dev/null
+++ b/roms/u-boot/board/esd/cpciiser4/cpciiser4.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2000
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "cpciiser4.h"
+#include <asm/processor.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * Init FPGA via RESET (read access on CS3)
+	 */
+	in_8((void *)0xf0200000);
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	/*  mtdcr(UIC0PR, 0xFFFFFF81);   /  set int polarities */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/cpciiser4/cpciiser4.h b/roms/u-boot/board/esd/cpciiser4/cpciiser4.h
new file mode 100644
index 00000000..75e7950b
--- /dev/null
+++ b/roms/u-boot/board/esd/cpciiser4/cpciiser4.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/roms/u-boot/board/esd/cpciiser4/flash.c b/roms/u-boot/board/esd/cpciiser4/flash.c
new file mode 100644
index 00000000..34bdc053
--- /dev/null
+++ b/roms/u-boot/board/esd/cpciiser4/flash.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+	/*          printf("PB1CR = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/cpciiser4/fpgadata.c b/roms/u-boot/board/esd/cpciiser4/fpgadata.c
new file mode 100644
index 00000000..ac6122dc
--- /dev/null
+++ b/roms/u-boot/board/esd/cpciiser4/fpgadata.c
@@ -0,0 +1,4136 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0c,
+0x69, 0x73, 0x65, 0x72, 0x34, 0x5f, 0x31, 0x2e,
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+0x38, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, 0x30,
+0x31, 0x2f, 0x30, 0x33, 0x2f, 0x31, 0x39, 0x00,
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+0x3a, 0x32, 0x35, 0x00, 0x65, 0xe2, 0x01, 0x00,
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+0xe5, 0x03, 0xe8, 0x04, 0x01, 0x02, 0x09, 0x07,
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+0x0b, 0x09, 0x06, 0xe5, 0xe5, 0x01, 0x03, 0xe5,
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+0x01, 0x09, 0x09, 0x13, 0xe5, 0x47, 0x05, 0x17,
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+0xe6, 0xe5, 0x46, 0x31, 0x1f, 0x13, 0x58, 0x25,
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+0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05, 0xe5, 0x01,
+0x05, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x06, 0xe5, 0x01, 0x71, 0x09, 0x09, 0x09, 0x9e,
+0xe8, 0x72, 0x09, 0x09, 0x09, 0x9c, 0x03, 0x91,
+0x08, 0x93, 0x02, 0xe5, 0x2d, 0x3d, 0x09, 0x09,
+0x09, 0x04, 0x04, 0x9a, 0xe5, 0xe5, 0x66, 0x01,
+0xe5, 0x05, 0x09, 0x01, 0xe5, 0x05, 0x09, 0x12,
+0x8b, 0xe5, 0xe6, 0xe5, 0x0e, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x06, 0xe5, 0xe5, 0x06, 0x01, 0x04,
+0x02, 0x01, 0x04, 0x02, 0xe8, 0x01, 0x02, 0x01,
+0xe5, 0x02, 0x02, 0x01, 0x02, 0xe5, 0x02, 0x01,
+0x04, 0x04, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05,
+0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x08, 0x01, 0xe6, 0xe5, 0x3c, 0x35, 0x01, 0x09,
+0x0e, 0x9f, 0x01, 0xe7, 0x36, 0xe3, 0x12, 0xe5,
+0xe7, 0x46, 0x13, 0x17, 0x25, 0x8a, 0x0a, 0xe5,
+0xe5, 0x1c, 0x48, 0x0c, 0x09, 0x07, 0xe5, 0x07,
+0xa0, 0xe6, 0x47, 0x1b, 0x12, 0x0c, 0x0d, 0x06,
+0x3c, 0x5b, 0x5c, 0x03, 0x0f, 0xe5, 0x08, 0x0a,
+0xe5, 0x10, 0x16, 0xe5, 0x05, 0x6d, 0x07, 0xe5,
+0x01, 0x63, 0x21, 0x13, 0x15, 0x7e, 0x02, 0xe5,
+0x61, 0x13, 0x01, 0x0c, 0x13, 0x11, 0x05, 0x7d,
+0xe5, 0xe5, 0x91, 0x06, 0x94, 0xe5, 0x01, 0x8a,
+0x0d, 0xe5, 0x93, 0x02, 0xe5, 0x61, 0x24, 0x12,
+0x06, 0x05, 0x27, 0x09, 0x57, 0xe6, 0x37, 0x32,
+0x1b, 0x1d, 0xe5, 0x24, 0x01, 0x08, 0x54, 0xe5,
+0x01, 0xe5, 0x3a, 0x49, 0x21, 0x25, 0x60, 0xe5,
+0xe6, 0x02, 0x09, 0xe7, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x03, 0xe5, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
+0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x01, 0x09, 0xe5, 0x01,
+0xe5, 0x0d, 0x01, 0x09, 0x09, 0x09, 0x09, 0x02,
+0x06, 0x02, 0x06, 0x07, 0x01, 0x09, 0x07, 0x01,
+0x05, 0x03, 0x09, 0x09, 0x07, 0x01, 0x0b, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x02, 0x0a, 0x03, 0x0f,
+0x05, 0x03, 0x09, 0x09, 0x09, 0x04, 0x04, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x0a, 0x11, 0x02,
+0xe5, 0x11, 0xe5, 0x03, 0x03, 0x09, 0x1d, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe5, 0x97,
+0x8b, 0x09, 0x01, 0xe6, 0x0e, 0x05, 0x03, 0x09,
+0x09, 0x09, 0x09, 0x04, 0x04, 0x09, 0x09, 0x04,
+0x04, 0x09, 0x06, 0x02, 0x09, 0x09, 0x06, 0x01,
+0x02, 0x09, 0x09, 0x05, 0x03, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0e,
+0xe5, 0x01, 0x0d, 0xe5, 0x05, 0x01, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x07, 0xe5, 0x09,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x05, 0x01, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x10, 0xe6, 0x02, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x08, 0xe5,
+0x08, 0x03, 0x05, 0x09, 0x03, 0x05, 0x09, 0x01,
+0x07, 0x0b, 0x01, 0x07, 0x09, 0x01, 0x07, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x0b, 0x05, 0xe5, 0xe5, 0x0d, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
+0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0x09, 0x02, 0x08, 0xe5, 0x07, 0x02,
+0x06, 0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x05, 0x02, 0x06, 0x02, 0x06, 0xe5, 0xe5, 0x05,
+0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x0b, 0x01, 0x01, 0x0e, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x0f, 0xe6, 0xe5, 0x86, 0x09, 0x15, 0x27, 0x09,
+0x4e, 0x05, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09,
+0x09, 0x13, 0x13, 0x05, 0x03, 0x09, 0x09, 0x09,
+0x09, 0x08, 0x02, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x07, 0xe6, 0x3f, 0x13, 0x10, 0x33, 0x1d,
+0x76, 0x03, 0x10, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x05,
+0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03,
+0x05, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x0e, 0xe7, 0x03, 0x37, 0x03, 0x05, 0x0d, 0x0f,
+0xe5, 0x33, 0x1c, 0x72, 0x03, 0xe6, 0xe5, 0x37,
+0x09, 0x13, 0x42, 0xe5, 0x8e, 0x04, 0xe7, 0x3f,
+0x13, 0x44, 0x90, 0x03, 0xe6, 0xe5, 0x8f, 0x9d,
+0x03, 0x13, 0x09, 0x09, 0x09, 0x1d, 0x09, 0x0c,
+0x06, 0x09, 0x09, 0x36, 0x06, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x15, 0x01,
+0xe5, 0x35, 0x05, 0x03, 0x05, 0x0d, 0x0f, 0x2a,
+0x97, 0x06, 0x02, 0xe5, 0x98, 0x8e, 0x05, 0x03,
+0xe3, 0x50, 0x14, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x02,
+0xe5, 0x04, 0xe6, 0x01, 0xe5, 0x04, 0x09, 0xe8,
+0x04, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x05,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x0f,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x03, 0x05, 0x09, 0x09, 0x08, 0xe5, 0x06, 0xe6,
+0x05, 0xe5, 0xe7, 0x07, 0xe5, 0x05, 0xe7, 0x08,
+0x09, 0x08, 0xe5, 0x07, 0xe5, 0x08, 0x07, 0xe6,
+0x08, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01, 0xe5,
+0x38, 0x09, 0x13, 0x0a, 0x36, 0x95, 0x02, 0x0d,
+0x09, 0x09, 0x09, 0x09, 0x04, 0x04, 0x03, 0xe5,
+0x03, 0x09, 0x03, 0x05, 0x04, 0x04, 0x09, 0x09,
+0x11, 0x09, 0x0b, 0x09, 0x09, 0x01, 0x09, 0x1d,
+0x0b, 0x07, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01,
+0xe7, 0x0a, 0x02, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x01, 0x07, 0x03, 0x02, 0x02, 0x03, 0x01, 0xe5,
+0x01, 0x01, 0x07, 0x03, 0x05, 0x01, 0x04, 0x02,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x02, 0x04,
+0x15, 0x04, 0x0e, 0x03, 0x07, 0x01, 0x07, 0x02,
+0x06, 0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x07,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x05, 0xe6, 0xe5, 0xe5, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff,
diff --git a/roms/u-boot/board/esd/dp405/Makefile b/roms/u-boot/board/esd/dp405/Makefile
new file mode 100644
index 00000000..cfcfb66a
--- /dev/null
+++ b/roms/u-boot/board/esd/dp405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+obj-y	= dp405.o flash.o ../common/misc.o $(CPLD)
diff --git a/roms/u-boot/board/esd/dp405/dp405.c b/roms/u-boot/board/esd/dp405/dp405.c
new file mode 100644
index 00000000..730ff215
--- /dev/null
+++ b/roms/u-boot/board/esd/dp405/dp405.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO13 (CS4) pin
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
+				   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+	unsigned char id1, id2, rev;
+
+	puts ("Board: ");
+
+	if (i == -1)
+		puts ("### No HW ID - assuming DP405");
+	else
+		puts(str);
+
+	id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
+	id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
+
+	rev = in_8((void *)0xf0001000);
+	if (rev & 0x10) /* old DP405 compatibility */
+		rev = in_8((void *)0xf0000800);
+
+	switch (rev & 0xc0) {
+	case 0x00:
+		puts(" (HW=DP405");
+		break;
+	case 0x80:
+		puts(" (HW=DP405/CO");
+		break;
+	case 0xc0:
+		puts(" (HW=DN405");
+		break;
+	}
+	printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
+
+	if ((rev & 0xc0) == 0xc0) {
+		printf(", C5V=%s",
+		       in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
+	}
+	puts(")\n");
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/dp405/flash.c b/roms/u-boot/board/esd/dp405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/dp405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/du405/Makefile b/roms/u-boot/board/esd/du405/Makefile
new file mode 100644
index 00000000..7914eab3
--- /dev/null
+++ b/roms/u-boot/board/esd/du405/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= du405.o flash.o ../common/misc.o
diff --git a/roms/u-boot/board/esd/du405/du405.c b/roms/u-boot/board/esd/du405/du405.c
new file mode 100644
index 00000000..8f5f4d02
--- /dev/null
+++ b/roms/u-boot/board/esd/du405/du405.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "du405.h"
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
+	 * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
+	 * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFFB1);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 100 us
+	 */
+	mtebc (EBC0_CFG, 0xb8400000);
+
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * Setup UART1 handshaking: use CTS instead of DSR
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming DU405");
+	} else {
+		puts (str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Reset external DUART via FPGA
+	 */
+	out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
+	out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/du405/du405.h b/roms/u-boot/board/esd/du405/du405.h
new file mode 100644
index 00000000..292f1963
--- /dev/null
+++ b/roms/u-boot/board/esd/du405/du405.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/roms/u-boot/board/esd/du405/flash.c b/roms/u-boot/board/esd/du405/flash.c
new file mode 100644
index 00000000..5650e5ea
--- /dev/null
+++ b/roms/u-boot/board/esd/du405/flash.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*          printf("PB1CR = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*            printf("PB0CR = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/roms/u-boot/board/esd/du405/fpgadata.c b/roms/u-boot/board/esd/du405/fpgadata.c
new file mode 100644
index 00000000..262f2ca2
--- /dev/null
+++ b/roms/u-boot/board/esd/du405/fpgadata.c
@@ -0,0 +1,1405 @@
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+0xe5, 0xdc, 0xe8, 0xdf, 0x01, 0xdf, 0xe5, 0xe5,
+0x10, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05, 0x01,
+0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x09,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x01, 0x07, 0x01, 0x0c, 0xe6, 0xdd, 0xe9, 0x50,
+0x33, 0x56, 0x01, 0x02, 0x01, 0x03, 0x2c, 0x3e,
+0x6c, 0xe5, 0xe7, 0x6f, 0x6b, 0x01, 0xe5, 0xe5,
+0x12, 0x5d, 0x6e, 0xe7, 0x08, 0x1f, 0x09, 0x3c,
+0x4a, 0x15, 0x0a, 0xe9, 0x70, 0x6c, 0x02, 0xe5,
+0x05, 0x6a, 0x6c, 0xe6, 0xe5, 0x70, 0x6e, 0xe6,
+0x70, 0x6d, 0xe7, 0x09, 0x09, 0x09, 0xbf, 0x01,
+0x01, 0xde, 0xe5, 0xe6, 0x26, 0xba, 0xdc, 0x01,
+0x01, 0xe6, 0x01, 0x01, 0xd4, 0x01, 0x03, 0xe7,
+0x03, 0xcf, 0xe5, 0x02, 0x04, 0x02, 0xe5, 0xe6,
+0xd7, 0x03, 0x01, 0xe6, 0xe5, 0x06, 0x01, 0xd0,
+0x02, 0xe6, 0xda, 0x02, 0xe5, 0x01, 0xdd, 0xe6,
+0xe6, 0xda, 0xe5, 0x02, 0xe7, 0x07, 0xd3, 0x01,
+0xe7, 0x09, 0x01, 0xd5, 0xe5, 0x07, 0x05, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x04, 0x01, 0x06, 0xe9, 0xd5, 0x04,
+0x05, 0xe5, 0xd2, 0x0a, 0x02, 0xe5, 0xdf, 0x01,
+0xdf, 0xe8, 0xdd, 0x01, 0xe5, 0x14, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0x01, 0xe5,
+0xd8, 0x05, 0xe7, 0xde, 0xe5, 0xe6, 0xdc, 0x02,
+0xe5, 0x02, 0x08, 0xd3, 0x01, 0x32, 0xab, 0xe6,
+0xe5, 0x10, 0x01, 0x02, 0x04, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x09, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x0a, 0x02, 0xe5, 0xde, 0x02, 0xe5,
+0x64, 0x15, 0x13, 0x4c, 0x02, 0xe6, 0x70, 0x6d,
+0xe5, 0xe6, 0x6f, 0x6b, 0x02, 0x01, 0x13, 0x5d,
+0x64, 0x07, 0xe5, 0xe7, 0x43, 0x2b, 0x61, 0x09,
+0xe5, 0x02, 0x25, 0x4b, 0x6e, 0x01, 0x06, 0x20,
+0x49, 0x6d, 0xe5, 0xe5, 0x70, 0x6c, 0x03, 0x03,
+0x6d, 0x6e, 0xe6, 0xe1, 0xdc, 0x01, 0xe5, 0x01,
+0xe3, 0xe7, 0xd9, 0x03, 0xe6, 0x01, 0x01, 0xd4,
+0x01, 0x02, 0x01, 0x01, 0x04, 0xd4, 0x06, 0x01,
+0xd4, 0xe5, 0x04, 0x02, 0x01, 0xe6, 0xdc, 0x01,
+0x02, 0x02, 0xd8, 0x03, 0x02, 0x01, 0xdb, 0x01,
+0xe5, 0xe5, 0xdd, 0xe5, 0x01, 0xdd, 0x01, 0xe7,
+0xdf, 0xe7, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0d, 0x02,
+0x01, 0x02, 0xd8, 0x04, 0xe6, 0xdd, 0x02, 0xe5,
+0xdd, 0x01, 0xe6, 0xdd, 0xe5, 0x01, 0xe5, 0xde,
+0x01, 0x15, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x06, 0x01, 0x01, 0xde, 0x01, 0x01, 0xe3,
+0xe6, 0xdc, 0xe5, 0x01, 0xdf, 0xe7, 0x3b, 0x10,
+0x92, 0xe6, 0x10, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01, 0x07,
+0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x09, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x01, 0x05, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01,
+0x07, 0x01, 0x01, 0x05, 0x01, 0x07, 0x01, 0x0d,
+0xe5, 0x50, 0x34, 0x58, 0x02, 0xe5, 0x50, 0x8a,
+0xe9, 0xe5, 0x02, 0x5f, 0x0a, 0xe5, 0x09, 0x12,
+0x51, 0xe5, 0x03, 0x49, 0x22, 0x14, 0x13, 0x42,
+0xe5, 0x01, 0xe6, 0x01, 0x6d, 0x6f, 0xe6, 0x2b,
+0x24, 0x1e, 0x52, 0xe5, 0x0b, 0x0a, 0xe5, 0x01,
+0xe6, 0x23, 0x05, 0x01, 0x3f, 0x03, 0x6c, 0xe5,
+0xe6, 0x26, 0x06, 0x42, 0x6c, 0x01, 0xe7, 0x6f,
+0x6d, 0xe7, 0x70, 0x6d, 0x01, 0xe5, 0x30, 0x3d,
+0x5f, 0x0e, 0x01, 0x01, 0x2d, 0x97, 0x08, 0xe5,
+0x0d, 0xe5, 0x01, 0x09, 0x23, 0x44, 0x52, 0x08,
+0x11, 0xe6, 0x02, 0x0b, 0xe5, 0x01, 0x06, 0x06,
+0xe7, 0x07, 0xe5, 0x05, 0xe7, 0x05, 0xe7, 0x05,
+0xe7, 0xe5, 0x05, 0xe5, 0x08, 0x08, 0xe5, 0x09,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x0b, 0x02, 0xe6, 0x0d, 0x01,
+0x02, 0x04, 0x01, 0x02, 0x04, 0x01, 0x02, 0x04,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x02, 0x02, 0x01,
+0x01, 0x08, 0xe5, 0x0d, 0x02, 0x01, 0x0b, 0x09,
+0x09, 0x09, 0x07, 0x01, 0x01, 0xe5, 0x05, 0x09,
+0x09, 0x02, 0x06, 0x09, 0x0d, 0x02, 0xe5, 0x0f,
+0x08, 0x13, 0x09, 0x1d, 0x09, 0x04, 0x04, 0x08,
+0x02, 0x04, 0x04, 0x09, 0x04, 0x04, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x0f, 0x02, 0x14, 0x41,
+0x87, 0x01, 0xe6, 0x18, 0x03, 0x05, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x13, 0x0b, 0x09, 0x04, 0x04,
+0x09, 0x04, 0x04, 0x02, 0x06, 0x09, 0x09, 0x09,
+0x09, 0x0e, 0x01, 0x01, 0x0d, 0xe5, 0x07, 0xe6,
+0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe6,
+0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x01, 0x03, 0x03, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x0e, 0xe8,
+0x02, 0x05, 0x03, 0x09, 0x01, 0x04, 0x02, 0x01,
+0x07, 0x09, 0x09, 0x01, 0x07, 0x01, 0x07, 0x09,
+0x07, 0x01, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x14, 0x0e, 0x09, 0x09,
+0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0x09,
+0x09, 0xe5, 0xe5, 0x05, 0x09, 0xe5, 0xe5, 0x07,
+0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
+0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x0f, 0x0e, 0x09,
+0x01, 0x07, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x01, 0x07, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x0f, 0x01, 0xe6, 0x47,
+0x11, 0x76, 0x0c, 0x01, 0x01, 0x0e, 0x05, 0x03,
+0x05, 0x03, 0x09, 0x05, 0x03, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x06, 0x01, 0x02, 0x05, 0x03, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0f,
+0xe8, 0x0f, 0x13, 0x1d, 0x09, 0x24, 0x70, 0x10,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x05, 0x03,
+0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x0e, 0x01, 0xe5, 0x46,
+0x96, 0x02, 0xe5, 0x70, 0x6e, 0x01, 0x22, 0x1d,
+0x09, 0x13, 0x11, 0xe5, 0x67, 0x06, 0xe5, 0x06,
+0x06, 0x06, 0x02, 0x06, 0x02, 0x06, 0x16, 0x06,
+0x02, 0x13, 0x06, 0x79, 0xe5, 0xe5, 0x3a, 0x1d,
+0x33, 0x1d, 0x09, 0x2a, 0xe6, 0x06, 0x05, 0x08,
+0xe5, 0x07, 0xe5, 0x07, 0x14, 0x08, 0xe5, 0x12,
+0x08, 0x0a, 0x65, 0x06, 0x03, 0x71, 0x66, 0x05,
+0xe5, 0xe6, 0xdd, 0xe5, 0xe6, 0x0c, 0xe5, 0x04,
+0xe8, 0x04, 0xe8, 0x04, 0xe6, 0x06, 0x09, 0x02,
+0xe5, 0x04, 0xe8, 0x04, 0x09, 0x02, 0xe5, 0x04,
+0xe6, 0x06, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x01, 0xe6, 0x0c,
+0xe6, 0x05, 0xe7, 0x05, 0xe7, 0x05, 0x01, 0xe5,
+0x08, 0x07, 0xe6, 0x05, 0xe7, 0x08, 0x07, 0xe6,
+0x05, 0x02, 0x07, 0x03, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x08, 0xe5, 0x07, 0xe5, 0x0e,
+0xe5, 0xe5, 0x33, 0x2d, 0x0e, 0x10, 0x13, 0x48,
+0x02, 0x11, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
+0x03, 0x01, 0x0d, 0x03, 0x05, 0x03, 0x01, 0x0d,
+0x03, 0x01, 0x03, 0x07, 0x09, 0x09, 0x09, 0x09,
+0x03, 0x05, 0x09, 0x09, 0x11, 0x13, 0x01, 0xe5,
+0x0a, 0x06, 0x09, 0x09, 0x04, 0x01, 0x02, 0x01,
+0x03, 0x07, 0x05, 0x09, 0x01, 0x03, 0x07, 0x0e,
+0xe5, 0x02, 0x06, 0xe5, 0x02, 0x04, 0x04, 0x01,
+0x07, 0x04, 0x04, 0x05, 0x03, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x03, 0x03, 0x02, 0x04, 0x04, 0x06,
+0x01, 0x03, 0xe5, 0xe5, 0xe6, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff,
diff --git a/roms/u-boot/board/esd/du440/Makefile b/roms/u-boot/board/esd/du440/Makefile
new file mode 100644
index 00000000..ef41d94a
--- /dev/null
+++ b/roms/u-boot/board/esd/du440/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= du440.o
+extra-y	+= init.o
diff --git a/roms/u-boot/board/esd/du440/config.mk b/roms/u-boot/board/esd/du440/config.mk
new file mode 100644
index 00000000..9cb071e4
--- /dev/null
+++ b/roms/u-boot/board/esd/du440/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/roms/u-boot/board/esd/du440/du440.c b/roms/u-boot/board/esd/du440/du440.c
new file mode 100644
index 00000000..b168b247
--- /dev/null
+++ b/roms/u-boot/board/esd/du440/du440.c
@@ -0,0 +1,882 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+	/*
+	 * Setup the GPIO pins
+	 */
+	out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_OSRL, 0x50055400);
+	out_be32((void*)GPIO0_OSRH, 0x55005000);
+	out_be32((void*)GPIO0_TSRL, 0x50055400);
+	out_be32((void*)GPIO0_TSRH, 0x55005000);
+	out_be32((void*)GPIO0_ISR1L, 0x50000000);
+	out_be32((void*)GPIO0_ISR1H, 0x00000000);
+	out_be32((void*)GPIO0_ISR2L, 0x00000000);
+	out_be32((void*)GPIO0_ISR2H, 0x00000000);
+	out_be32((void*)GPIO0_ISR3L, 0x00000000);
+	out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+	out_be32((void*)GPIO1_OR, 0x00000000);
+	out_be32((void*)GPIO1_TCR, 0xc2000000 |
+		 CONFIG_SYS_GPIO1_IORSTN |
+		 CONFIG_SYS_GPIO1_IORST2N |
+		 CONFIG_SYS_GPIO1_LEDUSR1 |
+		 CONFIG_SYS_GPIO1_LEDUSR2 |
+		 CONFIG_SYS_GPIO1_LEDPOST |
+		 CONFIG_SYS_GPIO1_LEDDU);
+	out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
+	out_be32((void*)GPIO1_OSRL, 0x0c280000);
+	out_be32((void*)GPIO1_OSRH, 0x00000000);
+	out_be32((void*)GPIO1_TSRL, 0xcc000000);
+	out_be32((void*)GPIO1_TSRH, 0x00000000);
+	out_be32((void*)GPIO1_ISR1L, 0x00005550);
+	out_be32((void*)GPIO1_ISR1H, 0x00000000);
+	out_be32((void*)GPIO1_ISR2L, 0x00050000);
+	out_be32((void*)GPIO1_ISR2H, 0x00000000);
+	out_be32((void*)GPIO1_ISR3L, 0x01400000);
+	out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * UIC1:
+	 *  bit30: ext. Irq 1: PLD : int 32+30
+	 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xfffffffd);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * UIC2
+	 *  bit3: ext. Irq 2: DCF77 : int 64+3
+	 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+	/* setup EMAC bridge interface */
+	if (board_revision() == 0) {
+		/* 1 x MII */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+			SDR0_PFC1_SELECT_CONFIG_1_2;
+		sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+			SDR0_PFC2_SELECT_CONFIG_1_2;
+	} else {
+		/* 2 x SMII */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+			SDR0_PFC1_SELECT_CONFIG_6;
+		sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+			SDR0_PFC2_SELECT_CONFIG_6;
+	}
+
+	/* enable 2nd IIC */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(SDR0_PCI0, reg);
+	mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
+		(0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
+	int i, j;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+	/*
+	 * USB suff...
+	 */
+	/* SDR Setting */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	mfsdr(SDR0_USB0, usb2d0cr);
+	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+	/* An 8-bit/60MHz interface is the only possible alternative
+	   when connecting the Device to the PHY */
+	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+	/* To enable the USB 2.0 Device function through the UTMI interface */
+	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+	mtsdr(SDR0_USB0, usb2d0cr);
+	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+	/*
+	 * Take USB out of reset:
+	 * -Initial status = all cores are in reset
+	 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+	 * -wait 1 ms
+	 * -deassert reset to PHY
+	 * -wait 1 ms
+	 * -deassert  reset to HOST
+	 * -wait 4 ms
+	 * -deassert all other resets
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |		\
+			SDR0_SRST1_P4OPB0 |		\
+			SDR0_SRST1_OPBA2 |		\
+			SDR0_SRST1_PLB42OPB1 |		\
+			SDR0_SRST1_OPB2PLB40);
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+	udelay(1000);
+
+	mfsdr(SDR0_SRST0, sdr0_srst0);
+	sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+	mtsdr(SDR0_SRST0, sdr0_srst0);
+	udelay(4000);
+
+	/* finally all the other resets */
+	mtsdr(SDR0_SRST1, 0x00000000);
+	mtsdr(SDR0_SRST0, 0x00000000);
+
+	printf("USB:   Host(int phy)\n");
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+	/*
+	 * release IO-RST#
+	 * We have to wait at least 560ms until we may call usbhub_init
+	 */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
+		 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
+
+	/*
+	 * flash USR1/2 LEDs (600ms)
+	 * This results in the necessary delay from IORST# until
+	 * calling usbhub_init will succeed
+	 */
+	for (j = 0; j < 3; j++) {
+		out_be32((void*)GPIO1_OR,
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
+			 CONFIG_SYS_GPIO1_LEDUSR1);
+
+		for (i = 0; i < 100; i++)
+			udelay(1000);
+
+		out_be32((void*)GPIO1_OR,
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
+			 CONFIG_SYS_GPIO1_LEDUSR2);
+
+		for (i = 0; i < 100; i++)
+			udelay(1000);
+	}
+
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+		 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
+
+	if (usbhub_init())
+		du440_post_errors++;
+
+	if (dvi_init())
+		du440_post_errors++;
+
+	return 0;
+}
+
+int pld_revision(void)
+{
+	out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
+	return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+	int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
+			  >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
+
+	return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+		((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#if defined(CONFIG_SHOW_ACTIVITY)
+void board_show_activity (ulong timestamp)
+{
+	if ((timestamp % 100) == 0)
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+	if (board_revision() == 0)
+		return devnum;
+
+	return devnum + 1;
+}
+
+int checkboard(void)
+{
+	char serno[32];
+
+	puts("Board: DU440");
+
+	if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
+		puts(", serial# ");
+		puts(serno);
+	}
+
+	printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+	       board_revision(), pld_revision());
+	return (0);
+}
+
+int last_stage_init(void)
+{
+	int e, i;
+
+	/* everyting is ok: turn on POST-LED */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+	/* slowly blink on errors and finally keep LED off */
+	for (e = 0; e < du440_post_errors; e++) {
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+		for (i = 0; i < 500; i++)
+			udelay(1000);
+
+		out_be32((void*)GPIO1_OR,
+			 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
+
+		for (i = 0; i < 500; i++)
+			udelay(1000);
+	}
+
+	return 0;
+}
+
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+	unsigned int oldbus;
+	uchar u[2];
+	int mv;
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(1);
+
+	if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+		I2C_SET_BUS(oldbus);
+		return -1;
+	}
+
+	mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+	I2C_SET_BUS(oldbus);
+	return mv;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int mv;
+	u32 pin, pinold;
+	unsigned long long t1, t2;
+	bd_t *bd = gd->bd;
+
+	printf("DCF77: ");
+	mv = dcf77_status();
+	if (mv > 0)
+		printf("signal=%d mV\n", mv);
+	else
+		printf("ERROR - no signal\n");
+
+	t1 = t2 = 0;
+	pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+	while (!ctrlc()) {
+		pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+		if (pin && !pinold) { /* bit start */
+			t1 = get_ticks();
+			if (t2 && ((unsigned int)(t1 - t2) /
+				   (bd->bi_procfreq / 1000) >= 1800))
+				printf("Start of minute\n");
+
+			t2 = t1;
+		}
+		if (t1 && !pin && pinold) { /* bit end */
+			printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+			       (bd->bi_procfreq / 1000));
+		}
+		pinold = pin;
+	}
+
+	printf("Abort\n");
+	return 0;
+}
+U_BOOT_CMD(
+	dcf77, 1, 1, do_dcf77,
+	"Check DCF77 receiver",
+	""
+);
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+	int reg;
+	int ret = 0;
+	unsigned int oldbus;
+	uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+		     0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+		     0x32};
+	uchar stcd;
+
+	printf("Hub:   ");
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(1);
+
+	for (reg = 0; reg < sizeof(u); reg++)
+		if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+			ret = -1;
+			break;
+		}
+
+	if (ret == 0) {
+		stcd = 0x03;
+		if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+			ret = -1;
+	}
+
+	if (ret == 0)
+		printf("initialized\n");
+	else
+		printf("failed - cannot initialize USB hub\n");
+
+	I2C_SET_BUS(oldbus);
+	return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	usbhub_init();
+	return 0;
+}
+U_BOOT_CMD(
+	hubinit, 1, 1, do_hubinit,
+	"Initialize USB hub",
+	""
+);
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+		       unsigned offset,
+		       uchar *buffer,
+		       unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 1);
+#endif
+	/*
+	 * Write data until done or would cross a write page boundary.
+	 * We must write the address again when changing pages
+	 * because the address counter only increments within a page.
+	 */
+
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen = 2;
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+		/*
+		 * For a FRAM device there is no limit on the number of the
+		 * bytes that can be ccessed with the single read or write
+		 * operation.
+		 */
+#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define	BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+		maxlen = BOOT_EEPROM_PAGE_SIZE -
+			BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+		maxlen = 0x100 - blk_off;
+#endif
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+			rcode = 1;
+
+		buffer += len;
+		offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+	}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 0);
+#endif
+	return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong sdsdp[4];
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "533")) {
+			printf("Bootstrapping for 533MHz\n");
+			sdsdp[0] = 0x87788252;
+			/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+			sdsdp[1] = 0x095fa030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "533-66")) {
+			printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+			sdsdp[0] = 0x87788252;
+			/* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+			sdsdp[1] = 0x0957a030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "667")) {
+			printf("Bootstrapping for 667MHz\n");
+			sdsdp[0] = 0x8778a256;
+			/* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+			sdsdp[1] = 0x0947a030;
+			/* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+			 * -> not working when overclocking 533MHz chips
+			 * -> untested on 667MHz chips */
+			/* sdsdp[1]=0x095fa030; */
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		} else if (!strcmp(argv[1], "667-166")) {
+			printf("Bootstrapping for 667-166MHz\n");
+			sdsdp[0] = 0x8778a252;
+			sdsdp[1] = 0x09d7a030;
+			sdsdp[2] = 0x40082350;
+			sdsdp[3] = 0x0d050000;
+		}
+	} else {
+		printf("Bootstrapping for 533MHz (default)\n");
+		sdsdp[0] = 0x87788252;
+		/* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+		sdsdp[1] = 0x095fa030;
+		sdsdp[2] = 0x40082350;
+		sdsdp[3] = 0x0d050000;
+	}
+
+	printf("Writing boot EEPROM ...\n");
+	if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+			      0, (uchar*)sdsdp, 16) != 0)
+		printf("boot_eeprom_write failed\n");
+	else
+		printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	sbe, 2, 0, do_setup_boot_eeprom,
+	"setup boot eeprom",
+	""
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ * Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *                      0: disable write
+ *                      1: enable write
+ * Returns:            -1: wrong device address
+ *                      0: dis-/en- able done
+ *                    0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
+		return -1;
+	else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void*)GPIO0_OR) &
+				       CONFIG_SYS_GPIO0_EP_EEP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0)
+			puts ("Query of write access state failed.\n");
+		else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0)
+			puts ("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+	int rc = -1; /* not for us */
+	u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
+
+	/* check for PLD interrupt */
+	if (status & PWR_INT_FLAG) {
+		/* reset this int */
+		out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+		rc = 0;
+		got_pldirq = 1; /* trigger backend */
+	}
+
+	return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	got_pldirq = 0;
+
+	/* clear any pending interrupt */
+	out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+
+	irq_install_handler(CPLD_IRQ,
+			    (interrupt_handler_t *)pld_interrupt, 0);
+
+	printf("Waiting ...\n");
+	while(!got_pldirq) {
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			break;
+		}
+	}
+	if (got_pldirq) {
+		printf("Got interrupt!\n");
+		printf("Power %sready!\n",
+		       in_8((void *)CONFIG_SYS_CPLD_BASE) &
+		       PWR_RDY ? "":"NOT ");
+	}
+
+	irq_free_handler(CPLD_IRQ);
+	return 0;
+}
+U_BOOT_CMD(
+	wpi,	1,	1,	do_waitpwrirq,
+	"Wait for power change interrupt",
+	""
+);
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+	int i;
+	int ret = 0;
+	unsigned int oldbus;
+	uchar u[] = {0x08, 0x34,
+		     0x09, 0x20,
+		     0x0a, 0x90,
+		     0x0c, 0x89,
+		     0x08, 0x35};
+
+	printf("DVI:   ");
+
+	oldbus = I2C_GET_BUS();
+	I2C_SET_BUS(0);
+
+	for (i = 0; i < sizeof(u); i += 2)
+		if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+			ret = -1;
+			break;
+		}
+
+	if (ret == 0)
+		printf("initialized\n");
+	else
+		printf("failed - cannot initialize DVI transmitter\n");
+
+	I2C_SET_BUS(oldbus);
+	return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	dvi_init();
+	return 0;
+}
+U_BOOT_CMD(
+	dviinit, 1, 1, do_dviinit,
+	"Initialize DVI Panellink transmitter",
+	""
+);
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ *       Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long long start, end;
+	char c, cmd[CONFIG_SYS_CBSIZE];
+	char *p, *d = cmd;
+	int ret, i;
+	ulong us;
+
+	for (i = 1; i < argc; i++) {
+		p = argv[i];
+
+		if (i > 1)
+			*d++ = ' ';
+
+		while ((c = *p++) != '\0') {
+			*d++ = c;
+		}
+	}
+	*d = '\0';
+
+	start = get_ticks();
+	ret = run_command(cmd, 0);
+	end = get_ticks();
+
+	printf("ticks=%ld\n", (ulong)(end - start));
+	us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+	printf("usec=%ld\n", us);
+
+	return ret;
+}
+U_BOOT_CMD(
+	time,	CONFIG_SYS_MAXARGS,	1,	do_time,
+	"run command and output execution time",
+	""
+);
+
+extern void video_hw_rectfill (
+	unsigned int bpp,		/* bytes per pixel */
+	unsigned int dst_x,		/* dest pos x */
+	unsigned int dst_y,		/* dest pos y */
+	unsigned int dim_x,		/* frame width */
+	unsigned int dim_y,		/* frame height */
+	unsigned int color		/* fill color */
+	);
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+	if (r == 0 || r == 1 || r == -1)
+		r = rprime; /* keep from getting stuck */
+
+	r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+	Y = (r >> 16) % max; /* choose upper bits and reduce */
+	return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int color;
+	unsigned int x, y, dx, dy;
+
+	while (!ctrlc()) {
+		x = prng(1280 - 1);
+		y = prng(1024 - 1);
+		dx = prng(1280- x - 1);
+		dy = prng(1024 - y - 1);
+		color = prng(0x10000);
+		video_hw_rectfill(2, x, y, dx, dy, color);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	gfxdemo,	CONFIG_SYS_MAXARGS,	1,	do_gfxdemo,
+	"demo",
+	""
+);
diff --git a/roms/u-boot/board/esd/du440/du440.h b/roms/u-boot/board/esd/du440/du440.h
new file mode 100644
index 00000000..df065ba0
--- /dev/null
+++ b/roms/u-boot/board/esd/du440/du440.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDR0_USB0		0x0320     /* USB Control Register */
+
+#define CONFIG_SYS_GPIO0_EP_EEP	(0x80000000 >> 23)       /* GPIO0_23 */
+#define CONFIG_SYS_GPIO1_DCF77		(0x80000000 >> (42-32))  /* GPIO1_42 */
+
+#define CONFIG_SYS_GPIO1_IORSTN	(0x80000000 >> (55-32))  /* GPIO1_55 */
+#define CONFIG_SYS_GPIO1_IORST2N	(0x80000000 >> (47-32))  /* GPIO1_47 */
+
+#define CONFIG_SYS_GPIO1_HWVER_MASK	0x000000f0 /* GPIO1_56-59 */
+#define CONFIG_SYS_GPIO1_HWVER_SHIFT	4
+#define CONFIG_SYS_GPIO1_LEDUSR1	0x00000008 /* GPIO1_60 */
+#define CONFIG_SYS_GPIO1_LEDUSR2	0x00000004 /* GPIO1_61 */
+#define CONFIG_SYS_GPIO1_LEDPOST	0x00000002 /* GPIO1_62 */
+#define CONFIG_SYS_GPIO1_LEDDU		0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK	0x0f
+#define PWR_INT_FLAG		0x80
+#define PWR_RDY			0x10
+
+#define CPLD_IRQ		(32+30)
diff --git a/roms/u-boot/board/esd/du440/init.S b/roms/u-boot/board/esd/du440/init.S
new file mode 100644
index 00000000..ab4b6ced
--- /dev/null
+++ b/roms/u-boot/board/esd/du440/init.S
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+	/* TLB-entry for PCI IO */
+	tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
+
+	/* TLB-entries for EBC:	 CPLD, DUMEM, DUIO */
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for NAND */
+	tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
+	tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
+
+	/* TLB-entry PCI registers */
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	tlbtab_end
diff --git a/roms/u-boot/board/esd/hh405/Makefile b/roms/u-boot/board/esd/hh405/Makefile
new file mode 100644
index 00000000..fba21a3a
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= hh405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
diff --git a/roms/u-boot/board/esd/hh405/flash.c b/roms/u-boot/board/esd/hh405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/hh405/fpgadata.c b/roms/u-boot/board/esd/hh405/fpgadata.c
new file mode 100644
index 00000000..620c7144
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/fpgadata.c
@@ -0,0 +1,5034 @@
+0x1f, 0x8b, 0x08, 0x08, 0x7a, 0x8e, 0xc6, 0x43,
+0x00, 0x03, 0x68, 0x68, 0x34, 0x30, 0x35, 0x5f,
+0x31, 0x5f, 0x30, 0x36, 0x2e, 0x62, 0x69, 0x74,
+0x00, 0xec, 0xfd, 0x7f, 0x7c, 0x14, 0x55, 0x9a,
+0x2f, 0x8e, 0x3f, 0x75, 0xaa, 0x12, 0x4e, 0xba,
+0x3a, 0xe9, 0x22, 0x09, 0x4e, 0x54, 0xc4, 0x4a,
+0x27, 0x30, 0x4d, 0xec, 0x84, 0xa6, 0x83, 0x21,
+0x42, 0x48, 0x2a, 0x9d, 0xe8, 0x44, 0x40, 0xe9,
+0x71, 0xdc, 0x59, 0x76, 0xae, 0x77, 0xb6, 0x65,
+0x98, 0xbd, 0x99, 0xb9, 0xe8, 0x46, 0xc7, 0xbb,
+0x97, 0xf1, 0xce, 0x8f, 0x93, 0x4e, 0x80, 0x4e,
+0x82, 0xd0, 0x20, 0x33, 0x46, 0x87, 0x71, 0x9b,
+0x10, 0x35, 0x2a, 0x33, 0xdb, 0x04, 0x94, 0xf0,
+0x63, 0xb0, 0x12, 0xa3, 0x36, 0x10, 0x20, 0x32,
+0xdc, 0x19, 0x54, 0x46, 0x1b, 0x8c, 0x4c, 0xd4,
+0xe8, 0x04, 0x44, 0x4d, 0xf8, 0xf9, 0x7d, 0x4e,
+0x75, 0xa7, 0xbb, 0x1a, 0x77, 0xf7, 0xce, 0xfd,
+0xdc, 0xd7, 0xf7, 0xf3, 0xda, 0xd7, 0xeb, 0x73,
+0xb3, 0x7f, 0xec, 0x99, 0xea, 0x43, 0x59, 0x75,
+0xea, 0x9c, 0xe7, 0x79, 0x3f, 0xbf, 0xde, 0x0f,
+0x64, 0xd8, 0x46, 0x63, 0xff, 0x07, 0x20, 0xdc,
+0x0f, 0xb6, 0xfa, 0xfa, 0x39, 0xae, 0x5b, 0xff,
+0x7e, 0xf6, 0xdf, 0xbb, 0xca, 0x4a, 0x1e, 0xfc,
+0xde, 0x72, 0x58, 0x06, 0xb2, 0xfb, 0x47, 0xb7,
+0xba, 0xbe, 0xff, 0xc8, 0x43, 0xb3, 0xe7, 0xcc,
+0x81, 0xef, 0xe1, 0xff, 0x72, 0xb9, 0xca, 0x66,
+0xb9, 0x66, 0xcf, 0x9a, 0xed, 0x86, 0xe5, 0x90,
+0x31, 0xbb, 0x7c, 0xde, 0xec, 0x39, 0xf3, 0x4a,
+0x6f, 0x85, 0xef, 0x83, 0x50, 0xda, 0x79, 0x15,
+0xff, 0x5e, 0x78, 0xf2, 0x6f, 0xfe, 0xc1, 0x05,
+0x4c, 0x00, 0x80, 0x49, 0x2e, 0xc1, 0xc7, 0xff,
+0xbf, 0xec, 0x12, 0x54, 0x01, 0x58, 0x55, 0xb1,
+0x0b, 0x74, 0xfe, 0xbf, 0x21, 0xfe, 0x7b, 0x86,
+0x0b, 0x54, 0xf3, 0xff, 0x16, 0x5c, 0xa0, 0x81,
+0x17, 0xb4, 0xb5, 0x6a, 0x36, 0xfc, 0x15, 0x7f,
+0x92, 0xc4, 0x26, 0x86, 0x7f, 0xd5, 0x7c, 0x48,
+0xcc, 0xbf, 0x7a, 0x90, 0xfd, 0x9b, 0x93, 0x92,
+0x7f, 0x55, 0xe7, 0x42, 0xf1, 0x91, 0x4a, 0x5c,
+0xff, 0xeb, 0xe9, 0x42, 0x2d, 0x4c, 0xdc, 0xf5,
+0xbd, 0xb7, 0xff, 0x9a, 0xfb, 0xcf, 0xff, 0x62,
+0xe2, 0xfe, 0xff, 0xbb, 0xf3, 0x41, 0xf9, 0x2b,
+0xa6, 0xe3, 0xfb, 0x4e, 0x0c, 0xde, 0x53, 0x04,
+0x1f, 0xe4, 0xc1, 0x75, 0x90, 0xc6, 0x80, 0x0f,
+0xd2, 0x41, 0xf8, 0x57, 0x06, 0xf3, 0xfb, 0x27,
+0xe6, 0xeb, 0x8d, 0xfb, 0xe0, 0x08, 0x2b, 0x55,
+0xad, 0x11, 0xd1, 0x0d, 0xef, 0xe5, 0x57, 0x45,
+0x96, 0x9c, 0xcb, 0xd9, 0xd7, 0x7c, 0xf5, 0x7b,
+0x73, 0x23, 0xb6, 0x73, 0x62, 0x39, 0x3b, 0x09,
+0x3f, 0x1a, 0xb5, 0x8e, 0xe5, 0x8c, 0x4a, 0x0d,
+0x13, 0xf3, 0xe9, 0x08, 0x6d, 0x65, 0xee, 0x7c,
+0x1a, 0x90, 0xed, 0x70, 0x48, 0x29, 0x19, 0x92,
+0x1b, 0x49, 0xd1, 0xd2, 0x3d, 0xd9, 0x25, 0x47,
+0x6c, 0xfb, 0x48, 0x97, 0x16, 0x90, 0xca, 0x22,
+0x96, 0x1e, 0x31, 0x2c, 0x4d, 0xac, 0x62, 0x44,
+0x5a, 0xbb, 0xa5, 0x55, 0x98, 0xa1, 0x65, 0x30,
+0xbb, 0x0f, 0x1e, 0x17, 0x9c, 0xda, 0x8d, 0x2e,
+0xb2, 0x56, 0xda, 0xa1, 0x3a, 0x41, 0xce, 0x25,
+0x54, 0xd9, 0x20, 0x86, 0x74, 0xea, 0x22, 0xe7,
+0x84, 0xc4, 0xfd, 0xa5, 0x6d, 0xe9, 0xad, 0xcc,
+0xae, 0x65, 0x04, 0x48, 0x3e, 0x6b, 0xcb, 0x2b,
+0xd1, 0x64, 0xd6, 0xba, 0x0d, 0xf6, 0x92, 0x12,
+0x62, 0x09, 0xf6, 0x75, 0x41, 0x06, 0xfb, 0x07,
+0xdd, 0x12, 0xf6, 0x8c, 0x4a, 0xbe, 0xf8, 0xfc,
+0xea, 0x29, 0x2b, 0x20, 0xd2, 0x38, 0x67, 0x4e,
+0x71, 0xab, 0x28, 0xc2, 0xdb, 0x5a, 0xa5, 0xbe,
+0x64, 0x8e, 0xfc, 0x5b, 0xed, 0x62, 0xb0, 0x64,
+0xb0, 0x26, 0x5c, 0x9a, 0x05, 0xdf, 0x09, 0xd9,
+0x7b, 0xad, 0xe1, 0x82, 0x41, 0x98, 0xb8, 0x7f,
+0x48, 0xd8, 0x0c, 0x97, 0x68, 0x15, 0xcb, 0xd2,
+0x73, 0xba, 0xe1, 0x8a, 0x50, 0xa5, 0x2f, 0x89,
+0x36, 0xd5, 0xc3, 0x05, 0xa8, 0xd4, 0xd7, 0x87,
+0x0b, 0x46, 0xd8, 0x85, 0x8c, 0xaa, 0xb3, 0xb6,
+0x51, 0xb1, 0x0b, 0x26, 0xee, 0xdf, 0xaf, 0x6c,
+0x83, 0x71, 0xbf, 0xdb, 0x63, 0x63, 0xe2, 0x29,
+0x38, 0xa8, 0xb9, 0xf5, 0x69, 0x3b, 0x73, 0xb6,
+0xd1, 0x43, 0xe0, 0xde, 0x60, 0xdd, 0x29, 0x3a,
+0xe1, 0x10, 0x2b, 0xd3, 0x97, 0x84, 0x6b, 0x46,
+0x41, 0x8d, 0xcf, 0x3f, 0x91, 0x56, 0x21, 0x6c,
+0xd7, 0xec, 0x63, 0x8b, 0x24, 0x32, 0xcc, 0x5a,
+0xc1, 0x1d, 0x99, 0xda, 0x49, 0x9c, 0xd0, 0x26,
+0xd9, 0x19, 0x2d, 0xc7, 0xc1, 0x3b, 0x7e, 0xbb,
+0x2e, 0x87, 0xc9, 0x17, 0xb8, 0xfb, 0x27, 0xde,
+0x77, 0xb1, 0xb5, 0x5b, 0xdb, 0x16, 0x92, 0x67,
+0xa4, 0xbf, 0xaa, 0x36, 0x0a, 0x85, 0xa1, 0x0c,
+0x17, 0x59, 0x0d, 0x1b, 0x24, 0x9f, 0x6e, 0x71,
+0x10, 0x02, 0xcf, 0xd7, 0xe2, 0x7c, 0x17, 0x19,
+0xc3, 0xb3, 0x12, 0xfb, 0x1b, 0x85, 0xef, 0xb2,
+0x97, 0x59, 0xf1, 0x29, 0xd9, 0x97, 0x7e, 0x4c,
+0x12, 0x98, 0x1a, 0xa5, 0x27, 0x48, 0xb6, 0xba,
+0x69, 0x63, 0x7e, 0xd4, 0x52, 0x8f, 0x83, 0x5d,
+0x41, 0x21, 0x2a, 0xaf, 0xd4, 0xae, 0x24, 0xee,
+0x5f, 0x07, 0x8b, 0xb5, 0x6e, 0xa8, 0x60, 0xb6,
+0x7c, 0x51, 0xef, 0xeb, 0x85, 0x39, 0x8a, 0x1c,
+0x16, 0x9b, 0xc9, 0x9b, 0x10, 0xd6, 0x4a, 0x94,
+0x36, 0x20, 0xef, 0x87, 0x82, 0xba, 0xcd, 0x25,
+0x1e, 0x23, 0x13, 0xfb, 0x41, 0xbb, 0x69, 0xdf,
+0xd0, 0x17, 0x50, 0xaa, 0xdb, 0xb6, 0x88, 0x83,
+0xda, 0x65, 0xe5, 0x95, 0xda, 0x59, 0x1b, 0xc4,
+0xf3, 0xf0, 0x3c, 0x54, 0xd5, 0x66, 0x0e, 0x0a,
+0xe7, 0x16, 0x1f, 0x82, 0xf9, 0xfd, 0xeb, 0xc3,
+0xe2, 0x60, 0xfa, 0xc4, 0xfa, 0x50, 0x69, 0x1b,
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+0xa5, 0x65, 0x61, 0xd8, 0x4b, 0xa1, 0xdd, 0xbe,
+0xcf, 0x4b, 0xe8, 0x7b, 0x7b, 0xe1, 0x18, 0x64,
+0x07, 0x63, 0x53, 0x93, 0x25, 0x38, 0xd6, 0x94,
+0x65, 0xf7, 0x67, 0xb9, 0x89, 0xc8, 0x35, 0xa1,
+0x98, 0xb7, 0x5e, 0x14, 0xd7, 0xab, 0x8f, 0x34,
+0xe3, 0x32, 0xd9, 0x55, 0xd7, 0xb0, 0xf5, 0x6a,
+0x30, 0x65, 0xcd, 0x5b, 0xaf, 0x22, 0x7e, 0xbc,
+0x47, 0x9c, 0xe6, 0xfd, 0xe1, 0xe3, 0xf6, 0x07,
+0x86, 0xc9, 0x7e, 0xdd, 0x5e, 0x81, 0x2b, 0xe0,
+0x9a, 0x33, 0x75, 0xe3, 0xcb, 0x3f, 0x98, 0x59,
+0x7b, 0x69, 0xa2, 0x18, 0x2e, 0x22, 0x3d, 0xf6,
+0xd0, 0x04, 0x0d, 0x6f, 0x87, 0x4b, 0x0c, 0x2c,
+0x8b, 0xe1, 0x24, 0x33, 0x94, 0x9b, 0xb3, 0xbe,
+0xf9, 0xc9, 0x29, 0xa5, 0xc1, 0xd4, 0x7e, 0x5c,
+0xdf, 0xc3, 0x4a, 0xe9, 0x4c, 0xca, 0x1c, 0x8e,
+0xeb, 0x37, 0x9b, 0x86, 0xf9, 0x11, 0x7c, 0xc8,
+0x2e, 0x46, 0xf2, 0x8b, 0x85, 0xec, 0x8a, 0x70,
+0xc3, 0xe5, 0xc3, 0x86, 0x4b, 0x85, 0x94, 0x14,
+0x2c, 0xc1, 0x87, 0x36, 0xa7, 0x41, 0x34, 0x3e,
+0x2c, 0x64, 0x66, 0x26, 0x97, 0x6e, 0xcc, 0x3f,
+0xd6, 0xf6, 0xf6, 0xb6, 0x68, 0x3e, 0xa7, 0x25,
+0xf7, 0x32, 0x3e, 0xcc, 0x63, 0xc6, 0xb1, 0xb8,
+0xe1, 0xf9, 0x07, 0xcd, 0x20, 0x1a, 0x5f, 0xfc,
+0xf0, 0x48, 0x0c, 0xb9, 0x29, 0x50, 0x9b, 0x8c,
+0x18, 0xa4, 0xc0, 0x62, 0x6a, 0x92, 0x5f, 0x3b,
+0xd9, 0x26, 0x0c, 0xf8, 0x84, 0x10, 0xe8, 0x40,
+0x15, 0xba, 0xa1, 0x09, 0xf8, 0xed, 0xf2, 0xc2,
+0xf8, 0xf9, 0xb0, 0xbb, 0x21, 0xff, 0x8c, 0x87,
+0x1f, 0xa3, 0x95, 0x0b, 0xe9, 0xf5, 0xf6, 0xf8,
+0xaa, 0x56, 0xfa, 0x0d, 0x1a, 0x75, 0x3c, 0xd4,
+0x4a, 0x2f, 0x5e, 0xe8, 0x5d, 0x9f, 0x18, 0x0f,
+0x85, 0xb9, 0x89, 0xfb, 0xc6, 0x43, 0x0a, 0x15,
+0xdc, 0xf4, 0xa7, 0x70, 0xf7, 0x3f, 0xcf, 0xf8,
+0x10, 0x5c, 0xc3, 0x79, 0xe0, 0x3b, 0xd7, 0x24,
+0x1d, 0xdf, 0x78, 0x38, 0x16, 0x32, 0x3e, 0x5c,
+0x3a, 0x3a, 0xea, 0xe7, 0xc3, 0xf7, 0xeb, 0x7c,
+0xb8, 0xb7, 0x91, 0x0f, 0x39, 0x7d, 0x31, 0x3e,
+0xdc, 0x78, 0x68, 0x8b, 0x9f, 0x0f, 0xaf, 0xdf,
+0x25, 0x3e, 0xe4, 0x58, 0xf8, 0xdb, 0x54, 0x6d,
+0x61, 0xe0, 0x4f, 0x01, 0x8a, 0x07, 0xbb, 0xde,
+0x65, 0x58, 0x38, 0xf5, 0xd6, 0xc2, 0xea, 0x9a,
+0x6b, 0xfc, 0xed, 0xf9, 0xd9, 0xff, 0xb8, 0x8a,
+0xed, 0xff, 0x12, 0xa0, 0xb8, 0xb0, 0xf1, 0x10,
+0xc3, 0xc2, 0xab, 0xd7, 0x16, 0x36, 0xd6, 0x5c,
+0xd3, 0xd0, 0xbe, 0xd3, 0xe5, 0xc3, 0x4c, 0xe7,
+0xe6, 0x5f, 0xa6, 0x7b, 0x90, 0x0f, 0x33, 0x2f,
+0x6f, 0x3e, 0xc7, 0x09, 0x33, 0xc3, 0x51, 0xb3,
+0x72, 0xed, 0x3f, 0x8c, 0xdf, 0x04, 0x83, 0xb0,
+0xdb, 0x33, 0x4c, 0xc8, 0xc5, 0xef, 0xbc, 0x17,
+0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29,
+0x29, 0x29, 0xa9, 0xff, 0xbb, 0x78, 0xed, 0xa0,
+0xc8, 0xda, 0x41, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0xea, 0xd6, 0xe2,
+0xb5, 0x43, 0x54, 0xd6, 0x0e, 0x52, 0x52, 0x52,
+0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52,
+0xb7, 0x16, 0xaf, 0x1d, 0x54, 0x5e, 0x3b, 0xe0,
+0x5f, 0x91, 0xbe, 0x27, 0x77, 0xd3, 0x81, 0xfe,
+0x97, 0x76, 0x07, 0x74, 0xb6, 0xee, 0x73, 0xf0,
+0x00, 0xcd, 0x58, 0xd0, 0x70, 0x13, 0xda, 0x5d,
+0x94, 0xd2, 0xf4, 0xcc, 0x31, 0x7b, 0x69, 0xdb,
+0x97, 0x85, 0x60, 0xba, 0x87, 0x81, 0x39, 0x36,
+0x7e, 0x0a, 0x03, 0x4e, 0x30, 0xfd, 0x2b, 0xc6,
+0xcc, 0x09, 0x67, 0xe5, 0xc5, 0xd7, 0x5f, 0x09,
+0xa6, 0x7b, 0x30, 0xe7, 0xcc, 0xdf, 0x69, 0x66,
+0xbf, 0x63, 0x3a, 0xc1, 0xf4, 0x9f, 0x78, 0xf8,
+0xe0, 0x11, 0xa7, 0xe3, 0x93, 0xa7, 0xb7, 0x04,
+0xd3, 0x3d, 0xce, 0xbf, 0x18, 0x7f, 0x50, 0xf3,
+0x1f, 0x5f, 0x73, 0xdc, 0x86, 0x47, 0x57, 0x54,
+0x83, 0x9b, 0xff, 0x65, 0x18, 0x3f, 0x5b, 0x20,
+0xa8, 0xf9, 0x6f, 0xce, 0x9e, 0x9e, 0x87, 0x7b,
+0x76, 0x7c, 0xbe, 0x29, 0x98, 0xee, 0x71, 0xfe,
+0xc5, 0xf8, 0x03, 0x8b, 0xff, 0xb5, 0x6d, 0x1f,
+0xd3, 0xa5, 0xcf, 0xcf, 0xa8, 0xb7, 0x6f, 0x7a,
+0x47, 0x32, 0xe7, 0x06, 0x30, 0x7e, 0x0e, 0x05,
+0x17, 0xff, 0x1a, 0xd9, 0x00, 0xab, 0x63, 0xf7,
+0x06, 0x17, 0xff, 0x62, 0xfc, 0x41, 0xcd, 0x7f,
+0x22, 0x6d, 0x0d, 0xc3, 0xba, 0xeb, 0xd9, 0xa0,
+0xe2, 0xc7, 0xac, 0x39, 0x2c, 0x7f, 0x9a, 0xf3,
+0x4e, 0x30, 0xfd, 0x2b, 0xea, 0x81, 0x37, 0x9d,
+0x0d, 0x9f, 0xce, 0x04, 0x96, 0xff, 0xdd, 0xf1,
+0xdf, 0xfc, 0xcb, 0x04, 0x77, 0x47, 0x4a, 0x66,
+0xe6, 0x94, 0x93, 0x59, 0x31, 0x1d, 0x58, 0xfe,
+0xa9, 0xcd, 0xb3, 0xfc, 0x39, 0x1f, 0xd4, 0xfc,
+0x2f, 0xeb, 0xff, 0xf5, 0x9a, 0xd3, 0xfb, 0xe3,
+0xe3, 0x73, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6,
+0x1f, 0xd8, 0xfc, 0xf7, 0xbf, 0xf6, 0x8e, 0xfd,
+0xd0, 0x8a, 0x93, 0xb1, 0xdb, 0x37, 0xbd, 0x23,
+0x99, 0xb5, 0x39, 0x96, 0x3f, 0x03, 0x8b, 0xff,
+0x68, 0xe7, 0xa9, 0x67, 0xed, 0xec, 0x57, 0x3f,
+0x59, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6, 0x1f,
+0xd8, 0xfc, 0xaf, 0xde, 0xf1, 0x05, 0x18, 0x6d,
+0x6f, 0x07, 0x97, 0x7f, 0x6a, 0x2c, 0x7f, 0x06,
+0x17, 0xff, 0x2b, 0x23, 0x69, 0xda, 0x7f, 0x32,
+0xf1, 0x7d, 0x30, 0xdd, 0xb3, 0x1f, 0x39, 0xe1,
+0xe3, 0x0f, 0x66, 0xfe, 0x4d, 0xf6, 0x7c, 0x1c,
+0xbc, 0xd8, 0x6a, 0x82, 0xcd, 0x9e, 0x5a, 0x09,
+0x9b, 0x40, 0xff, 0xf5, 0xff, 0x13, 0xdc, 0xf7,
+0x46, 0x4c, 0xa8, 0x12, 0xaf, 0xcf, 0x2b, 0x7b,
+0x6e, 0x6c, 0xf7, 0x37, 0xea, 0xe7, 0xba, 0x8f,
+0xf0, 0x33, 0x01, 0x00,
diff --git a/roms/u-boot/board/esd/hh405/hh405.c b/roms/u-boot/board/esd/hh405/hh405.c
new file mode 100644
index 00000000..8bd4223b
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/hh405.c
@@ -0,0 +1,895 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006-2007
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <sm501.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* FPGA internal regs */
+#define FPGA_CTRL	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
+#define FPGA_STATUS	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
+#define FPGA_CTR	((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
+#define FPGA_BL		((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
+
+/* FPGA Control Reg */
+#define FPGA_CTRL_REV0      0x0001
+#define FPGA_CTRL_REV1      0x0002
+#define FPGA_CTRL_VGA0_BL   0x0004
+#define FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define FPGA_CTRL_CF_RESET  0x0040
+#define FPGA_CTRL_PS2_PWR   0x0080
+#define FPGA_CTRL_CF_PWRN   0x0100      /* low active */
+#define FPGA_CTRL_CF_BUS_EN 0x0200
+#define FPGA_CTRL_LCD_CLK   0x7000      /* mask for lcd clock */
+#define FPGA_CTRL_OW_ENABLE 0x8000
+
+#define FPGA_STATUS_CF_DETECT 0x8000
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define SWAP32(x)	 ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+			  (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#define BPP	16
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 1 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+#define BPP	32
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 0 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* GPIO */
+	{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+	{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_320_8bpp[] =
+{
+#include "logo_320_240_8bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+unsigned char logo_bmp_1024[] =
+{
+#include "logo_1024_768_8bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13705_320_240_8bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#include "../common/s1d13806_1024_768_8bpp.h"
+
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"hh405/preinst.img", 0, -1, AU_SCRIPT},
+	{"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
+	{"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
+	{"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
+	{"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
+	{"hh405/postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+/*
+ * Get version of HH405 board from GPIO's
+ */
+int board_revision(void)
+{
+	unsigned long osrh_reg;
+	unsigned long isr1h_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
+	 */
+	osrh_reg = in_be32((void *)GPIO0_OSRH);
+	isr1h_reg = in_be32((void *)GPIO0_ISR1H);
+	tcr_reg = in_be32((void *)GPIO0_TCR);
+	out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in_be32((void *)GPIO0_IR) & 0x80400000;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out_be32((void *)GPIO0_OSRH, osrh_reg);                   /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1h_reg);                 /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x80000000) {
+		/* Revision 1.0 or 1.1 detected */
+		return 1;
+	} else {
+		if (value & 0x00400000) {
+			/* unused */
+			return 3;
+		} else {
+			return 2;
+		}
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int cf_enable(void)
+{
+	int i;
+
+	if (gd->board_type >= 2) {
+		if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
+			if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
+				out_be16(FPGA_CTRL,
+					 in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
+
+				for (i=0; i<300; i++)
+					udelay(1000);
+
+				out_be16(FPGA_CTRL,
+					 in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
+
+				for (i=0; i<20; i++)
+					udelay(1000);
+			}
+		} else {
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
+		}
+	}
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+	unsigned long contrast0 = 0xffffffff;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	/* setup FPGA_INIT as output */
+	out_be32((void *)GPIO0_TCR,
+		 in_be32((void *)GPIO0_TCR) | FPGA_INIT);
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write Board revision into FPGA
+	 */
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
+
+	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Reset touch-screen controller
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
+	udelay(1000);
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
+	for (i=0;i<500;i++)
+		udelay(1000);
+	out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
+
+	/*
+	 * Get contrast value from environment variable
+	 */
+	str = getenv("contrast0");
+	if (str) {
+		contrast0 = simple_strtol(str, NULL, 16);
+		if (contrast0 > 255) {
+			printf("ERROR: contrast0 value too high (0x%lx)!\n",
+			       contrast0);
+			contrast0 = 0xffffffff;
+		}
+	}
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc230") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
+		out_be16(FPGA_BL, 0x0000);
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_1024_768_8bpp,
+			 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
+			 logo_bmp_1024, sizeof(logo_bmp_1024));
+	} else if (strcmp(str, "ppc220") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
+		out_be16(FPGA_BL, 0x0000);
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else if (strcmp(str, "ppc215") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			out_be16(FPGA_CTR, 0x0082);
+		} else {
+			out_be16(FPGA_CTR, contrast0);
+		}
+		out_be16(FPGA_BL, 0xffff);
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 FPGA_CTRL_VGA0_BL |
+			 FPGA_CTRL_VGA0_BL_MODE);
+		/*
+		 * Set lcd clock (small epson)
+		 */
+		out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
+		udelay(100);               /* wait for 100 us */
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13705_320_240_8bpp,
+			 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
+			 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
+	} else if (strcmp(str, "ppc210") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			out_be16(FPGA_CTR, 0x0060);
+		} else {
+			out_be16(FPGA_CTR, contrast0);
+		}
+		out_be16(FPGA_BL, 0xffff);
+		/*
+		 * Switch backlight on
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 FPGA_CTRL_VGA0_BL |
+			 FPGA_CTRL_VGA0_BL_MODE);
+		/*
+		 * Set lcd clock (small epson), enable 1-wire interface
+		 */
+		out_be16(FPGA_CTRL,
+			 in_be16(FPGA_CTRL) |
+			 LCD_CLK_08330 |
+			 FPGA_CTRL_OW_ENABLE);
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+#ifdef CONFIG_VIDEO_SM501
+	} else {
+		pci_dev_t devbusfn;
+
+		/*
+		 * Is SM501 connected (ppc221/ppc231)?
+		 */
+		devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+		if (devbusfn != -1) {
+			puts("VGA:   SM501 with 8 MB ");
+			if (strcmp(str, "ppc221") == 0) {
+				printf("(800*600, %dbpp)\n", BPP);
+				out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
+			} else if (strcmp(str, "ppc231") == 0) {
+				printf("(1024*768, %dbpp)\n", BPP);
+				out_be16(FPGA_BL, 0x0000);
+			} else {
+				printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+				return 0;
+			}
+		} else {
+			printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+			return 0;
+		}
+#endif /* CONFIG_VIDEO_SM501 */
+	}
+
+	cf_enable();
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev %ld.x)\n", gd->board_type);
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	if (((gd->board_type >= 2) &&
+	     (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
+	    (gd->board_type < 2)) {
+		/*
+		 * Assert or deassert CompactFlash Reset Pin
+		 */
+		if (on) {		/* assert RESET */
+			cf_enable();
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) &
+				 ~FPGA_CTRL_CF_RESET);
+		} else {		/* release RESET */
+			out_be16(FPGA_CTRL,
+				 in_be16(FPGA_CTRL) |
+				 FPGA_CTRL_CF_RESET);
+		}
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+
+#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	char str[64];
+	char str2[64];
+	int i = getenv_f("serial#", str2, sizeof(str));
+
+	if (line_number == 1) {
+		sprintf(str, " Board: ");
+
+		if (i == -1) {
+			strcat(str, "### No HW ID - assuming HH405");
+		} else {
+			strcat(str, str2);
+		}
+
+		if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
+			strcat(str, " (");
+			strcat(str, str2);
+		} else {
+			strcat(str, " (Missing bd_type!");
+		}
+
+		sprintf(str2, ", Rev %ld.x)", gd->board_type);
+		strcat(str, str2);
+		strcpy(info, str);
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+/*
+ * Returns SM501 register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
+		return (addr & 0xfffffffe);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
+		addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+		addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+		return addr;
+	}
+
+	return 0;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return init_regs_800x600;
+	} else {
+		return init_regs_1024x768;
+	}
+}
+
+int board_get_width (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 800;
+	} else {
+		return 1024;
+	}
+}
+
+int board_get_height (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 600;
+	} else {
+		return 768;
+	}
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/hh405/logo_1024_768_8bpp.c b/roms/u-boot/board/esd/hh405/logo_1024_768_8bpp.c
new file mode 100644
index 00000000..331540f7
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/logo_1024_768_8bpp.c
@@ -0,0 +1,5087 @@
+0x1f, 0x8b, 0x08, 0x08, 0x20, 0xb5, 0x06, 0x40,
+0x00, 0x03, 0x48, 0x6f, 0x6c, 0x7a, 0x2d, 0x48,
+0x65, 0x72, 0x5f, 0x64, 0x74, 0x5f, 0x33, 0x43,
+0x5f, 0x31, 0x30, 0x32, 0x34, 0x78, 0x37, 0x36,
+0x38, 0x5f, 0x32, 0x35, 0x36, 0x2e, 0x62, 0x6d,
+0x70, 0x00, 0xec, 0xbd, 0x0b, 0x74, 0x23, 0xd7,
+0x79, 0xa0, 0x59, 0x14, 0x0d, 0x1d, 0x71, 0xb6,
+0xc9, 0x43, 0x37, 0xe4, 0xe4, 0xa8, 0xa2, 0x0c,
+0x80, 0x58, 0xeb, 0x14, 0x48, 0x77, 0x7a, 0xe2,
+0xb4, 0x2c, 0xcb, 0x56, 0x4b, 0xed, 0xb6, 0x8e,
+0xc2, 0x84, 0x4e, 0x6d, 0x83, 0x05, 0x80, 0x8b,
+0x09, 0x0c, 0xec, 0x28, 0x1c, 0xc3, 0x69, 0x39,
+0x41, 0x4f, 0xec, 0xc4, 0xde, 0x44, 0xc1, 0x60,
+0x6d, 0xb5, 0xdb, 0x8c, 0x9b, 0x09, 0x99, 0x75,
+0xbc, 0xd3, 0xed, 0xce, 0x64, 0xc6, 0x36, 0xd0,
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diff --git a/roms/u-boot/board/esd/hh405/logo_320_240_4bpp.c b/roms/u-boot/board/esd/hh405/logo_320_240_4bpp.c
new file mode 100644
index 00000000..52989de4
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/logo_320_240_4bpp.c
@@ -0,0 +1,454 @@
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diff --git a/roms/u-boot/board/esd/hh405/logo_320_240_8bpp.c b/roms/u-boot/board/esd/hh405/logo_320_240_8bpp.c
new file mode 100644
index 00000000..75004483
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/logo_320_240_8bpp.c
@@ -0,0 +1,1042 @@
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diff --git a/roms/u-boot/board/esd/hh405/logo_640_480_24bpp.c b/roms/u-boot/board/esd/hh405/logo_640_480_24bpp.c
new file mode 100644
index 00000000..3f8bb9ec
--- /dev/null
+++ b/roms/u-boot/board/esd/hh405/logo_640_480_24bpp.c
@@ -0,0 +1,8417 @@
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+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x6b, 0xbf,
+0x00, 0xff, 0xcf, 0xfd, 0x4c, 0x36, 0x10, 0x0e,
+0x00,
diff --git a/roms/u-boot/board/esd/hub405/Makefile b/roms/u-boot/board/esd/hub405/Makefile
new file mode 100644
index 00000000..99e18b56
--- /dev/null
+++ b/roms/u-boot/board/esd/hub405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= hub405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/hub405/flash.c b/roms/u-boot/board/esd/hub405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/hub405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/hub405/hub405.c b/roms/u-boot/board/esd/hub405/hub405.c
new file mode 100644
index 00000000..14237443
--- /dev/null
+++ b/roms/u-boot/board/esd/hub405/hub405.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_revision(void)
+{
+	unsigned long osrl_reg;
+	unsigned long isr1l_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HUB405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pin(s) (IRQ6/GPIO23)
+	 */
+	osrl_reg = in_be32((void *)GPIO0_OSRH);
+	isr1l_reg = in_be32((void *)GPIO0_ISR1H);
+	tcr_reg = in_be32((void *)GPIO0_TCR);
+	out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in_be32((void *)GPIO0_IR) & 0x00000100;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out_be32((void *)GPIO0_OSRH, osrl_reg);                   /* output select */
+	out_be32((void *)GPIO0_ISR1H, isr1l_reg);                 /* input select  */
+	out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x00000100) {
+		/* Revision 1.1 or 1.2 detected */
+		return 1;
+	}
+
+	/* Revision 1.0 */
+	return 0;
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+#define LED_REG (DUART0_BA + 0x20)
+int misc_init_r (void)
+{
+	unsigned long val;
+	int delay, flashcnt;
+	char *str;
+	char hw_rev[4];
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	/*
+	 * Set RS232/RS422 control (RS232 = high on GPIO)
+	 */
+	val = in_be32((void *)GPIO0_OR);
+	val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
+		 CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
+
+	str = getenv("phys0");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART2_RS232;
+
+	str = getenv("phys1");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART3_RS232;
+
+	str = getenv("phys2");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART4_RS232;
+
+	str = getenv("phys3");
+	if (!str || (str && (str[0] == '0')))
+		val |= CONFIG_SYS_UART5_RS232;
+
+	out_be32((void *)GPIO0_OR, val);
+
+	/*
+	 * check board type and setup AP power
+	 */
+	str = getenv("bd_type"); /* this is only set on non prototype hardware */
+	if (str != NULL) {
+		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
+			unsigned char led_reg_default = 0;
+			str = getenv("ap_pwr");
+			if (!str || (str && (str[0] == '1')))
+				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
+
+			/*
+			 * Flash LEDs
+			 */
+			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+				/* LED_A..D off */
+				out_8((void *)LED_REG, led_reg_default);
+				for (delay = 0; delay < 100; delay++)
+					udelay(1000);
+				/* LED_A..D on */
+				out_8((void *)LED_REG, led_reg_default | 0xf0);
+				for (delay = 0; delay < 50; delay++)
+					udelay(1000);
+			}
+			out_8((void *)LED_REG, led_reg_default);
+		}
+	}
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Store hardware revision in environment for further processing
+	 */
+	sprintf(hw_rev, "1.%ld", gd->board_type);
+	setenv("hw_rev", hw_rev);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HUB405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld)\n", gd->board_type);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/mecp5123/Makefile b/roms/u-boot/board/esd/mecp5123/Makefile
new file mode 100644
index 00000000..f5ebb014
--- /dev/null
+++ b/roms/u-boot/board/esd/mecp5123/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mecp5123.o
diff --git a/roms/u-boot/board/esd/mecp5123/mecp5123.c b/roms/u-boot/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 00000000..97006116
--- /dev/null
+++ b/roms/u-boot/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
+		return -1;
+
+	if (state == 0)
+		setbits_be32(&im->gpio.gpdat, 0x00100000);
+	else
+		clrbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	int i;
+
+	/*
+	 * Initialize Local Window for boot access
+	 */
+	out_be32(&im->sysconf.lpbaw,
+		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+	sync_law(&im->sysconf.lpbaw);
+
+	/*
+	 * Configure MSCAN clocks
+	 */
+	for (i=0; i<4; ++i) {
+		out_be32(&im->clk.msccr[i], 0x00300000);
+		out_be32(&im->clk.msccr[i], 0x00310000);
+	}
+
+	/*
+	 * Configure GPIO's
+	 */
+	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+	setbits_be32(&im->gpio.gpdir, 0x001000e0);
+	setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 val;
+
+	/*
+	 * Optimize access to profibus chip (VPC3) on the local bus
+	 */
+
+	/*
+	 * Select 1:1 for LPC_DIV
+	 */
+	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
+	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
+
+	/*
+	 * Configure LPC Chips Select Deadcycle Control Register
+	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
+	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+
+	/*
+	 * Configure LPC Chips Select Holdcycle Control Register
+	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
+	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+	return 0;
+}
+
+static iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SELECT LPC_CS1 */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC7_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC9_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC11_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC0=SELECT IRQ0 */
+	{
+		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	puts("Board: MECP_5123\n");
+
+	/*
+	 * Initialize function mux & slew rate IO inter alia on IO
+	 * Pins
+	 */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/roms/u-boot/board/esd/mecp5200/Makefile b/roms/u-boot/board/esd/mecp5200/Makefile
new file mode 100644
index 00000000..3d66c9f5
--- /dev/null
+++ b/roms/u-boot/board/esd/mecp5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= mecp5200.o
diff --git a/roms/u-boot/board/esd/mecp5200/mecp5200.c b/roms/u-boot/board/esd/mecp5200/mecp5200.c
new file mode 100644
index 00000000..17a70a9f
--- /dev/null
+++ b/roms/u-boot/board/esd/mecp5200/mecp5200.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPX CPU5200 (mecp5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == CONFIG_SYS_FLASH_SIZE) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset)
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	else
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/roms/u-boot/board/esd/mecp5200/mt46v16m16-75.h b/roms/u-boot/board/esd/mecp5200/mt46v16m16-75.h
new file mode 100644
index 00000000..63a40323
--- /dev/null
+++ b/roms/u-boot/board/esd/mecp5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/roms/u-boot/board/esd/meesc/Makefile b/roms/u-boot/board/esd/meesc/Makefile
new file mode 100644
index 00000000..5d167382
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= meesc.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/roms/u-boot/board/esd/meesc/meesc.c b/roms/u-boot/board/esd/meesc/meesc.c
new file mode 100644
index 00000000..c5994e0a
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/meesc.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(12),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+	at91_smc_t	*smc1	= (at91_smc_t *) ATMEL_BASE_SMC1;
+
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+	u_char hw_type;	/* hardware type */
+
+	/* read the "Type" register of the ET1100 controller */
+	hw_type = readb(CONFIG_ET1100_BASE);
+
+	switch (hw_type) {
+	case 0x11:
+	case 0x3F:
+		/* ET1100 present, arch number of MEESC-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+		puts("Board: CAN-EtherCAT Gateway");
+		break;
+	case 0xFF:
+		/* no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		puts("Board: EtherCAN/2 Gateway");
+		/* switch on LED1D */
+		at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
+		break;
+	default:
+		/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
+		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+		printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
+		puts("Board: EtherCAN/2 Gateway");
+		break;
+	}
+	if (getenv_f("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char		*str;
+	char		buf[32];
+	at91_pmc_t	*pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	/*
+	 * Normally the processor clock has a divisor of 2.
+	 * In some cases this this needs to be set to 4.
+	 * Check the user has set environment mdiv to 4 to change the divisor.
+	 */
+	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
+		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+		serial_setbrg();
+		/* Notify the user that the clock is not default */
+		printf("Setting master clock to %s MHz\n",
+			strmhz(buf, get_mck_clk_rate()));
+	}
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_early_init_f(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	/* enable all clocks */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
+		&pmc->pcer);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* initialize ET1100 Controller */
+	meesc_ethercat_hw_init();
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	meesc_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/meesc/partition.c b/roms/u-boot/board/esd/meesc/partition.c
new file mode 100644
index 00000000..b6afafc2
--- /dev/null
+++ b/roms/u-boot/board/esd/meesc/partition.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/roms/u-boot/board/esd/ocrtc/Makefile b/roms/u-boot/board/esd/ocrtc/Makefile
new file mode 100644
index 00000000..44b7d5d0
--- /dev/null
+++ b/roms/u-boot/board/esd/ocrtc/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c b/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c
new file mode 100644
index 00000000..6dcbd8b2
--- /dev/null
+++ b/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/4xx_pci.h>
+
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int idx = 1;	  /* start at 1 (skip device 0) */
+	pci_dev_t bdf = 0;
+	u32 addr;
+
+	while (bdf >= 0) {
+		if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
+			break;
+		}
+		printf("Found device nr %d at %x!\n", idx-1, bdf);
+		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+		addr &= ~0xf;
+		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
+		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	setdevice,	1,	1,	do_setdevice,
+	"Set device number on pci adapter boards",
+	""
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 device;
+	char str[32];
+
+	device = *(u32 *)0x0;
+	device = 0x16 - device;      /* calculate vxworks bp slot id */
+	sprintf(str, "%d", device);
+	setenv("slot", str);
+	printf("Variabel slot set to %x\n", device);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getdevice,	1,	1,	do_getdevice,
+	"Get device number and set slot env variable",
+	""
+);
+
+#endif
diff --git a/roms/u-boot/board/esd/ocrtc/flash.c b/roms/u-boot/board/esd/ocrtc/flash.c
new file mode 100644
index 00000000..279746e5
--- /dev/null
+++ b/roms/u-boot/board/esd/ocrtc/flash.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB0CR);
+		base_b1 = -size_b1;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*          printf("PB1CR = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		pbcr = mfdcr (EBC0_CFGDATA);
+		mtdcr (EBC0_CFGADDR, PB1CR);
+		base_b0 = base_b1 - size_b0;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+		mtdcr (EBC0_CFGDATA, pbcr);
+		/*            printf("PB0CR = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/roms/u-boot/board/esd/ocrtc/ocrtc.c b/roms/u-boot/board/esd/ocrtc/ocrtc.c
new file mode 100644
index 00000000..b8159613
--- /dev/null
+++ b/roms/u-boot/board/esd/ocrtc/ocrtc.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "ocrtc.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <command.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+	 * transfers, set device-paced timeout to 256 cycles
+	 */
+	mtebc (EBC0_CFG, 0x20400000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+#ifdef CONFIG_OCRTC
+		puts ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+		puts ("### No HW ID - assuming ORSG");
+#endif
+	} else {
+		puts (str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return (0);
+}
diff --git a/roms/u-boot/board/esd/ocrtc/ocrtc.h b/roms/u-boot/board/esd/ocrtc/ocrtc.h
new file mode 100644
index 00000000..029e27ef
--- /dev/null
+++ b/roms/u-boot/board/esd/ocrtc/ocrtc.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/roms/u-boot/board/esd/otc570/Makefile b/roms/u-boot/board/esd/otc570/Makefile
new file mode 100644
index 00000000..740bb0a2
--- /dev/null
+++ b/roms/u-boot/board/esd/otc570/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				+= otc570.o
+obj-$(CONFIG_HAS_DATAFLASH)	+= partition.o
diff --git a/roms/u-boot/board/esd/otc570/otc570.c b/roms/u-boot/board/esd/otc570/otc570.c
new file mode 100644
index 00000000..4751d0a9
--- /dev/null
+++ b/roms/u-boot/board/esd/otc570/otc570.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2010-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD
+# include <atmel_lcdc.h>
+# include <lcd.h>
+# ifdef CONFIG_LCD_INFO
+#  include <nand.h>
+#  include <version.h>
+# endif
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc 	= (at91_smc_t *) ATMEL_BASE_SMC0;
+	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(12),
+		&smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+	at91_smc_t	*smc1 	= (at91_smc_t *) ATMEL_BASE_SMC1;
+
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+	.vl_col =		640,
+	.vl_row =		480,
+	.vl_clk =		25175000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+
+	.vl_bpix =		LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
+	.vl_tft =		1,	/* 0 = passive, 1 = TFT */
+	.vl_vsync_len =		1,	/* Length of vertical sync in NOL */
+	.vl_upper_margin =	35,	/* Idle lines at the frame start */
+	.vl_lower_margin =	5,	/* Idle lines at the end of the frame */
+	.vl_hsync_len =		5,	/* Width of the LCDHSYNC pulse */
+	.vl_left_margin =	112,	/* Idle cycles at the line beginning */
+	.vl_right_margin =	1,	/* Idle cycles at the end of the line */
+
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+	at91_set_pio_output(AT91_PIO_PORTA, 30, 1);	/* PCI */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	lcd_printf("\n%s\n", U_BOOT_VERSION);
+	lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+	lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
+	lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
+	lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+
+	puts("Board            : esd ARM9 HMI Panel - OTC570");
+	if (getenv_f("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\n");
+	printf("Hardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type        : %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char		str[64];
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	/* Set USART_MODE = 1 (RS485) */
+	writel(1, 0xFFF8C004);
+
+	printf("USART0: ");
+
+	if (getenv_f("usart0", str, sizeof(str)) == -1) {
+		printf("No entry - assuming 1-wire\n");
+		/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+		at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+	} else {
+		if (strcmp(str, "1-wire") == 0) {
+			printf("%s\n", str);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+		} else if (strcmp(str, "rs485") == 0) {
+			printf("%s\n", str);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+		} else {
+			printf("Wrong entry - assuming 1-wire ");
+			printf("(valid values are '1-wire' or 'rs485')\n");
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+		}
+	}
+#ifdef CONFIG_LCD
+	printf("Display memory address: 0x%08lX\n", gd->fb_base);
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_early_init_f(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	/* enable all clocks */
+	writel((1 << ATMEL_ID_PIOA) |
+		(1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOCDE) |
+		(1 << ATMEL_ID_TWI) |
+		(1 << ATMEL_ID_SPI0) |
+#ifdef CONFIG_LCD
+		(1 << ATMEL_ID_LCDC) |
+#endif
+		(1 << ATMEL_ID_UHP),
+		&pmc->pcer);
+
+	at91_seriald_hw_init();
+
+	/* arch number of OTC570-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* initialize ET1100 Controller */
+	otc570_ethercat_hw_init();
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	otc570_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	otc570_lcd_hw_init();
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/otc570/partition.c b/roms/u-boot/board/esd/otc570/partition.c
new file mode 100644
index 00000000..b6afafc2
--- /dev/null
+++ b/roms/u-boot/board/esd/otc570/partition.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/roms/u-boot/board/esd/pci405/Makefile b/roms/u-boot/board/esd/pci405/Makefile
new file mode 100644
index 00000000..9e659c79
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= pci405.o flash.o ../common/misc.o cmd_pci405.o
+obj-y	+= writeibm.o
diff --git a/roms/u-boot/board/esd/pci405/cmd_pci405.c b/roms/u-boot/board/esd/pci405/cmd_pci405.c
new file mode 100644
index 00000000..55c20d02
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/cmd_pci405.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2002-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/processor.h>
+
+#include "pci405.h"
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	int i;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	*ptr = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	if (*ptr == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Save own pci configuration in PRAM
+		 */
+		memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+		for (i=0; i<0x40; i+=4) {
+			pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+		}
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+		printf("\nStoring PCI Configuration Regs...\n");
+	} else {
+		sprintf(addr, "%08x", *ptr);
+
+		/*
+		 * Boot image via bootm
+		 */
+		printf("\nBooting Image at addr 0x%s ...\n", addr);
+		setenv("loadaddr", addr);
+
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		do_bootm (cmdtp, 0, 1, local_args);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"Wait for pci-image and boot it",
+	""
+);
+#endif
diff --git a/roms/u-boot/board/esd/pci405/flash.c b/roms/u-boot/board/esd/pci405/flash.c
new file mode 100644
index 00000000..113111d3
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/pci405/fpgadata.c b/roms/u-boot/board/esd/pci405/fpgadata.c
new file mode 100644
index 00000000..d145826f
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/fpgadata.c
@@ -0,0 +1,1492 @@
+0x1f, 0x8b, 0x08, 0x08, 0xcd, 0x78, 0x61, 0x3f,
+0x00, 0x03, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x34, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xed, 0x9c, 0x7f, 0x78, 0x14, 0xc7,
+0x99, 0xe7, 0xdf, 0xae, 0xee, 0x11, 0x2d, 0xcd,
+0x88, 0x69, 0x89, 0x11, 0x1e, 0x3b, 0x32, 0xdb,
+0x1a, 0x09, 0x3c, 0xc1, 0x23, 0x69, 0x18, 0x61,
+0x85, 0x60, 0x79, 0xd4, 0x8c, 0x04, 0x19, 0x1b,
+0xd9, 0x4c, 0x6c, 0x27, 0x61, 0xf3, 0xf8, 0xc9,
+0x8e, 0x1d, 0x92, 0x23, 0x59, 0x92, 0x47, 0x90,
+0xdc, 0x2e, 0x49, 0x9c, 0x6c, 0x8d, 0x24, 0xd0,
+0x00, 0xb2, 0x19, 0x30, 0x97, 0xb0, 0x59, 0xce,
+0x3b, 0x60, 0x12, 0x0b, 0x9b, 0x64, 0x07, 0x61,
+0x1b, 0x61, 0x88, 0xdd, 0x92, 0x85, 0x23, 0x40,
+0x06, 0x85, 0xf5, 0x79, 0xb1, 0xcd, 0xe2, 0xc1,
+0x91, 0xbd, 0xb2, 0x23, 0x63, 0x19, 0xb3, 0x8e,
+0x00, 0x19, 0xdd, 0x5b, 0xdd, 0x3d, 0xdd, 0x2d,
+0xe1, 0xfd, 0x71, 0xb7, 0xf7, 0xdc, 0xde, 0xf3,
+0x9c, 0xdb, 0x7f, 0xb8, 0x50, 0xa9, 0xba, 0xab,
+0xab, 0xde, 0xfa, 0xd4, 0xf7, 0x7d, 0xdf, 0x6a,
+0x41, 0xbe, 0x7b, 0x54, 0xff, 0x0f, 0x80, 0xbb,
+0x1f, 0xa4, 0xe6, 0xaf, 0x7f, 0x6b, 0x7e, 0xf0,
+0x96, 0x3f, 0x9b, 0xf7, 0x67, 0xc1, 0xf9, 0x55,
+0xdf, 0xfd, 0xfa, 0x0a, 0x78, 0x00, 0x0a, 0x42,
+0xdf, 0x9b, 0x77, 0xcb, 0xf7, 0x57, 0xcf, 0x9b,
+0x3f, 0x1f, 0xbe, 0x0e, 0xce, 0x50, 0x30, 0x58,
+0x53, 0x1d, 0x5c, 0x50, 0x1d, 0xba, 0x05, 0x56,
+0x40, 0xfe, 0xbc, 0x05, 0x0b, 0x83, 0xb7, 0x2c,
+0x9c, 0x57, 0x03, 0xdf, 0x00, 0x88, 0x27, 0x27,
+0xf0, 0x7a, 0xe2, 0xaf, 0xbf, 0xf4, 0xcd, 0x20,
+0x50, 0x0e, 0x00, 0xa6, 0x05, 0xb9, 0x38, 0xfb,
+0x7f, 0x5e, 0x90, 0x93, 0x39, 0xa0, 0xf5, 0x95,
+0x41, 0x50, 0xd9, 0xbf, 0xc1, 0xa8, 0xcf, 0x0f,
+0x82, 0x6c, 0xff, 0x37, 0x17, 0x04, 0x05, 0x62,
+0xe0, 0xf9, 0x0e, 0x14, 0x4b, 0x30, 0xe5, 0xe2,
+0x14, 0x81, 0xea, 0xa5, 0x7f, 0xad, 0x8e, 0x4c,
+0xad, 0x62, 0xd7, 0xbf, 0xa3, 0xae, 0xf8, 0x13,
+0xaa, 0x84, 0xff, 0x58, 0xdd, 0x84, 0x04, 0x71,
+0xf0, 0x42, 0x1e, 0x70, 0xd4, 0x2c, 0xd4, 0xf7,
+0xe9, 0x75, 0xaa, 0x63, 0x5c, 0x7e, 0xbd, 0x68,
+0x46, 0x9f, 0xbb, 0x9f, 0x8c, 0xd3, 0x93, 0x05,
+0x3e, 0xa5, 0x70, 0x8c, 0x0f, 0x42, 0xb3, 0xde,
+0x23, 0xe9, 0x3d, 0xba, 0x59, 0x29, 0xff, 0x47,
+0x67, 0x92, 0x5c, 0x8d, 0x6c, 0x96, 0x7d, 0x59,
+0x31, 0x58, 0x20, 0x0b, 0x41, 0xad, 0x2e, 0xe9,
+0x18, 0x96, 0x1f, 0x89, 0x77, 0xf6, 0x3b, 0x81,
+0x74, 0xc0, 0x63, 0xa2, 0x4f, 0xc9, 0x0f, 0x92,
+0x5d, 0x9c, 0xde, 0x4e, 0x2d, 0xe9, 0x74, 0x3c,
+0x29, 0xcc, 0x55, 0x9d, 0x69, 0x18, 0x11, 0x9e,
+0x04, 0xd6, 0x8e, 0x64, 0x84, 0xb8, 0xde, 0xa7,
+0x92, 0x63, 0xf0, 0xba, 0xb0, 0x50, 0x75, 0xb7,
+0xf1, 0x7b, 0xe1, 0x0f, 0x10, 0x6a, 0x2e, 0xcc,
+0xf0, 0x54, 0xd0, 0xdb, 0x65, 0xb9, 0x27, 0x94,
+0xd7, 0xe1, 0x73, 0x3d, 0xee, 0x97, 0x1b, 0x46,
+0xe0, 0x1f, 0xe0, 0x79, 0xd5, 0x3d, 0xca, 0xaf,
+0x05, 0xbd, 0x9d, 0x22, 0xed, 0x26, 0xc7, 0x21,
+0xa4, 0xba, 0x93, 0xfc, 0x00, 0x1c, 0x87, 0xae,
+0xd8, 0xf4, 0x0c, 0x2f, 0x09, 0xb2, 0x56, 0xd7,
+0xef, 0xa8, 0xfb, 0xb6, 0x9b, 0x94, 0xab, 0xce,
+0xa7, 0xc8, 0x55, 0x79, 0x33, 0xc8, 0xaa, 0x98,
+0x21, 0x21, 0x9c, 0x3f, 0xed, 0x9e, 0x8e, 0x3b,
+0xc9, 0x26, 0xfc, 0x91, 0x33, 0xd8, 0x32, 0x00,
+0x8f, 0x80, 0x4c, 0x0b, 0x82, 0x64, 0x01, 0xce,
+0x2c, 0xbb, 0xe2, 0xdc, 0xac, 0xb6, 0x76, 0x5a,
+0x96, 0x75, 0xfe, 0x29, 0x39, 0x0b, 0x3f, 0xa3,
+0xe5, 0x9d, 0xe2, 0x5a, 0xe2, 0x35, 0xda, 0x45,
+0x45, 0x11, 0x5e, 0x68, 0x09, 0x1e, 0x75, 0xcf,
+0xe7, 0x07, 0x92, 0xaf, 0xd3, 0xe0, 0xf0, 0x5d,
+0x41, 0x67, 0xb1, 0x31, 0x6f, 0xca, 0x8d, 0xdd,
+0xf4, 0x7d, 0x8e, 0x75, 0xaf, 0x61, 0x5c, 0x7e,
+0x1f, 0x6e, 0xa3, 0xee, 0x0f, 0xf8, 0xc1, 0x3c,
+0xbd, 0x9f, 0x9d, 0xdc, 0xb0, 0xe0, 0xfc, 0x76,
+0x78, 0x60, 0x73, 0x95, 0x33, 0x90, 0xbe, 0x22,
+0x97, 0x52, 0x57, 0x86, 0x7f, 0xd7, 0x18, 0xcf,
+0x68, 0xd1, 0xc6, 0x64, 0xbb, 0x5c, 0x39, 0xe0,
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+0x17, 0x2b, 0xe4, 0xc6, 0x2c, 0xc6, 0x21, 0x97,
+0xcc, 0x76, 0xd8, 0x17, 0xd6, 0xce, 0xbc, 0xa7,
+0x82, 0xef, 0xe1, 0x81, 0xc5, 0x6c, 0x6c, 0x70,
+0x0b, 0x64, 0x85, 0x88, 0x71, 0xcf, 0x28, 0x4e,
+0xca, 0x22, 0x2a, 0xc5, 0x05, 0xaf, 0x90, 0x2b,
+0x98, 0xec, 0x89, 0x6a, 0xe7, 0x6c, 0x10, 0xef,
+0xa2, 0x80, 0xee, 0x9b, 0x5e, 0x00, 0xf3, 0x9e,
+0x8c, 0xf3, 0x0c, 0xef, 0xf9, 0x4b, 0x8c, 0x42,
+0xa1, 0xc9, 0x3a, 0x6e, 0x89, 0xb0, 0x3a, 0x51,
+0x1a, 0xff, 0x82, 0xb7, 0xe8, 0x45, 0x61, 0xf5,
+0xba, 0x1d, 0xac, 0x60, 0xbe, 0x1f, 0x8e, 0xf2,
+0x6a, 0xba, 0x23, 0x7e, 0x93, 0x37, 0xff, 0x45,
+0xb2, 0x9a, 0xde, 0xc7, 0x0a, 0xb9, 0xba, 0x18,
+0xe3, 0x3c, 0x6e, 0x0b, 0xb8, 0x3f, 0xbc, 0xe8,
+0x60, 0x37, 0xc0, 0x42, 0xaf, 0x39, 0x9e, 0xc5,
+0x50, 0x41, 0x6f, 0x97, 0x8b, 0xa3, 0xc2, 0x56,
+0xae, 0x82, 0x36, 0xd9, 0xed, 0x53, 0xc1, 0x77,
+0x28, 0xa3, 0xde, 0x78, 0x9e, 0x97, 0x5b, 0x0f,
+0xf7, 0x27, 0xb4, 0x82, 0x69, 0x4b, 0x8b, 0xe3,
+0x8e, 0x05, 0xdc, 0x2c, 0x34, 0x87, 0xa2, 0xac,
+0xb0, 0x56, 0x2f, 0x98, 0x73, 0xc4, 0xdd, 0x0d,
+0x2b, 0xe8, 0xf5, 0x72, 0x5e, 0x94, 0xdb, 0x8a,
+0x05, 0xc3, 0x50, 0x73, 0xfd, 0x64, 0xe3, 0xc9,
+0xf6, 0x00, 0xa9, 0x25, 0x57, 0xb0, 0xc6, 0x33,
+0x02, 0x31, 0x44, 0x7f, 0xa3, 0x58, 0x44, 0x04,
+0x85, 0x6a, 0x05, 0x30, 0xfb, 0x49, 0x20, 0x86,
+0x7b, 0x80, 0xc3, 0xc5, 0x35, 0xe4, 0x0a, 0x8a,
+0xd9, 0x4f, 0x51, 0x78, 0x00, 0x72, 0xba, 0x46,
+0x2f, 0x58, 0xe3, 0x19, 0x21, 0x40, 0x0d, 0xce,
+0x1b, 0x05, 0xf3, 0x9e, 0x9c, 0x52, 0x11, 0x77,
+0x78, 0x61, 0x92, 0x7d, 0x9a, 0xfd, 0x54, 0x80,
+0xfd, 0xa5, 0x85, 0x39, 0x4a, 0x7e, 0x8a, 0xac,
+0x80, 0x52, 0xcd, 0x50, 0xcd, 0x7b, 0xc6, 0xe7,
+0xf8, 0xb9, 0xe9, 0xd0, 0x40, 0xa5, 0xac, 0xb0,
+0x80, 0xbb, 0x81, 0x15, 0x72, 0xef, 0x1e, 0xc3,
+0xa5, 0x51, 0xa6, 0xb8, 0x62, 0xbc, 0x07, 0x8e,
+0xd0, 0x79, 0x8a, 0x28, 0xf1, 0x82, 0xcd, 0x3e,
+0x05, 0x98, 0xad, 0x14, 0x4a, 0xfc, 0xbd, 0xf0,
+0x3b, 0x98, 0xbf, 0x48, 0xfb, 0xa5, 0x5e, 0xab,
+0x9f, 0xc2, 0xfd, 0x3d, 0xde, 0xe0, 0x92, 0xd2,
+0xa2, 0x56, 0x66, 0x9f, 0xc1, 0x25, 0x2e, 0x9b,
+0x7d, 0x2a, 0x68, 0xea, 0xb6, 0xf5, 0x65, 0xe3,
+0xbc, 0xc2, 0x45, 0x1b, 0x43, 0x0c, 0xef, 0x65,
+0x45, 0x1d, 0x8d, 0x0f, 0x5c, 0xaf, 0x15, 0x6c,
+0xf6, 0xa9, 0x4a, 0x3f, 0xf0, 0xcc, 0x5a, 0x5c,
+0xb4, 0x45, 0x69, 0x8c, 0xc5, 0x3c, 0xc2, 0x62,
+0xae, 0x48, 0xb1, 0xd6, 0x11, 0x1b, 0x7a, 0x22,
+0x94, 0x25, 0xc4, 0xb8, 0xa2, 0x4f, 0x06, 0x98,
+0x57, 0x0e, 0xef, 0x42, 0x01, 0x67, 0x14, 0xac,
+0xf1, 0xbc, 0x93, 0xbf, 0x47, 0x79, 0x79, 0xf0,
+0x96, 0xf9, 0x85, 0x66, 0xc1, 0xbc, 0x27, 0x17,
+0xad, 0x58, 0x53, 0x58, 0x4a, 0xbe, 0x50, 0x56,
+0xa4, 0x36, 0xae, 0xc9, 0xdf, 0x31, 0x99, 0x59,
+0x33, 0x6c, 0x9c, 0xef, 0x29, 0x0a, 0x35, 0x36,
+0x6d, 0xb1, 0x9e, 0xf7, 0xbf, 0xcb, 0xf9, 0x4a,
+0x5b, 0xbb, 0xab, 0x53, 0x38, 0x5f, 0x63, 0xbf,
+0xe7, 0x14, 0xce, 0xdf, 0xea, 0xbd, 0xeb, 0x8d,
+0x47, 0x0e, 0x0c, 0xbd, 0x77, 0xe9, 0xd6, 0x9f,
+0xdc, 0x75, 0x76, 0x06, 0x2b, 0x58, 0x75, 0xe8,
+0xc3, 0xec, 0x04, 0xbf, 0x52, 0x50, 0xda, 0x6b,
+0x14, 0x24, 0xab, 0x4e, 0x23, 0x1f, 0x8e, 0x9d,
+0x64, 0x15, 0xac, 0x4b, 0x8b, 0x38, 0x31, 0x1a,
+0x9a, 0x85, 0x6b, 0xda, 0x95, 0xaa, 0xd7, 0xb6,
+0x63, 0xd9, 0x67, 0x48, 0xea, 0x21, 0x1f, 0xbd,
+0x60, 0xd6, 0x4c, 0x99, 0x71, 0xa3, 0x60, 0xd4,
+0x5d, 0xdb, 0xce, 0x56, 0x77, 0x4d, 0x4b, 0xeb,
+0x4f, 0x86, 0x15, 0xb4, 0x87, 0x76, 0x42, 0xa7,
+0x32, 0x57, 0x2a, 0x68, 0x23, 0x5a, 0xa1, 0xb4,
+0xd7, 0x6c, 0xa7, 0xf5, 0x73, 0x12, 0x99, 0xac,
+0x7b, 0x5e, 0xfb, 0x7e, 0x66, 0x9d, 0xc4, 0xfe,
+0x3e, 0xda, 0x40, 0xee, 0xfd, 0x06, 0xe0, 0x7b,
+0x50, 0xda, 0x6b, 0x5a, 0x8c, 0xfe, 0x27, 0x34,
+0x14, 0x52, 0xaa, 0x1a, 0x05, 0xc9, 0xea, 0x0b,
+0x11, 0x58, 0x0c, 0x96, 0x7d, 0x6f, 0x6d, 0x14,
+0xec, 0x93, 0xab, 0x3d, 0x06, 0x72, 0xcf, 0xb3,
+0xff, 0xd1, 0x33, 0x89, 0xf2, 0x41, 0x18, 0xc8,
+0xfd, 0x4b, 0x2f, 0x18, 0xbe, 0xf6, 0xbf, 0x76,
+0xd5, 0xd5, 0x5d, 0xfb, 0x33, 0xb7, 0xfb, 0xdf,
+0x6c, 0xf6, 0x1f, 0xb8, 0xea, 0x27, 0x26, 0x26,
+0xd4, 0x49, 0x85, 0xff, 0x37, 0xeb, 0x72, 0x36,
+0x2f, 0x91, 0xff, 0xf3, 0x36, 0xff, 0x49, 0xed,
+0xa6, 0xda, 0xae, 0x35, 0xb7, 0xff, 0x97, 0x6c,
+0xde, 0x6e, 0xd7, 0xd6, 0x26, 0xfc, 0xbf, 0x6c,
+0xf3, 0x80, 0xa6, 0xae, 0xbd, 0xdf, 0x54, 0x9b,
+0xff, 0x17, 0xdb, 0xc1, 0x27, 0xbc, 0x9f, 0xed,
+0xfa, 0x17, 0xde, 0x1c, 0x98, 0xcd, 0xc3, 0x35,
+0xd7, 0xa7, 0x36, 0xff, 0x1f, 0xa8, 0xfb, 0x97,
+0x2f, 0xf6, 0xb7, 0x1c, 0x89, 0xf6, 0xff, 0x45,
+0xbf, 0xfd, 0xf7, 0xb6, 0xf9, 0xf4, 0xfa, 0xf4,
+0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4,
+0xfa, 0xff, 0xe5, 0xd2, 0xf6, 0x49, 0xa2, 0xed,
+0x93, 0xea, 0x7f, 0x76, 0x5f, 0x3e, 0xbd, 0x3e,
+0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e,
+0xbd, 0xfe, 0x33, 0xae, 0x20, 0xfb, 0x73, 0x09,
+0x50, 0xf9, 0x6b, 0xe3, 0xef, 0xff, 0xf3, 0x41,
+0x50, 0xa6, 0xfd, 0xeb, 0xbf, 0xaf, 0xfd, 0x9e,
+0x23, 0x08, 0x69, 0xce, 0x6a, 0xbf, 0x3b, 0x35,
+0xb5, 0xaf, 0xff, 0x13, 0x87, 0x7b, 0xf6, 0xdd,
+0xd4, 0x60, 0x00, 0x00,
diff --git a/roms/u-boot/board/esd/pci405/pci405.c b/roms/u-boot/board/esd/pci405/pci405.c
new file mode 100644
index 00000000..566f6f77
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/pci405.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/io.h>
+
+#include "pci405.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Prototypes */
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
+
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
+
+
+int board_revision(void)
+{
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of PCI405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in_be32((void*)GPIO0_IR) & 0x00100200;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+	switch (value) {
+	case 0x00100200:
+		/* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+		return 1;
+	case 0x00000200:
+		/* CS2==0 && IRQ5==1 -> version 1.2 */
+		return 2;
+	case 0x00000000:
+		/* CS2==0 && IRQ5==0 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && IRQ5==0 -> version 1.4 */
+		return 4;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
+unsigned long fpga_done_state(void)
+{
+	if (gd->board_type < 2) {
+		return FPGA_DONE_STATE_V11;
+	} else {
+		return FPGA_DONE_STATE_V12;
+	}
+}
+
+
+unsigned long fpga_init_state(void)
+{
+	if (gd->board_type < 2) {
+		return FPGA_INIT_STATE_V11;
+	} else {
+		return FPGA_INIT_STATE_V12;
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	unsigned long CPC0_CR0Reg;
+
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+	 */
+	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
+	out_be32((void*)GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+
+	/*
+	 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
+	 */
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned int *ptr;
+	unsigned int *magic;
+
+	/*
+	 * On PCI-405 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Check if magic for pci reconfig is written
+	 */
+	magic = (unsigned int *)0x00000004;
+	if (*magic == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Rewrite pci config regs (only after soft-reset with magic set)
+		 */
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+			puts("Restoring PCI Configurations Regs!\n");
+			ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+			for (i=0; i<0x40; i+=4) {
+				pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
+			}
+		}
+		mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+
+		*magic = 0;      /* clear pci reconfig magic again */
+	}
+
+	/*
+	 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+	 */
+#define PCI0_BRDGOPT1 0x4a
+	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+
+	/*
+	 * Enable fairness and high bus utilization
+	 */
+	mtdcr(PLB0_ACR, 0x98000000);
+
+	free(dst);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PCI405");
+	} else {
+		puts (str);
+	}
+
+	gd->board_type = board_revision();
+	printf(" (Rev 1.%ld", gd->board_type);
+
+	if (gd->board_type >= 2) {
+		unsigned long CPC0_CR0Reg;
+		unsigned long value;
+
+		/*
+		 * Setup GPIO pins (Trace/GPIO1 to GPIO)
+		 */
+		CPC0_CR0Reg = mfdcr(CPC0_CR0);
+		mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
+		out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+		out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
+		udelay(1000);                   /* wait some time before reading input */
+		value = in_be32((void*)GPIO0_IR) & 0x40000000;       /* get config bits */
+		if (value) {
+			puts(", 33 MHz PCI");
+		} else {
+			puts(", 66 MHz PCI");
+		}
+	}
+
+	puts(")\n");
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#define UART1_MCR 0xef600404
+int wpeeprom(int wp)
+{
+	int wp_state = wp;
+
+	if (wp == 1) {
+		out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
+	} else if (wp == 0) {
+		out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
+	} else {
+		if (in_8((void *)UART1_MCR) & 0x02) {
+			wp_state = 0;
+		} else {
+			wp_state = 1;
+		}
+	}
+	return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int wp = -1;
+	if (argc >= 2) {
+		if (argv[1][0] == '1') {
+			wp = 1;
+		} else if (argv[1][0] == '0') {
+			wp = 0;
+		}
+	}
+
+	wp = wpeeprom(wp);
+	printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+	return 0;
+}
+
+U_BOOT_CMD(
+	wpeeprom,	2,	1,	do_wpeeprom,
+	"Check/Enable/Disable I2C EEPROM write protection",
+	"wpeeprom\n"
+	"    - check I2C EEPROM write protection state\n"
+	"wpeeprom 1\n"
+	"    - enable I2C EEPROM write protection\n"
+	"wpeeprom 0\n"
+	"    - disable I2C EEPROM write protection"
+);
diff --git a/roms/u-boot/board/esd/pci405/pci405.h b/roms/u-boot/board/esd/pci405/pci405.h
new file mode 100644
index 00000000..a62c9c2b
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/pci405.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PCI405_H_
+#define _PCI405_H_
+
+#define PCI_REGS_LEN    0x100
+#define PCI_REGS_ADDR   ((unsigned long)0x01000000 - PCI_REGS_LEN)
+
+#define PCI_RECONFIG_MAGIC  0x07081967
+
+#endif /* _PCI405_H_ */
diff --git a/roms/u-boot/board/esd/pci405/writeibm.S b/roms/u-boot/board/esd/pci405/writeibm.S
new file mode 100644
index 00000000..03eaf97b
--- /dev/null
+++ b/roms/u-boot/board/esd/pci405/writeibm.S
@@ -0,0 +1,205 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
+ */
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*	Bank 0 - Flash and SRAM */
+/*	Bank 1 - NVRAM/RTC */
+/*	Bank 2 - Keyboard/Mouse controller */
+/*	Bank 3 - IR controller */
+/*	Bank 4 - not used */
+/*	Bank 5 - not used */
+/*	Bank 6 - not used */
+/*	Bank 7 - FPGA registers */
+/*----------------------------------------------------------------------------- */
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	write_without_sync
+write_without_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start1:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+
+	b       start1
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_sync
+write_with_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start2
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_less_sync
+write_with_less_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2b:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+/*        sync */
+
+	b       start2b
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_more_sync
+write_with_more_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start3:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+	sync
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+	sync
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id (PCIC0_SBSYSVID)*/
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start3
+
+	blr	/* never reached !!!! */
diff --git a/roms/u-boot/board/esd/pf5200/Makefile b/roms/u-boot/board/esd/pf5200/Makefile
new file mode 100644
index 00000000..a54289c0
--- /dev/null
+++ b/roms/u-boot/board/esd/pf5200/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
+
+# obj-y	= pf5200.o flash.o $(CPLD)
+obj-y	= pf5200.o flash.o
diff --git a/roms/u-boot/board/esd/pf5200/flash.c b/roms/u-boot/board/esd/pf5200/flash.c
new file mode 100644
index 00000000..e1b13bfc
--- /dev/null
+++ b/roms/u-boot/board/esd/pf5200/flash.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK           0x00FF
+
+#define FPW                     FLASH_PORT_WIDTH
+#define FPWV                    FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1            0x0555
+#define FLASH_CYCLE2            0x0aaa
+#define FLASH_ID1               0x00
+#define FLASH_ID2               0x01
+#define FLASH_ID3               0x0E
+#define FLASH_ID4               0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef  CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+	int i;
+	flash_info_t *info;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		info = &flash_info[i];
+		if ((info->size) && (info->start[0] <= base)
+		    && (base <= info->start[0] + info->size - 1)) {
+			break;
+		}
+	}
+	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+	int i;
+	char *fmt;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt);
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+	       info->sector_count);
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		ulong size;
+		int erased;
+		ulong *flash = (unsigned long *)info->start[i];
+
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+		    (i !=
+		     (info->sector_count - 1)) ? (info->start[i + 1] -
+						  info->start[i]) >> 2 : (info->
+									  start
+									  [0] +
+									  info->
+									  size -
+									  info->
+									  start
+									  [i])
+		    >> 2;
+
+		for (flash = (unsigned long *)info->start[i], erased = 1;
+		     (flash != (unsigned long *)info->start[i] + size)
+		     && erased; flash++) {
+			erased = *flash == ~0x0UL;
+		}
+		printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+		       info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+	int i;
+
+	/* Write auto select command: read Manufacturer ID                     */
+	/* Write auto select command sequence and test FLASH answer            */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD        */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.         */
+	/* This works for any bus width and any FLASH device width.            */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0x00ff) {
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus.     */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW) addr[FLASH_ID2]) {
+		case (FPW) AMD_ID_MIRROR:
+			/* MIRROR BIT FLASH, read more ID bytes */
+			if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+			    && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+				/* attention: only the first 16 MB will be used in u-boot */
+				info->flash_id += FLASH_AMLV256U;
+				info->sector_count = 512;
+				info->size = 0x02000000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] =
+					    (ulong) addr + 0x10000 * i;
+				}
+				break;
+			}
+			/* fall thru to here ! */
+		default:
+			printf("unknown AMD device=%x %x %x",
+			       (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+			       (FPW) addr[FLASH_ID4]);
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0x800000;
+			break;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+		if (info->protect[sect] != 0) {	/* protected, skip it */
+			continue;
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel. */
+		/* Let's wait 1 ms.                            */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+			/* show that we're waiting */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {
+				/* every second */
+				putc('.');
+				last = get_timer(0);
+			}
+		}
+		/* show that we're waiting */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {
+			/* every second */
+			putc('.');
+			last = get_timer(0);
+		}
+		flash_reset(info);	/* reset to read mode */
+	}
+	printf(" done\n");
+	return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+	return (res);
+}
diff --git a/roms/u-boot/board/esd/pf5200/mt46v16m16-75.h b/roms/u-boot/board/esd/pf5200/mt46v16m16-75.h
new file mode 100644
index 00000000..63a40323
--- /dev/null
+++ b/roms/u-boot/board/esd/pf5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/roms/u-boot/board/esd/pf5200/pf5200.c b/roms/u-boot/board/esd/pf5200/pf5200.c
new file mode 100644
index 00000000..7a9ed229
--- /dev/null
+++ b/roms/u-boot/board/esd/pf5200/pf5200.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd ParaFinder (pf5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+	}
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+	*(vu_char *) CONFIG_SYS_CS1_START = 0x02;	/* Red Power LED on */
+	__asm__ volatile ("sync");
+
+	*(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
+	__asm__ volatile ("sync");
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void power_set_reset(int power)
+{
+	debug("ide_set_reset(%d)\n", power);
+
+	if (power) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
+		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+		    0) {
+			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+			    GPIO_USB0;
+		}
+
+	}
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	power_set_reset(1);
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
+
+int phypower(int flag)
+{
+	u32 addr;
+	vu_long *reg;
+	int status;
+	pci_dev_t dev;
+
+	dev = PCI_BDF(0, 0x18, 0);
+	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+	if (status == 0) {
+		reg = (vu_long *) (addr + 0x00000040);
+		*reg |= 0x40000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x001000c);
+		*reg |= 0x20000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x0010004);
+		if (flag != 0) {
+			*reg &= ~0x20000000;
+		} else {
+			*reg |= 0x20000000;
+		}
+		__asm__ volatile ("sync");
+	}
+	return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argv[1][0] == '0')
+		(void)phypower(0);
+	else
+		(void)phypower(1);
+
+	return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+	   "Switch power of ethernet phy", "");
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	"Write some data to pcibus",
+	"<addr> <size>\n"
+	""
+);
diff --git a/roms/u-boot/board/esd/plu405/Makefile b/roms/u-boot/board/esd/plu405/Makefile
new file mode 100644
index 00000000..6ffae677
--- /dev/null
+++ b/roms/u-boot/board/esd/plu405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= plu405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/plu405/flash.c b/roms/u-boot/board/esd/plu405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/plu405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/plu405/fpgadata.c b/roms/u-boot/board/esd/plu405/fpgadata.c
new file mode 100644
index 00000000..485b9a20
--- /dev/null
+++ b/roms/u-boot/board/esd/plu405/fpgadata.c
@@ -0,0 +1,2358 @@
+0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46,
+0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74,
+0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e,
+0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b,
+0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19,
+0x07, 0x76, 0xc4, 0x61, 0x18, 0x42, 0x80, 0x98,
+0x0d, 0x49, 0x33, 0xa4, 0xac, 0x71, 0xc9, 0x1e,
+0xf1, 0xce, 0xbb, 0xe2, 0xf6, 0xbc, 0xdd, 0x11,
+0x71, 0x8f, 0xbb, 0xe2, 0x2c, 0xd6, 0xdd, 0xb3,
+0xb8, 0x3b, 0x4b, 0x5f, 0x66, 0xa2, 0x04, 0x92,
+0x92, 0x01, 0x39, 0x37, 0xba, 0xac, 0x35, 0x40,
+0x6e, 0x8d, 0x4a, 0x59, 0x11, 0x75, 0x8d, 0x82,
+0xbb, 0x4d, 0x0c, 0x3a, 0x60, 0xd4, 0xb9, 0x94,
+0x7b, 0x8b, 0x7f, 0x8e, 0x6d, 0xd8, 0xc0, 0x46,
+0x89, 0x3a, 0xcb, 0xa2, 0x06, 0x65, 0xcd, 0xbd,
+0xd7, 0x3d, 0xdd, 0xd3, 0x99, 0x9e, 0x04, 0x37,
+0x5a, 0xc5, 0x2f, 0xaf, 0x1f, 0x8f, 0xf7, 0xfb,
+0xcd, 0xef, 0xfd, 0x7e, 0x9f, 0xfe, 0xbe, 0x81,
+0x52, 0x29, 0x63, 0xfe, 0x07, 0xc0, 0xdc, 0x06,
+0xd2, 0x96, 0xcd, 0xff, 0x56, 0x1f, 0x5a, 0xfe,
+0xfd, 0xa5, 0xdf, 0x5f, 0x1a, 0xbc, 0xf3, 0xf6,
+0x8d, 0xb0, 0x01, 0x84, 0xba, 0x1f, 0x2d, 0x0f,
+0xdd, 0xf1, 0xe3, 0x1f, 0x2e, 0xad, 0xaf, 0x87,
+0xdb, 0xc9, 0x6f, 0xa1, 0xd0, 0xca, 0x25, 0xe4,
+0xff, 0xa5, 0x37, 0xc0, 0x46, 0x28, 0x5d, 0x5a,
+0xd7, 0xb8, 0xfc, 0x86, 0xc6, 0xa5, 0x2b, 0xe1,
+0x0e, 0x60, 0x96, 0xf5, 0x4d, 0x91, 0x9f, 0x27,
+0x1f, 0xf9, 0xdb, 0x1f, 0x84, 0x00, 0x33, 0x00,
+0x50, 0x12, 0x62, 0xa2, 0xf4, 0x4f, 0x21, 0xc4,
+0x28, 0x0c, 0xe0, 0x96, 0xc5, 0x21, 0xd0, 0xe8,
+0xef, 0x90, 0x7d, 0x5e, 0x1a, 0x02, 0xc5, 0xf9,
+0x3b, 0x13, 0x02, 0x15, 0xda, 0x41, 0xed, 0x81,
+0x0a, 0x19, 0xae, 0xf8, 0xc3, 0xa8, 0x1c, 0xb6,
+0xec, 0x3f, 0x73, 0xfe, 0xd4, 0x09, 0x3c, 0xe3,
+0xb4, 0xdc, 0x4f, 0xcb, 0x85, 0xa4, 0x65, 0xa2,
+0xd0, 0xd7, 0x59, 0x1f, 0xec, 0xf5, 0xdf, 0xfd,
+0x5a, 0xeb, 0x7f, 0x66, 0xad, 0xff, 0xe7, 0xce,
+0x87, 0x8a, 0xaf, 0x31, 0x1d, 0x80, 0xb3, 0xf7,
+0x63, 0x86, 0x87, 0x03, 0x06, 0x43, 0x14, 0x64,
+0x28, 0xa6, 0x86, 0x42, 0x46, 0x10, 0x80, 0x69,
+0x18, 0xeb, 0x0f, 0x5b, 0xf3, 0x87, 0x8a, 0xbe,
+0x82, 0x29, 0xdc, 0xa2, 0x8a, 0x1a, 0x5b, 0x8f,
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+0x0e, 0x6b, 0xd6, 0x78, 0x01, 0x9a, 0xe1, 0x57,
+0xa9, 0xb1, 0x11, 0x5d, 0xe4, 0x23, 0xc6, 0xf9,
+0x70, 0xdc, 0x14, 0xf5, 0x10, 0x8b, 0xb7, 0x1e,
+0x1f, 0x4f, 0xb3, 0x74, 0x7c, 0x27, 0x1f, 0x85,
+0x1b, 0xd9, 0x80, 0x2e, 0xa2, 0x7f, 0x6a, 0x02,
+0x34, 0xb8, 0x5f, 0x64, 0xe6, 0xd2, 0xc8, 0x42,
+0x9e, 0x4f, 0x4f, 0x11, 0x0d, 0xce, 0x26, 0x9f,
+0x85, 0xa2, 0x06, 0xab, 0x86, 0x0f, 0x05, 0x45,
+0xca, 0xa6, 0x28, 0x9f, 0x1e, 0x7d, 0xa5, 0x44,
+0x67, 0xf3, 0x86, 0xc6, 0x7a, 0x41, 0x3e, 0x14,
+0xf4, 0x95, 0x3b, 0x6b, 0xb4, 0x31, 0xe0, 0xe4,
+0x73, 0x09, 0x69, 0x50, 0x27, 0xad, 0x18, 0x2e,
+0x21, 0x28, 0xbe, 0x30, 0x58, 0x98, 0xf3, 0x61,
+0x66, 0x54, 0x71, 0x7f, 0x17, 0x4b, 0x72, 0xb5,
+0x3f, 0x9b, 0x9c, 0x09, 0x83, 0xd1, 0x7f, 0x1b,
+0xe7, 0xfa, 0x23, 0x76, 0xae, 0xea, 0x47, 0xc9,
+0x61, 0x4b, 0x83, 0x64, 0x76, 0x8d, 0xf0, 0x44,
+0x66, 0x8d, 0xa9, 0xa4, 0x91, 0x62, 0x7d, 0x8c,
+0x7c, 0xd8, 0x36, 0x58, 0x28, 0x46, 0xa9, 0x99,
+0x19, 0x89, 0xd5, 0xfe, 0x6d, 0x34, 0x17, 0x33,
+0x62, 0x9c, 0xd9, 0x74, 0xea, 0x67, 0x1a, 0xc7,
+0x4c, 0xe4, 0x43, 0x25, 0xd7, 0x45, 0xa2, 0x97,
+0xed, 0x58, 0x3a, 0x87, 0xdb, 0x34, 0xdd, 0xc3,
+0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb,
+0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01,
+0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed,
+0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22,
+0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90,
+0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79,
+0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe,
+0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58,
+0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25,
+0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9,
+0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2,
+0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad,
+0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3,
+0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54,
+0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce,
+0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78,
+0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d,
+0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f,
+0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10,
+0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5,
+0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10,
+0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60,
+0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52,
+0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8,
+0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8,
+0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40,
+0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5,
+0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53,
+0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb,
+0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95,
+0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09,
+0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11,
+0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79,
+0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe,
+0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb,
+0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6,
+0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e,
+0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86,
+0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6,
+0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e,
+0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7,
+0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7,
+0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75,
+0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc,
+0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f,
+0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd,
+0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a,
+0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f,
+0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81,
+0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a,
+0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f,
+0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41,
+0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55,
+0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4,
+0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4,
+0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff,
+0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c,
+0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7,
+0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31,
+0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96,
+0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37,
+0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0,
+0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d,
+0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5,
+0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e,
+0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba,
+0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91,
+0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4,
+0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef,
+0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73,
+0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78,
+0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf,
+0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62,
+0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4,
+0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a,
+0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
+0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0,
+0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
+0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa,
+0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf,
+0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84,
+0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98,
+0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c,
+0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00,
diff --git a/roms/u-boot/board/esd/plu405/plu405.c b/roms/u-boot/board/esd/plu405/plu405.c
new file mode 100644
index 00000000..03bf9c8f
--- /dev/null
+++ b/roms/u-boot/board/esd/plu405/plu405.c
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+#undef FPGA_DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to
+	 * 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	unsigned char *dst;
+	unsigned char fctr;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+		   (uchar *)fpgadata, &len) != 0) {
+		printf("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low "
+			       "after asserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high "
+			       "after deasserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high "
+			       "after programming FPGA)\n");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10);
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) &
+		 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Setup EEPROM write protection
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR,
+		 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)DUART0_BA + 4, 0x08);
+	out_8((void *)DUART1_BA + 4, 0x08);
+
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
+	/*
+	 * Init magnetic couplers
+	 */
+	if (!getenv("noinitcoupler")) {
+		init_coupler(CAN0_BA);
+		init_coupler(CAN1_BA);
+	}
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts("Board: ");
+
+	if (i == -1)
+		puts("### No HW ID - assuming PLU405");
+	else
+		puts(str);
+
+	putc('\n');
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) &
+			 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) |
+			 CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	       <state> -1: deliver current state
+ *			0: disable write
+ *			1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		      0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) &
+				 ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) |
+				 CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = ((in_be32((void*)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP) == 0);
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR,
+			       state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if (argv[1][0] == '0') {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    1);
+		}
+		if (state < 0)
+			puts("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/roms/u-boot/board/esd/pmc405/Makefile b/roms/u-boot/board/esd/pmc405/Makefile
new file mode 100644
index 00000000..ad98207f
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+obj-y	= pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
diff --git a/roms/u-boot/board/esd/pmc405/pmc405.c b/roms/u-boot/board/esd/pmc405/pmc405.c
new file mode 100644
index 00000000..e67ff309
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc405/pmc405.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005-2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+	/*
+	 * EBC Configuration Register:
+	 * set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000);
+
+	/*
+	 * Setup GPIO pins
+	 */
+	mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
+					CONFIG_SYS_FPGA_DONE |
+					CONFIG_SYS_XEREADY |
+					CONFIG_SYS_NONMONARCH |
+					CONFIG_SYS_REV1_2) << 5));
+
+	if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+		/* rev 1.2 boards */
+		mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
+						CONFIG_SYS_SELF_RST) << 5));
+	}
+
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
+	/* setup for output */
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
+		 CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
+
+	/*
+	 * - check if rev1_2 is low, then:
+	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
+	 *   in TCR to assert INTA# or SELFRST#
+	 */
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* deassert EREADY# */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
+	return (0);
+}
+
+ushort pmc405_pci_subsys_deviceid(void)
+{
+	ulong val;
+
+	val = in_be32((void *)GPIO0_IR);
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+		/* check monarch# signal */
+		if (val & CONFIG_SYS_NONMONARCH)
+			return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+		return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
+	}
+	return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	ulong val;
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1)
+		puts ("### No HW ID - assuming PMC405");
+	else
+		puts(str);
+
+	val = in_be32((void *)GPIO0_IR);
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+		puts(" rev1.2 (");
+		if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
+			puts("non-");
+		puts("monarch)");
+	} else
+		puts(" <=rev1.1");
+
+	putc ('\n');
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/pmc405de/Makefile b/roms/u-boot/board/esd/pmc405de/Makefile
new file mode 100644
index 00000000..b3f6dcd1
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc405de/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= pmc405de.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+obj-y += ../common/cmd_loadpci.o
diff --git a/roms/u-boot/board/esd/pmc405de/chip_config.c b/roms/u-boot/board/esd/pmc405de/chip_config.c
new file mode 100644
index 00000000..c06a6aeb
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc405de/chip_config.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"133",
+		"CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
+		}
+	},
+	{
+		"266",
+		"CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
+		}
+	},
+	{
+		"333",
+		"CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
+		{
+			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/roms/u-boot/board/esd/pmc405de/pmc405de.c b/roms/u-boot/board/esd/pmc405de/pmc405de.c
new file mode 100644
index 00000000..4409ea65
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc405de/pmc405de.c
@@ -0,0 +1,504 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pci.h>
+#include <command.h>
+#include <malloc.h>
+
+/*
+ * PMC405-DE cpld registers
+ * - all registers are 8 bit
+ * - all registers are on 32 bit addesses
+ */
+struct pmc405de_cpld {
+	/* cpld design version */
+	u8 version;
+	u8 reserved0[3];
+
+	/* misc. status lines */
+	u8 status;
+	u8 reserved1[3];
+
+	/*
+	 * gated control flags
+	 * gate bit(s) must be written with '1' to
+	 * access control flag
+	 */
+	u8 control;
+	u8 reserved2[3];
+};
+
+#define CPLD_VERSION_MASK		0x0f
+#define CPLD_CONTROL_POSTLED_N		0x01
+#define CPLD_CONTROL_POSTLED_GATE	0x02
+#define CPLD_CONTROL_RESETOUT_N		0x40
+#define CPLD_CONTROL_RESETOUT_N_GATE	0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+extern void pll_write(u32 a, u32 b);
+
+static int wait_for_pci_ready_done;
+
+static int is_monarch(void);
+static int pci_is_66mhz(void);
+static int board_revision(void);
+static int cpld_revision(void);
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
+
+int board_early_init_f(void)
+{
+	u32 pllmr0, pllmr1;
+
+	/*
+	 * check M66EN and patch PLB:PCI divider for 66MHz PCI
+	 *
+	 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
+	 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
+	 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
+	 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
+	 *
+	 * calling upd_plb_pci_div() may end in calling pll_write() which will
+	 * do a chip reset and never return.
+	 */
+	pllmr0 = mfdcr(CPC0_PLLMR0);
+	pllmr1 = mfdcr(CPC0_PLLMR1);
+
+	if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
+		/* fCPU=333MHz, fPLB=111MHz */
+		if (pci_is_66mhz())
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
+		else
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+	} else {
+		/* fCPU=133|266MHz, fPLB=133MHz */
+		if (pci_is_66mhz())
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+		else
+			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
+	}
+
+	/*
+	 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register:
+	 * - set ready timeout to 512 ebc-clks -> ca. 15 us
+	 * - EBC lines are always driven
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);
+
+	return 0;
+}
+
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
+{
+	if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
+		pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
+}
+
+int misc_init_r(void)
+{
+	int i;
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+	if (!is_monarch()) {
+		/* PCI configuration done: release EREADY */
+		setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
+		setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
+	}
+
+	/* turn off POST LED */
+	out_8(&cpld->control,
+	      CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
+
+	/* turn on LEDs: RUN, A, B */
+	clrbits_be32(&gpio0->or,
+		     CONFIG_SYS_GPIO_LEDRUN_N |
+		     CONFIG_SYS_GPIO_LEDA_N |
+		     CONFIG_SYS_GPIO_LEDB_N);
+
+	for (i=0; i < 200; i++)
+		udelay(1000);
+
+	/* turn off LEDs: A, B */
+	setbits_be32(&gpio0->or,
+		     CONFIG_SYS_GPIO_LEDA_N |
+		     CONFIG_SYS_GPIO_LEDB_N);
+
+	return (0);
+}
+
+static int is_monarch(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
+}
+
+static int pci_is_66mhz(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
+}
+
+static int board_revision(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
+		CONFIG_SYS_GPIO_HWREV_SHIFT);
+}
+
+static int cpld_revision(void)
+{
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+	return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	puts("Board: esd GmbH - PMC-CPU/405-DE");
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld, ", gd->board_type);
+
+	if (!is_monarch())
+		puts("non-");
+
+	printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
+	       pci_is_66mhz() ? "66" : "33", cpld_revision());
+
+	return 0;
+}
+
+
+static void wait_for_pci_ready(void)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	int i;
+	char *s = getenv("pcidelay");
+
+	/* only wait once */
+	if (wait_for_pci_ready_done)
+		return;
+
+	/*
+	 * We have our own handling of the pcidelay variable.
+	 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+	 * and adapter devices. For adapter devices we do not
+	 * want this.
+	 */
+	if (s) {
+		int ms = simple_strtoul(s, NULL, 10);
+		printf("PCI:   Waiting for %d ms\n", ms);
+		for (i=0; i<ms; i++)
+			udelay(1000);
+	}
+
+	if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
+		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
+		while (1) {
+			if (ctrlc()) {
+				puts("abort\n");
+				break;
+			}
+			if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
+				printf("done\n");
+				break;
+			}
+		}
+	}
+
+	wait_for_pci_ready_done = 1;
+}
+
+/*
+ * Overwrite weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	char *s;
+
+	if (!is_monarch()) {
+		/*
+		 * Overwrite PCI identification when running in
+		 * non-monarch mode
+		 * This should be moved into pci_target_init()
+		 * when it is sometimes available for 405 CPUs
+		 */
+		pci_write_config_word(PCIDEVID_405GP,
+				      PCI_SUBSYSTEM_ID,
+				      CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+		pci_write_config_word(PCIDEVID_405GP,
+				      PCI_CLASS_SUB_CODE,
+				      CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+	}
+
+	s = getenv("pciscan");
+	if (s == NULL) {
+		if (is_monarch()) {
+			wait_for_pci_ready();
+			return 1;
+		} else {
+			return 0;
+		}
+	} else {
+		if (!strcmp(s, "yes"))
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Overwrite weak pci_pre_init()
+ *
+ * The default implementation enables the 405EP
+ * internal PCI arbiter. We do not want that
+ * on a PMC module.
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in non-monarch mode.
+	 */
+	if (!is_monarch()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *                      0: disable write
+ *                      1: enable write
+ * Returns:            -1: wrong device address
+ *                      0: dis-/en- able done
+ *                    0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32(&gpio0->or) &
+				       CONFIG_SYS_GPIO_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR,
+				state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(
+				CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(
+				CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0)
+			puts ("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 pram, nextbase, base;
+	char *v;
+	u32 param;
+	ulong *lptr;
+
+	v = getenv("pram");
+	if (v)
+		pram = simple_strtoul(v, NULL, 10);
+	else {
+		printf("Error: pram undefined. Please define pram in KiB\n");
+		return 1;
+	}
+
+	base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+	/*
+	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
+	 */
+	param = base - (pram << 10);
+	printf("PARAM: @%08x\n", param);
+	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
+
+	/* clear entire PA ram */
+	memset((void*)param, 0, (pram << 10));
+
+	/* reserve 4k for pointer field */
+	nextbase = base - 4096;
+	lptr = (ulong*)(base);
+
+	/*
+	 * *(--lptr) = item_size;
+	 * *(--lptr) = base - item_base = distance from field top;
+	 */
+
+	/* env is first (4k aligned) */
+	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+	memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
+	*(--lptr) = base - nextbase;  /* offset | type=0 */
+
+	/* free section */
+	*(--lptr) = nextbase - param; /* size */
+	*(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+	/* terminate pointer field */
+	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+	*(--lptr) = 0;                /* offset=0 -> terminator */
+	return 0;
+}
+U_BOOT_CMD(
+	painit,	1,	1,	do_painit,
+	"prepare PciAccess system",
+	""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+	setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
+	return 0;
+}
+U_BOOT_CMD(
+	selfreset,	1,	1,	do_selfreset,
+	"assert self-reset# signal",
+	""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct pmc405de_cpld *cpld =
+		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("PMC-RESETOUT# asserted\n");
+			out_8(&cpld->control,
+			      CPLD_CONTROL_RESETOUT_N_GATE);
+		} else {
+			/* deassert */
+			printf("PMC-RESETOUT# deasserted\n");
+			out_8(&cpld->control,
+			      CPLD_CONTROL_RESETOUT_N |
+			      CPLD_CONTROL_RESETOUT_N_GATE);
+		}
+	} else {
+		printf("PMC-RESETOUT# is %s\n",
+		       (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
+		       "inactive" : "active");
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	resetout,	2,	1,	do_resetout,
+	"assert PMC-RESETOUT# signal",
+	""
+);
diff --git a/roms/u-boot/board/esd/pmc440/Makefile b/roms/u-boot/board/esd/pmc440/Makefile
new file mode 100644
index 00000000..708e9d13
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= pmc440.o cmd_pmc440.o sdram.o fpga.o \
+	../common/cmd_loadpci.o
+extra-y	+= init.o
diff --git a/roms/u-boot/board/esd/pmc440/cmd_pmc440.c b/roms/u-boot/board/esd/pmc440/cmd_pmc440.c
new file mode 100644
index 00000000..3481e464
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/cmd_pmc440.c
@@ -0,0 +1,553 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
+
+#include "pmc440.h"
+
+int is_monarch(void);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt);
+int eeprom_write_enable(unsigned dev_addr, int state);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_BSP)
+
+static int got_fifoirq;
+static int got_hcirq;
+
+int fpga_interrupt(u32 arg)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
+	int rc = -1; /* not for us */
+	u32 status = FPGA_IN32(&fpga->status);
+
+	/* check for interrupt from fifo module */
+	if (status & STATUS_FIFO_ISF) {
+		/* disable this int source */
+		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+		rc = 0;
+		got_fifoirq = 1; /* trigger backend */
+	}
+
+	if (status & STATUS_HOST_ISF) {
+		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+		rc = 0;
+		got_hcirq = 1;
+	}
+
+	return rc;
+}
+
+int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	got_hcirq = 0;
+
+	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+
+	irq_install_handler(IRQ0_FPGA,
+			    (interrupt_handler_t *)fpga_interrupt,
+			    fpga);
+
+	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
+
+	while (!got_hcirq) {
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			break;
+		}
+	}
+	if (got_hcirq)
+		printf("Got interrupt!\n");
+
+	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+	irq_free_handler(IRQ0_FPGA);
+	return 0;
+}
+U_BOOT_CMD(
+	waithci,	1,	1,	do_waithci,
+	"Wait for host control interrupt",
+	""
+);
+
+void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
+{
+	u32 ctrl;
+
+	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
+		printf("%5d  %d    %3d  %08x",
+		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+		       FPGA_IN32(&fpga->fifo[f].data));
+		if (ctrl & FIFO_OVERFLOW) {
+			printf(" OVERFLOW\n");
+			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
+		} else
+			printf("\n");
+	}
+}
+
+int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	int i;
+	int n = 0;
+	u32 ctrl, data, f;
+	char str[] = "\\|/-";
+	int abort = 0;
+	int count = 0;
+	int count2 = 0;
+
+	switch (argc) {
+	case 1:
+		/* print all fifos status information */
+		printf("fifo level status\n");
+		printf("______________________________\n");
+		for (i=0; i<FIFO_COUNT; i++) {
+			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
+			printf(" %d    %3d  %s%s%s %s\n",
+			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+			       ctrl & FIFO_FULL ? "FULL     " : "",
+			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
+			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
+			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
+		}
+		break;
+
+	case 2:
+		/* completely read out fifo 'n' */
+		if (!strcmp(argv[1],"read")) {
+			printf("  #   fifo level data\n");
+			printf("______________________________\n");
+
+			for (i=0; i<FIFO_COUNT; i++)
+				dump_fifo(fpga, i, &n);
+
+		} else if (!strcmp(argv[1],"wait")) {
+			got_fifoirq = 0;
+
+			irq_install_handler(IRQ0_FPGA,
+					    (interrupt_handler_t *)fpga_interrupt,
+					    fpga);
+
+			printf("  #   fifo level data\n");
+			printf("______________________________\n");
+
+			/* enable all fifo interrupts */
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+			for (i=0; i<FIFO_COUNT; i++) {
+				/* enable interrupts from all fifos */
+				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+			}
+
+			while (1) {
+				/* wait loop */
+				while (!got_fifoirq) {
+					count++;
+					if (!(count % 100)) {
+						count2++;
+						putc(0x08); /* backspace */
+						putc(str[count2 % 4]);
+					}
+
+					/* Abort if ctrl-c was pressed */
+					if ((abort = ctrlc())) {
+						puts("\nAbort\n");
+						break;
+					}
+					udelay(1000);
+				}
+				if (abort)
+					break;
+
+				/* simple fifo backend */
+				if (got_fifoirq) {
+					for (i=0; i<FIFO_COUNT; i++)
+						dump_fifo(fpga, i, &n);
+
+					got_fifoirq = 0;
+					/* unmask global fifo irq */
+					FPGA_OUT32(&fpga->hostctrl,
+						   HOSTCTRL_FIFOIE_GATE |
+						   HOSTCTRL_FIFOIE_FLAG);
+				}
+			}
+
+			/* disable all fifo interrupts */
+			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+			for (i=0; i<FIFO_COUNT; i++)
+				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+
+			irq_free_handler(IRQ0_FPGA);
+
+		} else {
+			printf("Usage:\nfifo %s\n", cmdtp->help);
+			return 1;
+		}
+		break;
+
+	case 4:
+	case 5:
+		if (!strcmp(argv[1],"write")) {
+			/* get fifo number or fifo address */
+			f = simple_strtoul(argv[2], NULL, 16);
+
+			/* data paramter */
+			data = simple_strtoul(argv[3], NULL, 16);
+
+			/* get optional count parameter */
+			n = 1;
+			if (argc >= 5)
+				n = (int)simple_strtoul(argv[4], NULL, 10);
+
+			if (f < FIFO_COUNT) {
+				printf("writing %d x %08x to fifo %d\n",
+				       n, data, f);
+				for (i=0; i<n; i++)
+					FPGA_OUT32(&fpga->fifo[f].data, data);
+			} else {
+				printf("writing %d x %08x to fifo port at "
+				       "address %08x\n",
+				       n, data, f);
+				for (i=0; i<n; i++)
+					out_be32((void *)f, data);
+			}
+		} else {
+			printf("Usage:\nfifo %s\n", cmdtp->help);
+			return 1;
+		}
+		break;
+
+	default:
+		printf("Usage:\nfifo %s\n", cmdtp->help);
+		return 1;
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	fifo,	5,	1,	do_fifo,
+	"Fifo module operations",
+	"wait\nfifo read\n"
+	"fifo write fifo(0..3) data [cnt=1]\n"
+	"fifo write address(>=4) data [cnt=1]\n"
+	"  - without arguments: print all fifo's status\n"
+	"  - with 'wait' argument: interrupt driven read from all fifos\n"
+	"  - with 'read' argument: read current contents from all fifos\n"
+	"  - with 'write' argument: write 'data' 'cnt' times to "
+	"'fifo' or 'address'"
+);
+
+int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong sdsdp[5];
+	ulong delay;
+	int count=16;
+
+	if (argc < 2) {
+		printf("Usage:\nsbe %s\n", cmdtp->help);
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (!strcmp(argv[1], "400")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 400MHz\n");
+			sdsdp[0]=0x8678624e;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else if (!strcmp(argv[1], "533")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 533MHz\n");
+			sdsdp[0]=0x87788252;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else if (!strcmp(argv[1], "667")) {
+			/* PLB=133MHz, PLB/PCI=3 */
+			printf("Bootstrapping for 667MHz\n");
+			sdsdp[0]=0x8778a256;
+			sdsdp[1]=0x095fa030;
+			sdsdp[2]=0x40082350;
+			sdsdp[3]=0x0d050000;
+		} else {
+			printf("Usage:\nsbe %s\n", cmdtp->help);
+			return -1;
+		}
+	}
+
+	if (argc > 2) {
+		sdsdp[4] = 0;
+		if (argv[2][0]=='1')
+			sdsdp[4]=0x19750100;
+		else if (argv[2][0]=='0')
+			sdsdp[4]=0x19750000;
+		if (sdsdp[4])
+			count += 4;
+	}
+
+	if (argc > 3) {
+		delay = simple_strtoul(argv[3], NULL, 10);
+		if (delay > 20)
+			delay = 20;
+		sdsdp[4] |= delay;
+	}
+
+	printf("Writing boot EEPROM ...\n");
+	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+				   0, (uchar*)sdsdp, count) != 0)
+		printf("bootstrap_eeprom_write failed\n");
+	else
+		printf("done (dump via 'i2c md 52 0.1 14')\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	sbe, 4, 0, do_setup_bootstrap_eeprom,
+	"setup bootstrap eeprom",
+	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
+);
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+#include <search.h>
+#include <errno.h>
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 pram, nextbase, base;
+	char *v;
+	u32 param;
+	ulong *lptr;
+
+	env_t *envp;
+	char *res;
+	int len;
+
+	v = getenv("pram");
+	if (v)
+		pram = simple_strtoul(v, NULL, 10);
+	else {
+		printf("Error: pram undefined. Please define pram in KiB\n");
+		return 1;
+	}
+
+	base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+	/*
+	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+	 */
+	param = base - (pram << 10);
+	printf("PARAM: @%08x\n", param);
+	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
+
+	/* clear entire PA ram */
+	memset((void*)param, 0, (pram << 10));
+
+	/* reserve 4k for pointer field */
+	nextbase = base - 4096;
+	lptr = (ulong*)(base);
+
+	/*
+	 * *(--lptr) = item_size;
+	 * *(--lptr) = base - item_base = distance from field top;
+	 */
+
+	/* env is first (4k aligned) */
+	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+	envp = (env_t *)nextbase;
+	res = (char *)envp->data;
+	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
+	if (len < 0) {
+		error("Cannot export environment: errno = %d\n", errno);
+		return 1;
+	}
+	envp->crc = crc32(0, envp->data, ENV_SIZE);
+
+	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
+	*(--lptr) = base - nextbase;  /* offset | type=0 */
+
+	/* free section */
+	*(--lptr) = nextbase - param; /* size */
+	*(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+	/* terminate pointer field */
+	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+	*(--lptr) = 0;                /* offset=0 -> terminator */
+	return 0;
+}
+U_BOOT_CMD(
+	painit,	1,	1,	do_painit,
+	"prepare PciAccess system",
+	""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	in_be32((void*)CONFIG_SYS_RESET_BASE);
+	return 0;
+}
+U_BOOT_CMD(
+	selfreset,	1,	1,	do_selfreset,
+	"assert self-reset# signal",
+	""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	/* requiers bootet FPGA and PLD_IOEN_N active */
+	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
+		printf("Error: resetout requires a bootet FPGA\n");
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("PMC-RESETOUT# asserted\n");
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_PMCRSTOUT_GATE);
+		} else {
+			/* deassert */
+			printf("PMC-RESETOUT# deasserted\n");
+			FPGA_OUT32(&fpga->hostctrl,
+				   HOSTCTRL_PMCRSTOUT_GATE |
+				   HOSTCTRL_PMCRSTOUT_FLAG);
+		}
+	} else {
+		printf("PMC-RESETOUT# is %s\n",
+		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
+		       "inactive" : "active");
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	resetout,	2,	1,	do_resetout,
+	"assert PMC-RESETOUT# signal",
+	""
+);
+
+int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (is_monarch()) {
+		printf("This command is only supported in non-monarch mode\n");
+		return -1;
+	}
+
+	if (argc > 1) {
+		if (argv[1][0] == '0') {
+			/* assert */
+			printf("inta# asserted\n");
+			out_be32((void*)GPIO1_TCR,
+				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
+		} else {
+			/* deassert */
+			printf("inta# deasserted\n");
+			out_be32((void*)GPIO1_TCR,
+				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
+		}
+	} else {
+		printf("inta# is %s\n",
+		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
+		       "active" : "inactive");
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	inta,	2,	1,	do_inta,
+	"Assert/Deassert or query INTA# state in non-monarch mode",
+	""
+);
+
+/* test-only */
+int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong pciaddr;
+
+	if (argc > 1) {
+		pciaddr = simple_strtoul(argv[1], NULL, 16);
+
+		pciaddr &= 0xf0000000;
+
+		/* map PCI address at 0xc0000000 in PLB space */
+
+		/* PMM1 Mask/Attribute - disabled b4 setting */
+		out32r(PCIL0_PMM1MA, 0x00000000);
+		/* PMM1 Local Address */
+		out32r(PCIL0_PMM1LA, 0xc0000000);
+		/* PMM1 PCI Low Address */
+		out32r(PCIL0_PMM1PCILA, pciaddr);
+		/* PMM1 PCI High Address */
+		out32r(PCIL0_PMM1PCIHA, 0x00000000);
+		/* 256MB + No prefetching, and enable region */
+		out32r(PCIL0_PMM1MA, 0xf0000001);
+	} else {
+		printf("Usage:\npmm %s\n", cmdtp->help);
+	}
+	return 0;
+}
+U_BOOT_CMD(
+	pmm,	2,	1,	do_pmm,
+	"Setup pmm[1] registers",
+	"<pciaddr> (pciaddr will be aligned to 256MB)"
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#endif /* CONFIG_CMD_BSP */
diff --git a/roms/u-boot/board/esd/pmc440/config.mk b/roms/u-boot/board/esd/pmc440/config.mk
new file mode 100644
index 00000000..9cb071e4
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/roms/u-boot/board/esd/pmc440/fpga.c b/roms/u-boot/board/esd/pmc440/fpga.c
new file mode 100644
index 00000000..f876da85
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/fpga.c
@@ -0,0 +1,446 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spartan2.h>
+#include <spartan3.h>
+#include <command.h>
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#define USE_SP_CODE
+
+#ifdef USE_SP_CODE
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	NULL, /* err */
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	NULL, /* rdata */
+	fpga_wdata_fn,
+	fpga_busy_fn,
+	fpga_abort_fn,
+	fpga_post_config_fn,
+};
+#else
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_post_config_fn,
+};
+#endif
+
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
+	ngcc_fpga_pre_config_fn,
+	ngcc_fpga_pgm_fn,
+	ngcc_fpga_clk_fn,
+	ngcc_fpga_init_fn,
+	ngcc_fpga_done_fn,
+	ngcc_fpga_wr_fn,
+	ngcc_fpga_post_config_fn
+};
+
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	XILINX_XC3S1200E_DESC(
+#ifdef USE_SP_CODE
+		slave_parallel,
+#else
+		slave_serial,
+#endif
+		(void *)&pmc440_fpga_fns,
+		0),
+	XILINX_XC2S200_DESC(
+		slave_serial,
+		(void *)&ngcc_fpga_fns,
+		0)
+};
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset(int assert)
+{
+	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	if (assert) {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+		debug("asserted\n");
+	} else {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+		debug("deasserted\n");
+	}
+}
+
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
+	      __LINE__);
+	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	debug("%s:%d: FPGA PROGRAM ",
+	      __FUNCTION__, __LINE__);
+
+	if (assert) {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
+		debug("asserted\n");
+	} else {
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
+		debug("deasserted\n");
+	}
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
+		return 0;
+	else
+		return 1;
+}
+
+#ifdef USE_SP_CODE
+int fpga_abort_fn(int cookie)
+{
+	return 0;
+}
+
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+	return assert_cs;
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+	return 1;
+}
+#endif
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
+		return 1;
+	else
+		return 0;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn(int cookie)
+{
+	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset(true);
+
+	/* release init# */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
+	/* disable PLD IOs */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	int rc=0;
+	char *s;
+
+	debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+	/* enable PLD0..7 pins */
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
+
+	fpga_reset(true);
+	udelay (100);
+	fpga_reset(false);
+	udelay (100);
+
+	FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
+
+	/* NGCC/CANDES only: enable ledlink */
+	if ((s = getenv("bd_type")) &&
+	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
+		FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+	return rc;
+}
+
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	if (assert_clk)
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
+	else
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
+
+	return assert_clk;
+}
+
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	if (assert_write)
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+	else
+		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+
+	return assert_write;
+}
+
+#ifdef USE_SP_CODE
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+	uchar val = data;
+	ulong or = in_be32((void*)GPIO1_OR);
+	int i = 7;
+	do {
+		/* Write data */
+		if (val & 0x80)
+			or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+		else
+			or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+		out_be32((void*)GPIO1_OR, or);
+
+		/* Assert the clock */
+		or |= GPIO1_FPGA_CLK;
+		out_be32((void*)GPIO1_OR, or);
+		val <<= 1;
+		i --;
+	} while (i > 0);
+
+	/* Write last data bit (the 8th clock comes from the sp_load() code */
+	if (val & 0x80)
+		or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+	else
+		or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+	out_be32((void*)GPIO1_OR, or);
+
+	return 0;
+}
+#endif
+
+#define NGCC_FPGA_PRG  CLOCK_EN
+#define NGCC_FPGA_DATA RESET_OUT
+#define NGCC_FPGA_DONE CLOCK_IN
+#define NGCC_FPGA_INIT IRIGB_R_IN
+#define NGCC_FPGA_CLK  CLOCK_OUT
+
+void ngcc_fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n",
+	      __FUNCTION__, __LINE__);
+
+	/* make sure program pin is inactive */
+	ngcc_fpga_pgm_fn(false, false, 0);
+}
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void ngcc_fpga_reset(int assert)
+{
+	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+		debug("asserted\n");
+	} else {
+		FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+		debug("deasserted\n");
+	}
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+		debug("asserted\n");
+	} else {
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+		debug("deasserted\n");
+	}
+
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int ngcc_fpga_init_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
+		debug("high\n");
+		return 0;
+	} else {
+		debug("low\n");
+		return 1;
+	}
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int ngcc_fpga_done_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
+		debug("DONE high\n");
+		return 1;
+	} else {
+		debug("low\n");
+		return 0;
+	}
+}
+
+
+/*
+ * FPGA pre-configuration function.
+ */
+int ngcc_fpga_pre_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+
+	ngcc_fpga_reset(true);
+	FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
+
+	ngcc_fpga_reset(true);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int ngcc_fpga_post_config_fn(int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+	udelay (100);
+	ngcc_fpga_reset(false);
+
+	FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+	return 0;
+}
+
+
+int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	if (assert_clk)
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+	else
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+
+	return assert_clk;
+}
+
+
+int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+	if (assert_write)
+		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+	else
+		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+
+	return assert_write;
+}
+
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int pmc440_init_fpga(void)
+{
+	char *s;
+
+	debug("%s:%d: Initialize FPGA interface\n",
+	      __FUNCTION__, __LINE__);
+	fpga_init();
+
+	fpga_serialslave_init ();
+	debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
+	fpga_add (fpga_xilinx, &fpga[0]);
+
+	/* NGCC only */
+	if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
+		ngcc_fpga_serialslave_init ();
+		debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
+		fpga_add (fpga_xilinx, &fpga[1]);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FPGA */
diff --git a/roms/u-boot/board/esd/pmc440/fpga.h b/roms/u-boot/board/esd/pmc440/fpga.h
new file mode 100644
index 00000000..3810788a
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/fpga.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+extern int pmc440_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_wdata_fn (uchar data, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
+
+extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int ngcc_fpga_init_fn(int cookie);
+extern int ngcc_fpga_done_fn(int cookie);
+extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int ngcc_fpga_pre_config_fn(int cookie );
+extern int ngcc_fpga_post_config_fn(int cookie );
diff --git a/roms/u-boot/board/esd/pmc440/init.S b/roms/u-boot/board/esd/pmc440/init.S
new file mode 100644
index 00000000..1f26fad1
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/init.S
@@ -0,0 +1,69 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ */
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+	/* TLB entries for DDR2 SDRAM are generated dynamically */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+	/* TLB-entries for EBC */
+	/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
+	 * tlb entry.
+	 * This dummy entry is only for convinience in order not to modify the
+	 * amount of entries. Currently OS/9 relies on this :-)
+	 */
+	tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for NAND */
+	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+	/* TLB-entry PCI IO space */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
+
+	/* TODO:  what about high IO space */
+	tlbtab_end
diff --git a/roms/u-boot/board/esd/pmc440/pmc440.c b/roms/u-boot/board/esd/pmc440/pmc440.c
new file mode 100644
index 00000000..062ae672
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/pmc440.c
@@ -0,0 +1,903 @@
+/*
+ * (Cg) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on board/amcc/sequoia/sequoia.c
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#ifdef CONFIG_RESET_PHY_R
+#include <miiphy.h>
+#endif
+#include <serial.h>
+#include <asm/4xx_pci.h>
+#include <usb.h>
+
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+ulong flash_get_size(ulong base, int banknum);
+static int pci_is_66mhz(void);
+int is_monarch(void);
+static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+				 uchar *buffer, unsigned cnt);
+
+struct serial_device *default_serial_console(void)
+{
+	uchar buf[4];
+	ulong delay;
+	int i;
+	ulong val;
+
+	/*
+	 * Use default console on P4 when strapping jumper
+	 * is installed (bootstrap option != 'H').
+	 */
+	mfsdr(SDR0_PINSTP, val);
+	if (((val & 0xf0000000) >> 29) != 7)
+		return &eserial2_device;
+
+	ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
+	if (!(scratchreg & 0x80)) {
+		/* mark scratchreg valid */
+		scratchreg = (scratchreg & 0xffffff00) | 0x80;
+
+		i2c_init_all();
+
+		i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+					  0x10, buf, 4);
+		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
+			scratchreg |= buf[2];
+
+			/* bringup delay for console */
+			for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
+				udelay(1000);
+		} else
+			scratchreg |= 0x01;
+		out_be32((void *)GPIO0_ISR3L, scratchreg);
+	}
+
+	if (scratchreg & 0x01)
+		return &eserial2_device;
+	else
+		return &eserial1_device;
+}
+
+int board_early_init_f(void)
+{
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
+
+	/* general EBC configuration (disable EBC timeouts) */
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	mtdcr(EBC0_CFGDATA, 0xf8400000);
+
+	/* Setup the GPIO pins */
+	out_be32((void *)GPIO0_OR,    0x40000102);
+	out_be32((void *)GPIO0_TCR,   0x4c90011f);
+	out_be32((void *)GPIO0_OSRL,  0x28051400);
+	out_be32((void *)GPIO0_OSRH,  0x55005000);
+	out_be32((void *)GPIO0_TSRL,  0x08051400);
+	out_be32((void *)GPIO0_TSRH,  0x55005000);
+	out_be32((void *)GPIO0_ISR1L, 0x54000000);
+	out_be32((void *)GPIO0_ISR1H, 0x00000000);
+	out_be32((void *)GPIO0_ISR2L, 0x44000000);
+	out_be32((void *)GPIO0_ISR2H, 0x00000100);
+	out_be32((void *)GPIO0_ISR3L, 0x00000000);
+	out_be32((void *)GPIO0_ISR3H, 0x00000000);
+
+	out_be32((void *)GPIO1_OR,    0x80002408);
+	out_be32((void *)GPIO1_TCR,   0xd6003c08);
+	out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
+	out_be32((void *)GPIO1_OSRH,  0x00000000);
+	out_be32((void *)GPIO1_TSRL,  0x00000000);
+	out_be32((void *)GPIO1_TSRH,  0x00000000);
+	out_be32((void *)GPIO1_ISR1L, 0x00005555);
+	out_be32((void *)GPIO1_ISR1H, 0x40000000);
+	out_be32((void *)GPIO1_ISR2L, 0x04010000);
+	out_be32((void *)GPIO1_ISR2H, 0x00000000);
+	out_be32((void *)GPIO1_ISR3L, 0x01400000);
+	out_be32((void *)GPIO1_ISR3H, 0x00000000);
+
+	/* patch PLB:PCI divider for 66MHz PCI */
+	mfcpr(CPR0_SPCID, reg);
+	if (pci_is_66mhz() && (reg != 0x02000000)) {
+		mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
+
+		mfcpr(CPR0_ICFG, reg);
+		reg |= CPR0_ICFG_RLI_MASK;
+		mtcpr(CPR0_ICFG, reg);
+
+		mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
+	}
+
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xfffff7ef);
+	mtdcr(UIC0TR, 0x00000000);
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffc7f5);
+	mtdcr(UIC1TR, 0x00000000);
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0x27ffffff);
+	mtdcr(UIC2TR, 0x00000000);
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+		SDR0_PFC1_SELECT_CONFIG_4;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+		SDR0_PFC2_SELECT_CONFIG_4;
+
+	/* enable 2nd IIC */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+	mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_F)
+int misc_init_f(void)
+{
+	struct pci_controller hose;
+	hose.first_busno = 0;
+	hose.last_busno = 0;
+	hose.region_count = 0;
+
+	if (getenv("pciearly") && (!is_monarch())) {
+		printf("PCI:   early target init\n");
+		pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
+		pci_target_init(&hose);
+	}
+	return 0;
+}
+#endif
+
+/*
+ * misc_init_r.
+ */
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	u32 reg;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
+	char *act = getenv("usbact");
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_ENV_ADDR_REDUND,
+			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+
+	/*
+	 * USB suff...
+	 */
+	if ((act == NULL || strcmp(act, "host") == 0) &&
+	    !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+		/* SDR Setting */
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+		/*
+		 * An 8-bit/60MHz interface is the only possible alternative
+		 * when connecting the Device to the PHY
+		 */
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/*
+		 * Take USB out of reset:
+		 * -Initial status = all cores are in reset
+		 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+		 * -wait 1 ms
+		 * -deassert reset to PHY
+		 * -wait 1 ms
+		 * -deassert  reset to HOST
+		 * -wait 4 ms
+		 * -deassert all other resets
+		 */
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |	\
+				SDR0_SRST1_P4OPB0 |	\
+				SDR0_SRST1_OPBA2 |	\
+				SDR0_SRST1_PLB42OPB1 |	\
+				SDR0_SRST1_OPB2PLB40);
+		mtsdr(SDR0_SRST1, sdr0_srst1);
+		udelay(1000);
+
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+		mtsdr(SDR0_SRST1, sdr0_srst1);
+		udelay(1000);
+
+		mfsdr(SDR0_SRST0, sdr0_srst0);
+		sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+		mtsdr(SDR0_SRST0, sdr0_srst0);
+		udelay(4000);
+
+		/* finally all the other resets */
+		mtsdr(SDR0_SRST1, 0x00000000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+			/* enable power on USB socket */
+			out_be32((void *)GPIO1_OR,
+				 in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+		}
+
+		printf("USB:   Host\n");
+
+	} else if ((strcmp(act, "dev") == 0) ||
+		   (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+
+		/* SDR Setting */
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB2D0CR, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2D0CR, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/*clear resets*/
+		udelay(1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay(1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device\n");
+	}
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
+
+#ifdef CONFIG_FPGA
+	pmc440_init_fpga();
+#endif
+
+	/* turn off POST LED */
+	out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
+	/* turn on RUN LED */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
+	return 0;
+}
+
+int is_monarch(void)
+{
+	if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
+		return 0;
+
+	return 1;
+}
+
+static int pci_is_66mhz(void)
+{
+	if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
+		return 1;
+	return 0;
+}
+
+static int board_revision(void)
+{
+	return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd GmbH - PMC440");
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld, ", gd->board_type);
+
+	if (!is_monarch()) {
+		puts("non-");
+	}
+
+	printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
+	return (0);
+}
+
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices. Some OSs rely on this.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+				   int_line[PCI_DEV(dev) & 0x03]);
+}
+#endif
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	char *ptmla_str, *ptmms_str;
+
+	/*
+	 * Set up Direct MMIO registers
+	 */
+	/*
+	 * PowerPC440EPX PCI Master configuration.
+	 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	 * PLB address 0x80000000-0xBFFFFFFF
+	 *     ==> PCI address 0x80000000-0xBFFFFFFF
+	 * Use byte reversed out routines to handle endianess.
+	 * Make this region non-prefetchable.
+	 */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+						/* - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
+						/* and enable region */
+
+	if (!is_monarch()) {
+		ptmla_str = getenv("ptm1la");
+		ptmms_str = getenv("ptm1ms");
+		if(NULL != ptmla_str && NULL != ptmms_str ) {
+			out32r(PCIL0_PTM1MS,
+			       simple_strtoul(ptmms_str, NULL, 16));
+			out32r(PCIL0_PTM1LA,
+			       simple_strtoul(ptmla_str, NULL, 16));
+		} else {
+			/* BAR1: default top 64MB of RAM */
+			out32r(PCIL0_PTM1MS, 0xfc000001);
+			out32r(PCIL0_PTM1LA, 0x0c000000);
+		}
+	} else {
+		/* BAR1: default: complete 256MB RAM */
+		out32r(PCIL0_PTM1MS, 0xf0000001);
+		out32r(PCIL0_PTM1LA, 0x00000000);
+	}
+
+	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
+	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
+	if(NULL != ptmla_str && NULL != ptmms_str ) {
+		out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+		out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+	} else {
+		/* BAR2: default: 4MB FPGA */
+		out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+		out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+	}
+
+	if (is_monarch()) {
+		/* BAR2: map FPGA registers behind system memory at 1GB */
+		pci_hose_write_config_dword(hose, 0,
+					    PCI_BASE_ADDRESS_2, 0x40000008);
+	}
+
+	/*
+	 * Set up Configuration registers
+	 */
+
+	/* Program the board's vendor id */
+	pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
+				   CONFIG_SYS_PCI_SUBSYS_VENDORID);
+
+	/* disabled for PMC405 backward compatibility */
+	/* Configure command register as bus master */
+	/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
+
+
+	/* 240nS PCI clock */
+	pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
+
+	if (!is_monarch()) {
+		/* Program the board's subsystem id/classcode */
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+
+		/* PCI configuration done: release ERREADY */
+		out_be32((void *)GPIO1_OR,
+			 in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
+		out_be32((void *)GPIO1_TCR,
+			 in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
+	} else {
+		/* Program the board's subsystem id/classcode */
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_MONARCH);
+	}
+
+	/* enable host configuration */
+	pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+/*
+ * Override weak default pci_master_init()
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	/*
+	 * Only configure the master in monach mode
+	 */
+	if (is_monarch())
+		__pci_master_init(hose);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
+
+static void wait_for_pci_ready(void)
+{
+	if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
+		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
+		while (1) {
+			if (ctrlc()) {
+				puts("abort\n");
+				break;
+			}
+			if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
+				printf("done\n");
+				break;
+			}
+		}
+	}
+}
+
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	char *s = getenv("pciscan");
+	if (s == NULL)
+		if (is_monarch()) {
+			wait_for_pci_ready();
+			return 1;
+		} else
+			return 0;
+	else if (!strcmp(s, "yes"))
+		return 1;
+
+	return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_RESET_PHY_R
+static int pmc440_setup_vsc8601(char *devname, int phy_addr,
+				unsigned short behavior, unsigned short method)
+{
+	/* adjust LED behavior */
+	if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
+		printf("Phy%d: register write access failed\n", phy_addr);
+		return -1;
+	}
+
+	miiphy_write(devname, phy_addr, 0x11, 0x0010);
+	miiphy_write(devname, phy_addr, 0x11, behavior);
+	miiphy_write(devname, phy_addr, 0x10, method);
+	miiphy_write(devname, phy_addr, 0x1f, 0x0000);
+
+	return 0;
+}
+
+static int pmc440_setup_ksz9031(char *devname, int phy_addr)
+{
+	unsigned short id1, id2;
+
+	if (miiphy_read(devname, phy_addr, 2, &id1) ||
+	    miiphy_read(devname, phy_addr, 3, &id2)) {
+		printf("Phy%d: cannot read id\n", phy_addr);
+		return -1;
+	}
+
+	if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
+		printf("Phy%d: unexpected id\n", phy_addr);
+		return -1;
+	}
+
+	/* MMD 2.08: adjust tx_clk pad skew */
+	miiphy_write(devname, phy_addr, 0x0d, 2);
+	miiphy_write(devname, phy_addr, 0x0e, 8);
+	miiphy_write(devname, phy_addr, 0x0d, 0x4002);
+	miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+	char *s;
+	unsigned short val_method, val_behavior;
+
+	if (gd->board_type < 4) {
+		/* special LED setup for NGCC/CANDES */
+		s = getenv("bd_type");
+		if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+			val_method   = 0x0e0a;
+			val_behavior = 0x0cf2;
+		} else {
+			/* PMC440 standard type */
+			val_method   = 0x0e10;
+			val_behavior = 0x0cf0;
+		}
+
+		/* boards up to rev. 1.3 use Vitesse VSC8601 phys */
+		pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
+				     val_method, val_behavior);
+		pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
+				     val_method, val_behavior);
+	} else {
+		/* rev. 1.4 uses a Micrel KSZ9031 */
+		pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+		pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
+	}
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ *  Input: <dev_addr> I2C address of EEPROM device to enable.
+ *         <state>    -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:          -1: wrong device address
+ *                     0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+			      in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out_be32((void *)GPIO0_OR,
+				 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)GPIO0_OR)
+				       & GPIO0_EP_EEP));
+			break;
+		}
+	}
+	return state;
+}
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+			   uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 1);
+#endif
+	/*
+	 * Write data until done or would cross a write page boundary.
+	 * We must write the address again when changing pages
+	 * because the address counter only increments within a page.
+	 */
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+		maxlen = BOOT_EEPROM_PAGE_SIZE -
+			BOOT_EEPROM_PAGE_OFFSET(blk_off);
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+
+		buffer += len;
+		offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+	}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	eeprom_write_enable(dev_addr, 0);
+#endif
+	return rcode;
+}
+
+static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+				 uchar *buffer, unsigned cnt)
+{
+	unsigned end = offset + cnt;
+	unsigned blk_off;
+	int rcode = 0;
+
+	/*
+	 * Read data until done or would cross a page boundary.
+	 * We must write the address again when changing pages
+	 * because the next page may be in a different device.
+	 */
+	while (offset < end) {
+		unsigned alen, len;
+		unsigned maxlen;
+		uchar addr[2];
+
+		blk_off = offset & 0xFF;	/* block offset */
+
+		addr[0] = offset >> 8;		/* block number */
+		addr[1] = blk_off;		/* block offset */
+		alen	= 2;
+
+		addr[0] |= dev_addr;		/* insert device address */
+
+		len = end - offset;
+
+		maxlen = 0x100 - blk_off;
+		if (maxlen > I2C_RXTX_LEN)
+			maxlen = I2C_RXTX_LEN;
+		if (len > maxlen)
+			len = maxlen;
+
+		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+			rcode = 1;
+		buffer += len;
+		offset += len;
+	}
+
+	return rcode;
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	char *act = getenv("usbact");
+	int i;
+
+	if ((act == NULL || strcmp(act, "host") == 0) &&
+	    !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
+		/* enable power on USB socket */
+		out_be32((void *)GPIO1_OR,
+			 in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+
+	for (i=0; i<1000; i++)
+		udelay(1000);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	/* disable power on USB socket */
+	out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return usb_board_stop();
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in non-monarch mode.
+	 */
+	if (!is_monarch()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, ");
+			printf("err=%s\n", fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/roms/u-boot/board/esd/pmc440/pmc440.h b/roms/u-boot/board/esd/pmc440/pmc440.h
new file mode 100644
index 00000000..84e0b1f4
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/pmc440.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PMC440_H__
+#define __PMC440_H__
+
+/*
+ * GPIOs
+ */
+#define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
+#define GPIO1_NONMONARCH          (0x80000000 >> (63-32)) /* GPIO63 I */
+#define GPIO1_PPC_EREADY          (0x80000000 >> (62-32)) /* GPIO62 I/O */
+#define GPIO1_M66EN               (0x80000000 >> (61-32)) /* GPIO61 I */
+#define GPIO1_POST_N              (0x80000000 >> (60-32)) /* GPIO60 O */
+#define GPIO1_IOEN_N              (0x80000000 >> (50-32)) /* GPIO50 O */
+#define GPIO1_HWID_MASK           (0xf0000000 >> (56-32)) /* GPIO56..59 I */
+
+#define GPIO1_USB_PWR_N           (0x80000000 >> (32-32)) /* GPIO32 I */
+#define GPIO0_LED_RUN_N           (0x80000000 >> 30)      /* GPIO30 O */
+#define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
+#define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
+#define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
+
+/*
+ * FPGA programming pin configuration
+ */
+#define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
+#define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
+#define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
+#define GPIO1_FPGA_DONE           (0x80000000 >> (55-32)) /* FPGA done pin (ppc input)     */
+#define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
+#define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
+
+/*
+ * FPGA interface
+ */
+#define FPGA_BA CONFIG_SYS_FPGA_BASE0
+#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
+#define FPGA_IN32(p) in_be32((void*)(p))
+#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
+#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
+
+struct pmc440_fifo_s {
+	u32 data;
+	u32 ctrl;
+};
+
+/* fifo ctrl register */
+#define FIFO_IE              (1 << 15)
+#define FIFO_OVERFLOW        (1 << 10)
+#define FIFO_EMPTY           (1 <<  9)
+#define FIFO_FULL            (1 <<  8)
+#define FIFO_LEVEL_MASK      0x000000ff
+
+#define FIFO_COUNT           4
+
+struct pmc440_fpga_s {
+	u32 ctrla;
+	u32 status;
+	u32 ctrlb;
+	u32 pad1[0x40 / sizeof(u32) - 3];
+	u32 irig_time;                  /* offset: 0x0040 */
+	u32 irig_tod;
+	u32 irig_cf;
+	u32 pad2;
+	u32 irig_rx_time;               /* offset: 0x0050 */
+	u32 pad3[3];
+	u32 hostctrl;                   /* offset: 0x0060 */
+	u32 pad4[0x20 / sizeof(u32) - 1];
+	struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
+};
+
+typedef struct pmc440_fpga_s pmc440_fpga_t;
+
+/* ctrl register */
+#define CTRL_HOST_IE         (1 <<  8)
+
+/* outputs */
+#define RESET_EN    (1 << 31)
+#define CLOCK_EN    (1 << 30)
+#define RESET_OUT   (1 << 19)
+#define CLOCK_OUT   (1 << 22)
+#define RESET_OUT   (1 << 19)
+#define IRIGB_R_OUT (1 << 14)
+
+/* status register */
+#define STATUS_VERSION_SHIFT 24
+#define STATUS_VERSION_MASK  0xff000000
+#define STATUS_HWREV_SHIFT   20
+#define STATUS_HWREV_MASK    0x00f00000
+
+#define STATUS_CAN_ISF       (1 << 11)
+#define STATUS_CSTM_ISF      (1 << 10)
+#define STATUS_FIFO_ISF      (1 <<  9)
+#define STATUS_HOST_ISF      (1 <<  8)
+
+/* inputs */
+#define RESET_IN    (1 << 0)
+#define CLOCK_IN    (1 << 1)
+#define IRIGB_R_IN  (1 << 5)
+
+/* hostctrl register */
+#define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
+#define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
+#define HOSTCTRL_CSTM1IE_GATE (1 <<  7)
+#define HOSTCTRL_CSTM1IW_FLAG (1 <<  6)
+#define HOSTCTRL_CSTM0IE_GATE (1 <<  5)
+#define HOSTCTRL_CSTM0IW_FLAG (1 <<  4)
+#define HOSTCTRL_FIFOIE_GATE (1 <<  3)
+#define HOSTCTRL_FIFOIE_FLAG (1 <<  2)
+#define HOSTCTRL_HCINT_GATE  (1 <<  1)
+#define HOSTCTRL_HCINT_FLAG  (1 <<  0)
+
+#define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_FPGARST_N    (1 <<  2)
+
+/*
+ * FPGA to PPC interrupt
+ */
+#define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */
+#define IRQ1_FPGA            (32+30) /* UIC1 - custom module */
+#define IRQ2_FPGA            (64+ 3) /* UIC2 - custom module / CAN */
+#define IRQ_ETH0             (64+ 4) /* UIC2 */
+#define IRQ_ETH1             (   27) /* UIC0 */
+#define IRQ_RTC              (64+ 0) /* UIC2 */
+#define IRQ_PCIA             (64+ 1) /* UIC2 */
+#define IRQ_PCIB             (32+18) /* UIC1 */
+#define IRQ_PCIC             (32+19) /* UIC1 */
+#define IRQ_PCID             (32+20) /* UIC1 */
+
+#endif /* __PMC440_H__ */
diff --git a/roms/u-boot/board/esd/pmc440/sdram.c b/roms/u-boot/board/esd/pmc440/sdram.c
new file mode 100644
index 00000000..e7f81158
--- /dev/null
+++ b/roms/u-boot/board/esd/pmc440/sdram.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
+ *
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc440.h>
+
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+struct sdram_conf_s {
+	ulong size;
+	int rows;
+	int banks;
+};
+
+struct sdram_conf_s sdram_conf[] = {
+	{(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
+	{(512 << 20),  13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
+	{(256 << 20),  13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
+};
+
+/*
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ */
+int initdram_by_rb(int rows, int banks)
+{
+	ulong speed = get_bus_freq(0);
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x0A020200);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0102C812);
+	mtsdram(DDR0_07, 0x000D0100);
+	mtsdram(DDR0_08, 0x02430001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000100);
+	mtsdram(DDR0_11, 0x0027C800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x19000000);
+	mtsdram(DDR0_18, 0x19191919);
+	mtsdram(DDR0_19, 0x19191919);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+	mtsdram(DDR0_22, 0x00267F0B);
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01010002);
+	if (speed > 133333334)
+		mtsdram(DDR0_26, 0x5B26050C);
+	else
+		mtsdram(DDR0_26, 0x5B260408);
+	mtsdram(DDR0_27, 0x0000682B);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+
+	mtsdram(DDR0_42,
+		DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+		0x00000006);
+	mtsdram(DDR0_43,
+		DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
+		0x030A0200);
+
+	mtsdram(DDR0_44, 0x00000003);
+	mtsdram(DDR0_02, 0x00000001);
+
+	denali_wait_for_dlllock();
+
+#ifdef CONFIG_DDR_DATA_EYE
+	/*
+	 * Perform data eye search if requested.
+	 */
+	denali_core_search_data_eye();
+#endif
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t size;
+	int n;
+
+	/* go through supported memory configurations */
+	for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
+		size = sdram_conf[n].size;
+
+		/* program TLB entries */
+		program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
+			    TLB_WORD2_I_ENABLE);
+
+		/*
+		 * setup denali core
+		 */
+		initdram_by_rb(sdram_conf[n].rows,
+			       sdram_conf[n].banks);
+
+		/* check for suitable configuration */
+		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
+			return size;
+
+		/* delete TLB entries */
+		remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/tasreg/Makefile b/roms/u-boot/board/esd/tasreg/Makefile
new file mode 100644
index 00000000..46f25504
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= tasreg.o flash.o
diff --git a/roms/u-boot/board/esd/tasreg/config.mk b/roms/u-boot/board/esd/tasreg/config.mk
new file mode 100644
index 00000000..40f7570c
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/roms/u-boot/board/esd/tasreg/flash.c b/roms/u-boot/board/esd/tasreg/flash.c
new file mode 100644
index 00000000..71388811
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/flash.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+/*#include <asm/ppc4xx.h>*/
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* test-only: todo: Re-do sizing to get full correct info */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/tasreg/fpgadata.c b/roms/u-boot/board/esd/tasreg/fpgadata.c
new file mode 100644
index 00000000..427b1d07
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/fpgadata.c
@@ -0,0 +1,10661 @@
+0x1f, 0x8b, 0x08, 0x08, 0x5a, 0x90, 0xc1, 0x41,
+0x00, 0x03, 0x72, 0x61, 0x73, 0x72, 0x65, 0x67,
+0x2e, 0x62, 0x69, 0x74, 0x00, 0xac, 0xfd, 0x7d,
+0x78, 0x14, 0xd7, 0x95, 0x2e, 0x8a, 0xaf, 0xde,
+0xd5, 0x88, 0x52, 0x57, 0x4b, 0x5d, 0x96, 0x48,
+0x0e, 0xb1, 0x19, 0x5c, 0x6a, 0x09, 0xd2, 0xe0,
+0x96, 0xd4, 0x6e, 0xb0, 0x90, 0x65, 0xd1, 0x2a,
+0x04, 0x33, 0xa3, 0x00, 0x13, 0x34, 0x9e, 0xdc,
+0xf3, 0x78, 0xe6, 0xe4, 0xe6, 0xd7, 0xf6, 0x90,
+0x0c, 0x93, 0x43, 0x3c, 0xc4, 0xf1, 0x9d, 0x4b,
+0x1c, 0x1f, 0x67, 0xab, 0x5b, 0x36, 0x02, 0x61,
+0xd3, 0x60, 0x32, 0xc1, 0x89, 0x27, 0xd3, 0x7c,
+0x24, 0x66, 0x6c, 0x92, 0x69, 0x24, 0x6c, 0xc4,
+0x47, 0xec, 0x92, 0xac, 0x38, 0xe2, 0xc3, 0xa0,
+0x38, 0x3e, 0x09, 0xb6, 0x19, 0xa7, 0xf1, 0xc8,
+0x8e, 0x6c, 0xcb, 0xb6, 0xf8, 0x48, 0x2c, 0x21,
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+0x70, 0xef, 0xb7, 0x1e, 0xf8, 0xea, 0xdf, 0xd5,
+0xdc, 0xff, 0xb7, 0xab, 0xe1, 0x3e, 0xd0, 0xa2,
+0xdf, 0x8a, 0x46, 0x22, 0x5f, 0xfb, 0xbb, 0x85,
+0x77, 0xd4, 0xc1, 0xdf, 0xe2, 0x7f, 0x45, 0x22,
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+0x5a, 0x04, 0xb8, 0x07, 0x00, 0xa6, 0x47, 0x3c,
+0x71, 0xfa, 0xff, 0x9b, 0x22, 0x1e, 0xc3, 0x03,
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+0xd7, 0x8b, 0x23, 0x60, 0xb8, 0xff, 0xdb, 0x13,
+0x01, 0x13, 0x5a, 0xe1, 0xa9, 0x57, 0xa0, 0xcc,
+0x80, 0xff, 0x9d, 0x7f, 0x3c, 0xe0, 0xe5, 0xc2,
+0xf8, 0x3f, 0xf5, 0x1c, 0xf6, 0xbf, 0xf5, 0x18,
+0xfa, 0x27, 0xf5, 0x7f, 0xe8, 0x39, 0xfc, 0xff,
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+0xa5, 0xb6, 0xef, 0x98, 0x11, 0xb5, 0xfc, 0x9b,
+0x14, 0xf0, 0x8a, 0xef, 0x93, 0xf5, 0x1c, 0x55,
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+0xc3, 0x41, 0x6f, 0xb5, 0xa5, 0x44, 0x7c, 0x50,
+0x96, 0x84, 0x34, 0x0f, 0xad, 0x63, 0xb3, 0x60,
+0x37, 0x54, 0x58, 0x25, 0x06, 0x1a, 0x07, 0xa1,
+0xda, 0xd2, 0xfe, 0x31, 0x31, 0x08, 0x07, 0xd0,
+0x08, 0x8d, 0xb2, 0x59, 0xfa, 0x06, 0xbc, 0xa4,
+0xae, 0x63, 0x4f, 0xc3, 0x06, 0xa8, 0x1d, 0x68,
+0x89, 0xb3, 0xd7, 0xe4, 0xfb, 0x6c, 0xc1, 0x8f,
+0xe0, 0xf9, 0x8e, 0xea, 0xac, 0x86, 0x7d, 0x08,
+0x1b, 0x78, 0x45, 0xb6, 0x78, 0x80, 0xf5, 0xc1,
+0x1e, 0x7e, 0x9b, 0xe1, 0xbb, 0xc7, 0xf8, 0x0a,
+0x1c, 0xb4, 0xc4, 0xa5, 0x6d, 0x91, 0x03, 0x78,
+0x4f, 0xf1, 0xfa, 0xb2, 0xd9, 0x7a, 0x12, 0xef,
+0x51, 0xeb, 0xd9, 0x57, 0xe0, 0x51, 0x5e, 0x9d,
+0x55, 0xef, 0x61, 0xa3, 0x20, 0xde, 0x9f, 0x96,
+0x19, 0x27, 0x8b, 0xf7, 0x2f, 0x5f, 0x6b, 0x69,
+0x20, 0xa7, 0x1e, 0xee, 0x50, 0x6c, 0x25, 0x7e,
+0x1f, 0xc3, 0x2a, 0x36, 0xd8, 0x17, 0xa1, 0x9b,
+0x87, 0x71, 0xdc, 0xd9, 0x6b, 0x70, 0x80, 0xcf,
+0x79, 0xb7, 0x98, 0xbe, 0xea, 0x86, 0xc1, 0x8a,
+0xd7, 0xf1, 0xfb, 0x9c, 0x65, 0x8f, 0xe2, 0x14,
+0x0e, 0x2d, 0x4c, 0xbc, 0x26, 0xe7, 0xfb, 0xf0,
+0x67, 0xf6, 0xc2, 0x1f, 0xcd, 0xa6, 0x54, 0x20,
+0xad, 0xcc, 0x87, 0xe3, 0x10, 0xe5, 0x25, 0x69,
+0x31, 0x9b, 0x1a, 0x78, 0x69, 0x5a, 0xf9, 0x3a,
+0x5c, 0x35, 0xf1, 0x0d, 0x4f, 0x2b, 0x7b, 0xe1,
+0x32, 0xbe, 0xcf, 0x25, 0x69, 0x2d, 0xc4, 0xf0,
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+0x5c, 0x83, 0x5d, 0x8f, 0xc2, 0x05, 0xf3, 0x9c,
+0xf5, 0x8a, 0xc9, 0xb5, 0xc2, 0xb5, 0xf8, 0xe6,
+0x4a, 0xca, 0xcb, 0x85, 0x02, 0x61, 0x3e, 0x25,
+0x69, 0x71, 0x3a, 0xdc, 0x87, 0x0d, 0xb4, 0x39,
+0x2d, 0x07, 0x84, 0x35, 0x44, 0x4a, 0xc2, 0x7d,
+0xb8, 0x3c, 0xa7, 0xa0, 0x75, 0x29, 0xde, 0x7e,
+0xcb, 0x61, 0xf0, 0x7c, 0xe8, 0xca, 0x0d, 0xc0,
+0x18, 0xf8, 0x2b, 0xeb, 0x3e, 0x6c, 0x86, 0x97,
+0xe4, 0x0c, 0x4d, 0xd1, 0x00, 0x0b, 0xaf, 0x25,
+0x65, 0x86, 0x57, 0x13, 0x65, 0xad, 0x97, 0xe8,
+0xcc, 0x20, 0x7d, 0x06, 0x26, 0x0a, 0x34, 0x4e,
+0x26, 0xac, 0x85, 0x42, 0x0b, 0x1a, 0x0a, 0xb1,
+0x0c, 0xa4, 0x45, 0x73, 0xf6, 0x1d, 0x92, 0x43,
+0x6e, 0x9a, 0x97, 0xdf, 0x2c, 0xb5, 0x90, 0xef,
+0xca, 0x33, 0x69, 0x7e, 0x4b, 0xa3, 0x66, 0x34,
+0x21, 0xb8, 0xc6, 0xa8, 0xe7, 0x2f, 0xe1, 0x1f,
+0x51, 0x9a, 0xa5, 0x3b, 0xc9, 0xf3, 0xf2, 0x0c,
+0xc3, 0x6b, 0xc0, 0x3f, 0xfa, 0xe7, 0xf2, 0x4d,
+0x80, 0x04, 0x1b, 0x9b, 0xb5, 0x2f, 0xc3, 0x3f,
+0x9a, 0xdf, 0xdc, 0x58, 0x42, 0x9c, 0x7d, 0xb9,
+0x51, 0x5e, 0xd2, 0x5b, 0x1a, 0x9a, 0x3f, 0x59,
+0x58, 0x85, 0x1b, 0x59, 0xcb, 0x7c, 0x2f, 0xdb,
+0xa4, 0x4a, 0x43, 0xb9, 0x60, 0x10, 0x34, 0x9c,
+0x16, 0xb8, 0x21, 0x25, 0x39, 0x66, 0xb2, 0x96,
+0x49, 0x6c, 0xd7, 0x9b, 0xe4, 0xda, 0xbf, 0x0c,
+0x4e, 0xc0, 0x44, 0xb4, 0xd6, 0x6c, 0xe0, 0xdc,
+0x00, 0x3e, 0x8b, 0xac, 0xbb, 0x3d, 0x14, 0x14,
+0xba, 0xb3, 0x06, 0xf3, 0x16, 0x70, 0x2a, 0x9c,
+0xdf, 0x25, 0x44, 0x9b, 0x96, 0x14, 0x96, 0xca,
+0xf3, 0x85, 0xf5, 0xdc, 0x97, 0x60, 0x78, 0x39,
+0x56, 0x58, 0xfa, 0x00, 0x62, 0x61, 0x0e, 0x9c,
+0x05, 0x68, 0x69, 0x28, 0x64, 0x78, 0x79, 0xad,
+0x1c, 0xd3, 0xf0, 0xdc, 0x95, 0xe3, 0x65, 0xb9,
+0xa1, 0xcc, 0xf6, 0xc3, 0x61, 0xff, 0x6a, 0x6a,
+0xd6, 0x4a, 0xe4, 0x5b, 0x73, 0x60, 0xdb, 0x6a,
+0x2e, 0x2c, 0x91, 0x73, 0x84, 0x42, 0xc3, 0x40,
+0xe3, 0x56, 0x30, 0x78, 0x97, 0xf0, 0x12, 0xb4,
+0x08, 0x25, 0x39, 0x39, 0x85, 0xd8, 0xa5, 0xe1,
+0x18, 0x81, 0xb5, 0xc8, 0x82, 0xa0, 0x19, 0xf6,
+0xf3, 0xa5, 0xc0, 0x0a, 0x94, 0xc4, 0x73, 0xc8,
+0x03, 0xf0, 0x40, 0x13, 0xed, 0x41, 0x3c, 0x2c,
+0x0a, 0x35, 0x60, 0x8b, 0xde, 0x4a, 0x62, 0x77,
+0xf0, 0xa7, 0x3f, 0x1a, 0x6b, 0x60, 0xa2, 0x39,
+0xec, 0x11, 0x2f, 0x11, 0x73, 0x74, 0x21, 0xca,
+0x5e, 0x0c, 0x38, 0xc6, 0xfa, 0x08, 0x80, 0x7c,
+0x3b, 0x48, 0x12, 0x89, 0x26, 0xcb, 0x6c, 0x2c,
+0x5c, 0x26, 0xb6, 0x62, 0x0b, 0x82, 0xe2, 0x56,
+0x6c, 0x21, 0x1e, 0x22, 0x52, 0x92, 0x6c, 0x06,
+0xa3, 0xd0, 0x1e, 0x93, 0x83, 0x06, 0x09, 0x64,
+0xf6, 0xaf, 0xcf, 0x03, 0xf2, 0x6d, 0x1f, 0x28,
+0x9b, 0xb9, 0x16, 0x8c, 0x28, 0x40, 0xe0, 0x99,
+0x0f, 0x7c, 0x5e, 0xf8, 0x92, 0xd2, 0x6e, 0x96,
+0xcd, 0xcc, 0xff, 0xbc, 0x28, 0x18, 0xe6, 0xc0,
+0x55, 0x21, 0xe5, 0xf3, 0x52, 0xb1, 0xd1, 0x07,
+0x5d, 0xde, 0xcf, 0x4b, 0x5f, 0x6c, 0x6a, 0x7f,
+0x69, 0xea, 0x4c, 0x25, 0xbf, 0xf8, 0x4b, 0xc6,
+0x09, 0xf8, 0x2b, 0x7b, 0xff, 0x82, 0x79, 0x06,
+0x0f, 0x7f, 0x33, 0x3a, 0xff, 0xfd, 0xb9, 0xe8,
+0xf3, 0xff, 0xad, 0x0b, 0x17, 0xf4, 0x4f, 0x6a,
+0x01, 0x50, 0xfc, 0x39, 0x5d, 0xe8, 0x9f, 0x74,
+0x0f, 0xb9, 0x2b, 0xfe, 0x39, 0x80, 0xc9, 0x62,
+0x8b, 0xb0, 0x89, 0xfe, 0xb3, 0x6b, 0x8c, 0x69,
+0xff, 0xb0, 0x72, 0xc5, 0x30, 0xb5, 0x50, 0x3b,
+0x7a, 0x59, 0x60, 0xcc, 0x90, 0xd7, 0x0a, 0x88,
+0x97, 0x11, 0x0b, 0x2f, 0x01, 0x50, 0x6c, 0x02,
+0x82, 0xf6, 0x2e, 0x29, 0xd7, 0xa2, 0x07, 0x39,
+0x5e, 0xd6, 0x0c, 0x40, 0xd0, 0x2e, 0xbc, 0x3c,
+0xcf, 0xbe, 0x0c, 0xe0, 0xe5, 0xcf, 0x5d, 0x02,
+0xe4, 0xfb, 0x9d, 0x1f, 0xd6, 0xff, 0x61, 0xd1,
+0x85, 0x7f, 0xbb, 0x72, 0xef, 0x95, 0x67, 0xb9,
+0x01, 0xe0, 0xf1, 0xfa, 0x3f, 0x30, 0x50, 0xfc,
+0x9d, 0x4b, 0xf5, 0x68, 0x5c, 0xfe, 0x7f, 0x0b,
+0x2f, 0x4f, 0x7a, 0xfa, 0xe5, 0x17, 0x53, 0xd6,
+0xf7, 0x79, 0xf7, 0xde, 0x5d, 0xcf, 0x06, 0x7f,
+0xb5, 0xe0, 0x3e, 0x06, 0x9c, 0xa7, 0xfc, 0x6a,
+0x01, 0x22, 0xe8, 0x6f, 0xad, 0x80, 0x96, 0xfb,
+0x0f, 0xbe, 0x9a, 0xba, 0xb0, 0x22, 0x62, 0x61,
+0xea, 0xff, 0x1b, 0x8c, 0xfb, 0xd9, 0x18, 0xe7,
+0x3a, 0x35, 0x75, 0x9f, 0x7b, 0xf1, 0xdf, 0x6a,
+0xfa, 0xac, 0xeb, 0x7c, 0x78, 0xef, 0xf1, 0x67,
+0x6b, 0x6e, 0x5e, 0x78, 0x81, 0x01, 0xe7, 0xeb,
+0x6f, 0x66, 0x08, 0xfa, 0xdb, 0x67, 0xa1, 0xe5,
+0x4a, 0x71, 0xa4, 0xef, 0xe2, 0xd9, 0x7a, 0x0b,
+0x53, 0x5f, 0x02, 0xe3, 0x0a, 0x1b, 0xe3, 0x5c,
+0x67, 0xce, 0x14, 0xa3, 0xaf, 0x68, 0xc6, 0xa0,
+0x57, 0x98, 0xd3, 0xf2, 0x85, 0xe7, 0x1e, 0xd9,
+0x25, 0x9f, 0xb9, 0x65, 0x8e, 0x16, 0x7d, 0x6e,
+0xc3, 0x8c, 0xf6, 0x77, 0x47, 0x25, 0xed, 0x0b,
+0x2f, 0x14, 0xef, 0x1a, 0xcc, 0x1f, 0x85, 0xae,
+0xd7, 0x1e, 0x49, 0xb5, 0x9f, 0xf9, 0xe6, 0x9c,
+0x95, 0xd1, 0x57, 0x8b, 0x6e, 0x6e, 0x5f, 0xfb,
+0xcd, 0x39, 0xa5, 0x5f, 0x78, 0x0d, 0xc7, 0x9c,
+0x76, 0xae, 0x23, 0xb6, 0x93, 0x2d, 0x24, 0xf0,
+0x8f, 0x1e, 0x8d, 0x1b, 0x86, 0xdb, 0x58, 0x15,
+0xca, 0xb4, 0x1c, 0x75, 0x77, 0x79, 0x0f, 0xda,
+0x63, 0x9c, 0xcb, 0xb8, 0x42, 0x83, 0xcc, 0x11,
+0x23, 0xee, 0x50, 0x86, 0x65, 0x64, 0x87, 0x0f,
+0x49, 0x56, 0x97, 0x73, 0x42, 0xd6, 0x8e, 0xcc,
+0x5b, 0x06, 0x7b, 0x29, 0x4c, 0x64, 0x74, 0xb0,
+0x54, 0x2b, 0x71, 0x8c, 0xe1, 0x74, 0x11, 0x6b,
+0xe7, 0xb1, 0xbe, 0xc6, 0x3f, 0xea, 0x13, 0x7c,
+0x0d, 0x65, 0x52, 0x38, 0xd3, 0x72, 0xd4, 0xd5,
+0xe5, 0x0e, 0x70, 0x3a, 0xbf, 0x8b, 0x8e, 0x3b,
+0xf8, 0x03, 0xe3, 0xe8, 0xb8, 0x96, 0x8f, 0x33,
+0xf8, 0xef, 0xfa, 0x4f, 0x0f, 0xff, 0x63, 0x57,
+0x62, 0xd7, 0x61, 0x34, 0x77, 0x1d, 0xfc, 0x7d,
+0xc9, 0x0d, 0x36, 0xa2, 0x03, 0x46, 0x58, 0x2d,
+0xe2, 0x98, 0x2e, 0x85, 0x0d, 0x26, 0x56, 0x8b,
+0xfd, 0x99, 0xf8, 0x1f, 0x39, 0xfa, 0x9f, 0xfd,
+0x46, 0xf6, 0xf7, 0x91, 0x3d, 0xed, 0xe2, 0x16,
+0xb2, 0xdd, 0x98, 0xae, 0xfd, 0x69, 0x86, 0x28,
+0xd8, 0xbf, 0x6b, 0xfc, 0x32, 0xfd, 0xef, 0x18,
+0xce, 0xfc, 0x7c, 0xd2, 0xfd, 0xf3, 0x49, 0x06,
+0xb1, 0xef, 0x9f, 0x49, 0x21, 0xe1, 0x28, 0xf9,
+0x47, 0x32, 0xd9, 0xfc, 0x93, 0x8c, 0x83, 0xf2,
+0x7f, 0xe5, 0xfb, 0x4c, 0x36, 0xed, 0x16, 0x31,
+0x73, 0x23, 0xfe, 0x09, 0xb7, 0x8d, 0xe6, 0xb4,
+0x64, 0x3e, 0x7f, 0xca, 0xcd, 0xa7, 0x65, 0xdf,
+0x85, 0x38, 0x3f, 0xe6, 0x1f, 0x7b, 0x59, 0x7e,
+0xdc, 0xc7, 0x9b, 0xf9, 0x2b, 0x9e, 0x1f, 0x15,
+0xfa, 0x53, 0xae, 0x92, 0x75, 0x45, 0x83, 0xfd,
+0x2f, 0xa4, 0xff, 0x57, 0xaf, 0x63, 0x4d, 0xd1,
+0x24, 0xf3, 0xbf, 0x78, 0x21, 0x61, 0xf8, 0xbf,
+0x78, 0x81, 0xff, 0x43, 0x9f, 0xfa, 0x2b, 0x57,
+0xae, 0x98, 0x7f, 0xba, 0xf1, 0xe9, 0x75, 0xfe,
+0x5f, 0xbe, 0xce, 0x04, 0xdb, 0xf1, 0xff, 0x8e,
+0xe1, 0x5c, 0xe7, 0xbf, 0xf8, 0x5e, 0xcd, 0x5c,
+0x67, 0xdc, 0x9e, 0xfb, 0x31, 0x86, 0x6b, 0xa7,
+0x9e, 0xe0, 0xbd, 0x4a, 0xc8, 0x7f, 0xfe, 0x5f,
+0xb7, 0x5c, 0x08, 0x32, 0xd1, 0xbe, 0xfc, 0xdf,
+0xb2, 0x9b, 0xfe, 0xf7, 0xee, 0xcb, 0xce, 0x56,
+0x3b, 0x76, 0x83, 0xfe, 0x24, 0x23, 0xeb, 0xfb,
+0xfc, 0x89, 0x6f, 0xfa, 0xb1, 0xfb, 0x32, 0xc1,
+0x1d, 0xf6, 0xe8, 0xf6, 0x7f, 0x9c, 0x70, 0xf3,
+0x5d, 0x15, 0x86, 0x2e, 0x97, 0x31, 0xf9, 0x30,
+0xeb, 0x72, 0x0f, 0xce, 0xfc, 0xae, 0xff, 0xbe,
+0x7d, 0x59, 0xff, 0xb8, 0x5d, 0x8f, 0x4e, 0xdc,
+0x45, 0xc6, 0xdf, 0x3f, 0x0a, 0xdb, 0x97, 0xc9,
+0xb8, 0x3d, 0x97, 0xb7, 0xb0, 0x9b, 0x64, 0x7c,
+0x97, 0xc1, 0xbb, 0xfe, 0x1b, 0xf6, 0xe5, 0x8c,
+0xf1, 0x5f, 0xdb, 0x97, 0x33, 0xc6, 0x7f, 0xf3,
+0xfd, 0x4c, 0x32, 0x01, 0x91, 0x3f, 0xf1, 0xc3,
+0xf3, 0xe7, 0xff, 0xbb, 0x3e, 0x75, 0x75, 0xff,
+0xc5, 0x0b, 0xf8, 0x7c, 0xff, 0x2d, 0xdf, 0xe3,
+0xff, 0xbb, 0x9f, 0xff, 0xaf, 0xed, 0x3b, 0x9f,
+0x5e, 0xe7, 0x8f, 0x5f, 0xe7, 0xbf, 0xe7, 0x13,
+0x22, 0xba, 0x20, 0xb2, 0xff, 0x37, 0x6d, 0xf8,
+0x3f, 0x70, 0xf9, 0x4f, 0x3f, 0x9f, 0x7e, 0x3e,
+0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
+0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
+0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
+0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0xff,
+0x7f, 0xf8, 0x61, 0x67, 0x4a, 0x22, 0x3b, 0x53,
+0xa2, 0xff, 0xbf, 0xfe, 0x2e, 0x9f, 0x7e, 0x3e,
+0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
+0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
+0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
+0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f,
+0x7e, 0xfe, 0xcf, 0x7e, 0x42, 0x04, 0x53, 0x21,
+0x3d, 0x7f, 0x15, 0x22, 0x14, 0x0b, 0x2c, 0xa4,
+0x10, 0x31, 0x8a, 0xfe, 0xfb, 0xae, 0xcd, 0xae,
+0x99, 0x13, 0x22, 0x49, 0x21, 0xf3, 0x6f, 0xcd,
+0xbe, 0x3c, 0x76, 0xdc, 0xff, 0x03, 0xe6, 0xeb,
+0xaf, 0xb2, 0x8c, 0x8c, 0x02, 0x00,
diff --git a/roms/u-boot/board/esd/tasreg/tasreg.c b/roms/u-boot/board/esd/tasreg/tasreg.c
new file mode 100644
index 00000000..09a90ed2
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/tasreg.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/m5249.h>
+#include <asm/io.h>
+
+
+/* Prototypes */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data)  mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_PROG_ACTIVE_HIGH          /* on this platform is PROG active high!   */
+#define out32(a,b)                     /* nothing to do (gpio already configured) */
+
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int checkboard (void) {
+	ulong val;
+	uchar val8;
+
+	puts ("Board: ");
+	puts("esd TASREG");
+	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+	printf(" (Switch=%1X)\n", val8);
+
+	/*
+	 * Set LED on
+	 */
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
+
+	return 0;
+};
+
+
+phys_size_t initdram (int board_type) {
+	unsigned long	junk = 0xa5a59696;
+
+	/*
+	 *  Note:
+	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+	 */
+
+#ifdef CONFIG_SYS_FAST_CLK
+	/*
+	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+	/*
+	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+	/*
+	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+	/*
+	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+	 * PM=1 (continuous page mode)
+	 */
+
+	/* RE=0 (keep auto-refresh disabled while setting up registers) */
+	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+	/** Precharge sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+	out_be32((void *)0, junk); /* write to a memory location to init. precharge */
+	udelay(0x10); /* Allow several Precharge cycles */
+
+	/** Refresh Sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+	udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+	/** Mode Register initialization **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+	out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	uchar buf[8];
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 *
+	 */
+	buf[0] = 0x00;
+	buf[1] = 0x32;
+	buf[2] = 0x3f;
+	i2c_write(0x38, 0, 0, buf, 3);
+
+	return (0);
+}
+
+
+#if 1 /* test-only: board specific test commands */
+int i2c_probe(uchar addr);
+
+/*
+ */
+int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+
+	printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_probe(addr);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	iploop,	2,	1,	do_iploop,
+	"i2c probe loop <addr>",
+	""
+);
+
+/*
+ */
+int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uchar buf[8];
+
+	out_be16((void *)0xe0000000, 0x4000);
+
+	udelay(5000); /* wait for 5ms */
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x01;
+	buf[2] = 0x80;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x02;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x03;
+	buf[2] = 0x29;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x04;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x05;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x02;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	codec,	1,	1,	do_codec,
+	"Enable codec",
+	""
+);
+
+/*
+ */
+int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong instr;
+	ulong cntrl;
+	ulong data;
+	uchar buf[8];
+
+	if (argc < 5) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	instr = simple_strtol (argv[2], NULL, 16);
+	cntrl = simple_strtol (argv[3], NULL, 16);
+	data = simple_strtol (argv[4], NULL, 16);
+
+	buf[0] = (uchar)instr;
+	buf[1] = (uchar)cntrl;
+	buf[2] = (uchar)data;
+	i2c_write(addr, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	saa,	5,	1,	do_saa,
+	"Write to SAA1064 <addr> <instr> <cntrl> <data>",
+	""
+);
+
+/*
+ */
+int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong data0;
+	ulong data1;
+	ulong data2;
+	ulong data3;
+	uchar buf[8];
+	int cnt;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+	data0 = simple_strtol (argv[3], NULL, 16);
+	data1 = simple_strtol (argv[4], NULL, 16);
+	data2 = simple_strtol (argv[5], NULL, 16);
+	data3 = simple_strtol (argv[6], NULL, 16);
+
+	printf("Writing %d bytes to device %lx!\n", cnt, addr);
+	buf[0] = (uchar)data0;
+	buf[1] = (uchar)data1;
+	buf[2] = (uchar)data2;
+	buf[3] = (uchar)data3;
+	i2c_write(addr, 0, 0, buf, cnt);
+
+	return 0;
+}
+U_BOOT_CMD(
+	iwrite,	6,	1,	do_iwrite,
+	"Write n bytes to I2C-device",
+	"addr cnt data0 ... datan"
+);
+
+/*
+ */
+int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	ulong cnt;
+	uchar buf[32];
+	int i;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+
+	i2c_read(addr, 0, 0, buf, cnt);
+	printf("I2C Data:");
+	for (i=0; i<cnt; i++) {
+		printf(" %02X", buf[i]);
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	iread,	3,	1,	do_iread,
+	"Read from I2C <addr> <cnt>",
+	""
+);
+
+/*
+ */
+int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr;
+	uchar buf[32];
+	int cnt;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = 1;
+
+	printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_read(addr, 0, 0, buf, cnt);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(3000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	ireadl,	2,	1,	do_ireadl,
+	"Read-loop from I2C <addr>",
+	""
+);
+#endif
diff --git a/roms/u-boot/board/esd/tasreg/u-boot.lds b/roms/u-boot/board/esd/tasreg/u-boot.lds
new file mode 100644
index 00000000..7f9e41c6
--- /dev/null
+++ b/roms/u-boot/board/esd/tasreg/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+  .text      :
+  {
+    arch/m68k/cpu/mcf52x2/start.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)      :
+  {
+   _sbss = .;
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
diff --git a/roms/u-boot/board/esd/vme8349/Makefile b/roms/u-boot/board/esd/vme8349/Makefile
new file mode 100644
index 00000000..fa11d5d1
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += vme8349.o caddy.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/roms/u-boot/board/esd/vme8349/caddy.c b/roms/u-boot/board/esd/vme8349/caddy.c
new file mode 100644
index 00000000..cd56bed9
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/caddy.c
@@ -0,0 +1,177 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+	struct caddy_answer *answer;
+	uint32_t ptr;
+
+	answer = &caddy_interface->answer[caddy_interface->answer_in];
+	memset((void *)answer, 0, sizeof(struct caddy_answer));
+	answer->answer = cmd->cmd;
+	answer->issue = cmd->issue;
+	answer->status = status;
+	memcpy(answer->par, result, 5 * sizeof(result[0]));
+	ptr = caddy_interface->answer_in + 1;
+	ptr = ptr & (ANSWER_SIZE - 1);
+	if (ptr != caddy_interface->answer_out)
+		caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long base_addr;
+	uint32_t ptr;
+	struct caddy_cmd *caddy_cmd;
+	uint32_t result[5];
+	uint16_t data16;
+	uint8_t data8;
+	uint32_t status;
+	pci_dev_t dev;
+	void *pci_ptr;
+
+	if (argc < 2) {
+		puts("Missing parameter\n");
+		return 1;
+	}
+
+	base_addr = simple_strtoul(argv[1], NULL, 16);
+	caddy_interface = (struct caddy_interface *) base_addr;
+
+	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+	while (ctrlc() == 0) {
+		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+			memset(result, 0, 5 * sizeof(result[0]));
+			status = 0;
+			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+				(caddy_cmd->addr & 0x001fffff);
+
+			switch (caddy_cmd->cmd) {
+			case CADDY_CMD_IO_READ_8:
+				result[0] = in_8(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_16:
+				result[0] = in_be16(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_32:
+				result[0] = in_be32(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_WRITE_8:
+				data8 = caddy_cmd->par[0] & 0x000000ff;
+				out_8(pci_ptr, data8);
+				break;
+
+			case CADDY_CMD_IO_WRITE_16:
+				data16 = caddy_cmd->par[0] & 0x0000ffff;
+				out_be16(pci_ptr, data16);
+				break;
+
+			case CADDY_CMD_IO_WRITE_32:
+				out_be32(pci_ptr, caddy_cmd->par[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_READ_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_byte(dev,
+							      caddy_cmd->addr,
+							      &data8);
+				result[0] = data8;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_word(dev,
+							      caddy_cmd->addr,
+							      &data16);
+				result[0] = data16;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_dword(dev,
+							       caddy_cmd->addr,
+							       &result[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data8 = caddy_cmd->par[3] & 0x000000ff;
+				status = pci_write_config_byte(dev,
+							       caddy_cmd->addr,
+							       data8);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data16 = caddy_cmd->par[3] & 0x0000ffff;
+				status = pci_write_config_word(dev,
+							       caddy_cmd->addr,
+							       data16);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_write_config_dword(dev,
+								caddy_cmd->addr,
+								caddy_cmd->par[3]);
+				break;
+
+			default:
+				status = 0xffffffff;
+				break;
+			}
+
+			generate_answer(caddy_cmd, status, &result[0]);
+
+			ptr = caddy_interface->cmd_out + 1;
+			ptr = ptr & (CMD_SIZE - 1);
+			caddy_interface->cmd_out = ptr;
+		}
+
+		caddy_interface->heartbeat++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	caddy,	2,	0,	do_caddy,
+	"Start Caddy server.",
+	"Start Caddy server with Data structure a given addr\n"
+	);
diff --git a/roms/u-boot/board/esd/vme8349/caddy.h b/roms/u-boot/board/esd/vme8349/caddy.h
new file mode 100644
index 00000000..989f3c72
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/caddy.h
@@ -0,0 +1,60 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE	1024
+#define ANSWER_SIZE	1024
+#define CADDY_MAGIC	"esd vme8349 V1.0"
+
+enum caddy_cmds {
+	CADDY_CMD_IO_READ_8,
+	CADDY_CMD_IO_READ_16,
+	CADDY_CMD_IO_READ_32,
+	CADDY_CMD_IO_WRITE_8,
+	CADDY_CMD_IO_WRITE_16,
+	CADDY_CMD_IO_WRITE_32,
+	CADDY_CMD_CONFIG_READ_8,
+	CADDY_CMD_CONFIG_READ_16,
+	CADDY_CMD_CONFIG_READ_32,
+	CADDY_CMD_CONFIG_WRITE_8,
+	CADDY_CMD_CONFIG_WRITE_16,
+	CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+	uint32_t cmd;
+	uint32_t issue;
+	uint32_t addr;
+	uint32_t par[5];
+};
+
+struct caddy_answer {
+	uint32_t answer;
+	uint32_t issue;
+	uint32_t status;
+	uint32_t par[5];
+};
+
+struct caddy_interface {
+	uint8_t  magic[16];
+	uint32_t cmd_in;
+	uint32_t cmd_out;
+	uint32_t heartbeat;
+	uint32_t reserved1;
+	struct caddy_cmd cmd[CMD_SIZE];
+	uint32_t answer_in;
+	uint32_t answer_out;
+	uint32_t reserved2;
+	uint32_t reserved3;
+	struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
diff --git a/roms/u-boot/board/esd/vme8349/pci.c b/roms/u-boot/board/esd/vme8349/pci.c
new file mode 100644
index 00000000..4d3b21dd
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/pci.c
@@ -0,0 +1,119 @@
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u8 reg8;
+	int monarch = 0;
+
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
+	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
+		if (reg8 & 0x40) {
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+			printf("PCI:   66MHz\n");
+		} else {
+			clk->occr = 0xffff0003;	/* 33 MHz PCI */
+			printf("PCI:   33MHz\n");
+		}
+		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+			monarch = 1;
+	} else {
+		clk->occr = 0xffff0003;	/* 33 MHz PCI */
+		printf("PCI:   33MHz (I2C read failed)\n");
+	}
+	udelay(2000);
+
+	/*
+	 * Assert/deassert VME reset
+	 */
+	clrsetbits_be32(&immr->gpio[1].dat,
+			GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+			GPIO2_VME_RESET_N  | GPIO2_L_RESET_EN_N);
+	setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+		     GPIO2_TSI_POWERUP_RESET_N |
+		     GPIO2_VME_RESET_N |
+		     GPIO2_L_RESET_EN_N);
+	clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
+	udelay(600000);
+	clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	if (monarch == 0) {
+		mpc83xx_pci_init(1, reg);
+	} else {
+		/*
+		 * Release PCI RST Output signal
+		 */
+		out_be32(&immr->pci_ctrl[0].gcr, 0);
+		udelay(2000);
+		out_be32(&immr->pci_ctrl[0].gcr, 1);
+	}
+}
diff --git a/roms/u-boot/board/esd/vme8349/vme8349.c b/roms/u-boot/board/esd/vme8349/vme8349.c
new file mode 100644
index 00000000..01365dcb
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/vme8349.c
@@ -0,0 +1,204 @@
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main memory */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* Now check memory size (after ECC is initialized) */
+	msize = get_ram_size(0, msize);
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef VME_CADDY2
+	puts("Board: esd VME-CADDY/2\n");
+#else
+	puts("Board: esd VME-CPU/8349\n");
+#endif
+
+	return 0;
+}
+
+#ifdef VME_CADDY2
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+
+int misc_init_r()
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
+
+	return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef VME_CADDY2
+#define SMALL_RAM	0xff
+#define LARGE_RAM	0x00
+#else
+#define SMALL_RAM	0x00
+#define LARGE_RAM	0xff
+#endif
+
+#define SPD_VAL(a, b)	(((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
+	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
+	SPD_MEMTYPE_DDR2,	/* 02 type is DDR2 */
+	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
+	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
+	SPD_VAL(0x00, 0x00),	/* 05 */
+	SPD_VAL(0x40, 0x40),	/* 06 */
+	SPD_VAL(0x00, 0x00),	/* 07 */
+	SPD_VAL(0x05, 0x05),	/* 08 */
+	SPD_VAL(0x30, 0x30),	/* 09 */
+	SPD_VAL(0x45, 0x45),	/* 10 */
+	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
+	SPD_VAL(0x82, 0x82),	/* 12 */
+	SPD_VAL(0x10, 0x10),	/* 13 */
+	SPD_VAL(0x08, 0x08),	/* 14 */
+	SPD_VAL(0x00, 0x00),	/* 15 */
+	SPD_VAL(0x0c, 0x0c),	/* 16 */
+	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
+	SPD_VAL(0x38, 0x38),	/* 18 */
+	SPD_VAL(0x00, 0x00),	/* 19 */
+	SPD_VAL(0x02, 0x02),	/* 20 */
+	SPD_VAL(0x00, 0x00),	/* 21 */
+	SPD_VAL(0x03, 0x03),	/* 22 */
+	SPD_VAL(0x3d, 0x3d),	/* 23 */
+	SPD_VAL(0x45, 0x45),	/* 24 */
+	SPD_VAL(0x50, 0x50),	/* 25 */
+	SPD_VAL(0x45, 0x45),	/* 26 */
+	SPD_VAL(0x3c, 0x3c),	/* 27 */
+	SPD_VAL(0x28, 0x28),	/* 28 */
+	SPD_VAL(0x3c, 0x3c),	/* 29 */
+	SPD_VAL(0x2d, 0x2d),	/* 30 */
+	SPD_VAL(0x20, 0x80),	/* 31 */
+	SPD_VAL(0x20, 0x20),	/* 32 */
+	SPD_VAL(0x27, 0x27),	/* 33 */
+	SPD_VAL(0x10, 0x10),	/* 34 */
+	SPD_VAL(0x17, 0x17),	/* 35 */
+	SPD_VAL(0x3c, 0x3c),	/* 36 */
+	SPD_VAL(0x1e, 0x1e),	/* 37 */
+	SPD_VAL(0x1e, 0x1e),	/* 38 */
+	SPD_VAL(0x00, 0x00),	/* 39 */
+	SPD_VAL(0x00, 0x06),	/* 40 */
+	SPD_VAL(0x37, 0x37),	/* 41 */
+	SPD_VAL(0x4b, 0x7f),	/* 42 */
+	SPD_VAL(0x80, 0x80),	/* 43 */
+	SPD_VAL(0x18, 0x18),	/* 44 */
+	SPD_VAL(0x22, 0x22),	/* 45 */
+	SPD_VAL(0x00, 0x00),	/* 46 */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	SPD_VAL(0x10, 0x10),	/* 62 */
+	SPD_VAL(0x7e, 0x1d),	/* 63 */
+	{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+	SPD_VAL(0x00, 0x00),	/* 72 */
+#ifdef VME_CADDY2
+	{ "vme-caddy/2 ram   " }
+#else
+	{ "vme-cpu/2 ram     " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int old_bus = i2c_get_bus_num();
+	unsigned int l, sum;
+	int valid = 0;
+
+	i2c_set_bus_num(0);
+
+	if (i2c_read(chip, addr, alen, buffer, len) == 0)
+		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+			sum = 0;
+			for (l = 0; l < 63; l++)
+				sum = (sum + buffer[l]) & 0xff;
+			if (sum == buffer[63])
+				valid = 1;
+			else
+				printf("Invalid checksum in EEPROM %02x %02x\n",
+				       sum, buffer[63]);
+		}
+
+	if (valid == 0) {
+		memcpy(buffer, (void *)&default_spd_eeprom, len);
+		sum = 0;
+		for (l = 0; l < 63; l++)
+			sum = (sum + buffer[l]) & 0xff;
+		if (sum != buffer[63])
+			printf("Invalid checksum in FLASH %02x %02x\n",
+			       sum, buffer[63]);
+		buffer[63] = sum;
+	}
+
+	i2c_set_bus_num(old_bus);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/esd/vme8349/vme8349pin.h b/roms/u-boot/board/esd/vme8349/vme8349pin.h
new file mode 100644
index 00000000..fcf6c59b
--- /dev/null
+++ b/roms/u-boot/board/esd/vme8349/vme8349pin.h
@@ -0,0 +1,19 @@
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON		0x80000000 /* In:  from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N	0x20000000 /* Out: to tsi148                */
+#define GPIO2_TSI_PLL_RESET_N	0x08000000 /* Out: to tsi148                */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148              */
+#define GPIO2_L_RESET_EN_N	0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/roms/u-boot/board/esd/voh405/Makefile b/roms/u-boot/board/esd/voh405/Makefile
new file mode 100644
index 00000000..3d82399e
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= voh405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/voh405/flash.c b/roms/u-boot/board/esd/voh405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/voh405/fpgadata.c b/roms/u-boot/board/esd/voh405/fpgadata.c
new file mode 100644
index 00000000..9ad96508
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/fpgadata.c
@@ -0,0 +1,4021 @@
+0x1f, 0x8b, 0x08, 0x08, 0x38, 0x6c, 0x35, 0x42,
+0x00, 0x03, 0x76, 0x6f, 0x68, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x1c, 0xd5,
+0x91, 0x2f, 0x8c, 0x57, 0x9f, 0x6e, 0xc9, 0xad,
+0xe9, 0x91, 0xa6, 0xf5, 0x62, 0x22, 0x40, 0x98,
+0xd6, 0x48, 0x98, 0x41, 0x19, 0x49, 0x63, 0xc9,
+0x18, 0x63, 0xcc, 0xa8, 0x2d, 0x09, 0x22, 0x6c,
+0x07, 0x4f, 0x80, 0xcd, 0xfa, 0x66, 0xb9, 0xd9,
+0x31, 0xf1, 0x66, 0xbd, 0xfb, 0x73, 0xb8, 0x82,
+0xe4, 0xd9, 0x75, 0x72, 0xb3, 0xe4, 0x68, 0x24,
+0xdb, 0x23, 0xcb, 0xc1, 0x83, 0x71, 0x88, 0x20,
+0xde, 0xec, 0xd8, 0x78, 0x89, 0x21, 0x4e, 0xee,
+0x58, 0x36, 0x20, 0x63, 0x16, 0x5a, 0x46, 0x80,
+0x6c, 0x8c, 0x51, 0x58, 0x27, 0xeb, 0x10, 0x42,
+0xc6, 0x44, 0x21, 0x82, 0x18, 0x22, 0x8c, 0x49,
+0xe4, 0xf7, 0xe7, 0xd4, 0xe9, 0x97, 0xe9, 0x99,
+0x91, 0xd9, 0xcd, 0xbd, 0xf7, 0x79, 0xee, 0x7e,
+0x7e, 0x8f, 0x27, 0x7f, 0xa4, 0xe8, 0x39, 0x6e,
+0xf5, 0xa9, 0x39, 0x5d, 0xf5, 0x3d, 0x55, 0xdf,
+0xaa, 0x03, 0x45, 0xbe, 0x09, 0xf3, 0x7f, 0x00,
+0xc2, 0x32, 0x50, 0xff, 0xee, 0xbf, 0xad, 0x98,
+0x1d, 0xba, 0xf6, 0x2f, 0x67, 0xfd, 0x65, 0xa8,
+0xb9, 0xe1, 0xee, 0x2f, 0x2d, 0x87, 0xbb, 0x40,
+0x69, 0xfa, 0xea, 0xb5, 0xa1, 0xbf, 0xfa, 0xda,
+0x3d, 0xb3, 0x66, 0xcf, 0x86, 0x2f, 0xb1, 0xff,
+0x0a, 0x85, 0xae, 0x6d, 0x0c, 0x35, 0x37, 0xce,
+0x9a, 0x0d, 0xcb, 0xa1, 0x68, 0xd6, 0xac, 0x79,
+0xb3, 0xaf, 0x9f, 0xd7, 0x34, 0x17, 0xfe, 0x0a,
+0x84, 0xe6, 0x6d, 0xe7, 0xd9, 0xe7, 0x89, 0x87,
+0xff, 0xec, 0xcb, 0x21, 0xa0, 0x02, 0x00, 0x4c,
+0x0b, 0x09, 0x51, 0xfc, 0x7f, 0x25, 0x24, 0x68,
+0x02, 0xd0, 0x96, 0xfa, 0x10, 0x18, 0xf8, 0xdf,
+0x60, 0x7d, 0x5f, 0x14, 0x02, 0xcd, 0xfd, 0xdf,
+0x42, 0x08, 0x74, 0x88, 0x80, 0xbe, 0x5e, 0x2d,
+0x83, 0x7f, 0xff, 0x23, 0xe8, 0x12, 0xb5, 0xe5,
+0x3f, 0x71, 0xfc, 0xf9, 0x03, 0xf4, 0x82, 0xc3,
+0x32, 0x9f, 0x96, 0xe3, 0x49, 0x4b, 0x52, 0x49,
+0xe8, 0x3f, 0x72, 0x7f, 0xb0, 0xef, 0xfa, 0xfb,
+0x37, 0xfe, 0x43, 0xf7, 0xff, 0x83, 0x7d, 0xff,
+0x3f, 0x75, 0x3c, 0xa8, 0xff, 0x81, 0xe1, 0x00,
+0x92, 0xf3, 0x3c, 0xaa, 0xa0, 0x41, 0x07, 0x14,
+0x82, 0x40, 0x21, 0x0a, 0x95, 0x17, 0x10, 0x5a,
+0x86, 0xed, 0xf1, 0x86, 0x70, 0x0e, 0xce, 0xd3,
+0x96, 0x03, 0xbe, 0x81, 0xee, 0x7b, 0xe1, 0x1c,
+0x84, 0xf5, 0xe2, 0x09, 0xf1, 0x3e, 0xf5, 0x4d,
+0xb5, 0x45, 0xf3, 0xbd, 0x24, 0x1e, 0x87, 0x33,
+0xb4, 0xb9, 0xd2, 0xbb, 0x4f, 0x0c, 0x41, 0xa7,
+0x3d, 0x3e, 0xfe, 0x63, 0xd8, 0x4b, 0x1b, 0x26,
+0x94, 0x13, 0x7d, 0x7e, 0x58, 0x67, 0x34, 0xec,
+0xf3, 0x9c, 0x28, 0xab, 0xad, 0xe8, 0x8d, 0x34,
+0x68, 0x4a, 0x8c, 0xbc, 0x03, 0x83, 0xd4, 0x2f,
+0xcb, 0xb1, 0x7d, 0xa1, 0x5a, 0x5b, 0x8b, 0x23,
+0xd2, 0x7a, 0xd8, 0x05, 0x41, 0x43, 0x69, 0x22,
+0x00, 0x03, 0x0b, 0x82, 0x23, 0x97, 0xce, 0x22,
+0x2b, 0x20, 0xa1, 0xad, 0xd4, 0x94, 0x42, 0x62,
+0xc0, 0x20, 0x68, 0x95, 0x72, 0x39, 0x69, 0x02,
+0xcd, 0xbe, 0xbf, 0xb4, 0x03, 0xf6, 0x42, 0x83,
+0xa1, 0xa4, 0x88, 0x46, 0xd7, 0x91, 0x86, 0xb4,
+0x27, 0x45, 0x02, 0x6a, 0x3c, 0x7e, 0xab, 0xae,
+0xc4, 0x49, 0x5a, 0xdf, 0x43, 0xfd, 0x9a, 0xdc,
+0x4f, 0x42, 0x92, 0xfd, 0x3c, 0x37, 0x4d, 0x3f,
+0x06, 0xa7, 0xd9, 0x78, 0x5f, 0xaa, 0xcd, 0x0f,
+0xa7, 0x92, 0xe1, 0x0f, 0x8b, 0x53, 0x0b, 0x16,
+0xc3, 0x11, 0x63, 0x86, 0xe0, 0x7b, 0x44, 0x4c,
+0xc3, 0x84, 0x36, 0xb0, 0xc2, 0xbb, 0x5e, 0x54,
+0xdb, 0xed, 0xf1, 0x49, 0xe1, 0x59, 0x78, 0x1e,
+0xae, 0x64, 0xe3, 0xd9, 0x77, 0x1f, 0x24, 0xc2,
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diff --git a/roms/u-boot/board/esd/voh405/logo_320_240_4bpp.c b/roms/u-boot/board/esd/voh405/logo_320_240_4bpp.c
new file mode 100644
index 00000000..5dfc1f7b
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/logo_320_240_4bpp.c
@@ -0,0 +1,153 @@
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diff --git a/roms/u-boot/board/esd/voh405/logo_640_480_24bpp.c b/roms/u-boot/board/esd/voh405/logo_640_480_24bpp.c
new file mode 100644
index 00000000..defa69f4
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/logo_640_480_24bpp.c
@@ -0,0 +1,3443 @@
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+0xfa, 0xef, 0x55, 0x6f, 0xa3, 0xc1, 0x4e, 0xd3,
+0x4b, 0x04, 0x00, 0x00, 0x00, 0x42, 0x07, 0x2d,
+0x9f, 0x18, 0x6c, 0x08, 0xbc, 0x67, 0xa1, 0xe9,
+0x25, 0x02, 0x00, 0x00, 0x00, 0xa1, 0x83, 0x8f,
+0x14, 0xbc, 0xe4, 0xf5, 0x01, 0xfa, 0xef, 0xac,
+0x0b, 0x30, 0xb2, 0x10, 0x00, 0x00, 0x00, 0xc8,
+0x27, 0x1e, 0xa5, 0x09, 0x9f, 0x0a, 0xd0, 0x7f,
+0xaf, 0x7d, 0x37, 0x45, 0x06, 0x4c, 0x2f, 0x12,
+0x00, 0x00, 0x00, 0x08, 0x1d, 0xb4, 0xf8, 0x96,
+0x00, 0xfd, 0xf7, 0xa2, 0xb3, 0xf8, 0x10, 0x43,
+0x00, 0x00, 0x00, 0x00, 0xe4, 0x42, 0x4d, 0xfb,
+0x69, 0xec, 0xd9, 0x41, 0xa6, 0xa0, 0x7f, 0x8d,
+0x39, 0x86, 0x00, 0x00, 0x00, 0x40, 0x1e, 0x14,
+0x8f, 0xd2, 0x1d, 0x9f, 0x0c, 0xd0, 0x7f, 0x6f,
+0x78, 0x3f, 0x0d, 0xf5, 0x98, 0x5e, 0x25, 0x00,
+0x00, 0x00, 0x10, 0x3a, 0x68, 0xd1, 0xb8, 0x20,
+0x53, 0xd0, 0xaf, 0x46, 0x0a, 0x1a, 0x00, 0x00,
+0x00, 0x28, 0x84, 0x8e, 0x6f, 0xe3, 0x2e, 0x19,
+0x9c, 0x05, 0xcf, 0xbd, 0xd4, 0xf4, 0x12, 0x01,
+0x00, 0x00, 0x80, 0xd0, 0x41, 0x89, 0x38, 0x8d,
+0xff, 0x48, 0x90, 0x29, 0xe8, 0xf7, 0x51, 0x3c,
+0x6a, 0x7a, 0x95, 0x00, 0x00, 0x00, 0x40, 0xe8,
+0xa0, 0x45, 0x37, 0x05, 0x99, 0x82, 0x3e, 0x8b,
+0x6a, 0xd6, 0x9a, 0x5e, 0x22, 0x00, 0x00, 0x00,
+0x10, 0x3a, 0xe8, 0xf8, 0x56, 0x1a, 0xfb, 0x9a,
+0x20, 0x53, 0xd0, 0x97, 0x99, 0x5e, 0x22, 0x00,
+0x00, 0x00, 0x10, 0x3e, 0xa2, 0x83, 0xc1, 0xa6,
+0xa0, 0xc7, 0x7d, 0x88, 0xa2, 0xc3, 0xa6, 0x17,
+0x09, 0x00, 0x00, 0x00, 0x84, 0x0e, 0x9a, 0x77,
+0x45, 0x80, 0xfe, 0x3b, 0xe6, 0xd5, 0x54, 0xbf,
+0xd5, 0xf4, 0x12, 0x01, 0x00, 0x00, 0x80, 0xd0,
+0x41, 0xf5, 0x9b, 0xe9, 0xa2, 0x57, 0x05, 0x68,
+0xc1, 0xcf, 0xfe, 0xd6, 0xf4, 0x12, 0x01, 0x00,
+0x00, 0x80, 0xd0, 0x41, 0xf1, 0x18, 0xdd, 0xf4,
+0xc1, 0x20, 0x53, 0xd0, 0x7f, 0x6b, 0xc5, 0x86,
+0x4c, 0xaf, 0x12, 0x00, 0x00, 0x00, 0x08, 0x17,
+0xc4, 0x98, 0x77, 0x79, 0x80, 0xfe, 0x3b, 0xf6,
+0x6c, 0xaa, 0xdf, 0x62, 0x7a, 0x95, 0x00, 0x00,
+0x00, 0x40, 0xe8, 0xa0, 0xc3, 0xab, 0x82, 0x4d,
+0x41, 0x2f, 0x1a, 0x67, 0x7a, 0x89, 0x00, 0x00,
+0x00, 0x40, 0xe8, 0xa0, 0x48, 0x3f, 0x5d, 0xff,
+0xde, 0x00, 0xfd, 0x77, 0xfc, 0x47, 0x31, 0x0e,
+0x18, 0x00, 0x00, 0x00, 0x28, 0x84, 0xe6, 0x07,
+0x59, 0x05, 0xcd, 0x74, 0x62, 0x87, 0xe9, 0x25,
+0x02, 0x00, 0x00, 0x00, 0xa1, 0x83, 0x8e, 0x04,
+0x9d, 0x82, 0xbe, 0xc9, 0xf4, 0x12, 0x01, 0x00,
+0x00, 0x80, 0xd0, 0x41, 0x43, 0xbd, 0xc1, 0xa6,
+0xa0, 0xef, 0xfc, 0x34, 0xc5, 0x22, 0xa6, 0x57,
+0x09, 0x00, 0x00, 0x00, 0x84, 0x0c, 0x22, 0x9a,
+0xf5, 0xab, 0x00, 0xfd, 0xf7, 0xe2, 0xd7, 0xd1,
+0xc9, 0xbd, 0xa6, 0x17, 0x09, 0x00, 0x00, 0x00,
+0x84, 0x0e, 0x3a, 0xf0, 0x22, 0x5d, 0x78, 0x56,
+0x80, 0x16, 0xfc, 0xe2, 0x04, 0xd3, 0x4b, 0x04,
+0x00, 0x00, 0x00, 0x42, 0x07, 0xc5, 0x86, 0xe8,
+0xda, 0x77, 0x05, 0xe8, 0xbf, 0xb7, 0x7f, 0xd2,
+0x4a, 0xc4, 0x4d, 0xaf, 0x12, 0x00, 0x00, 0x00,
+0x08, 0x1d, 0x34, 0xeb, 0x97, 0x01, 0xfa, 0xef,
+0x98, 0xb3, 0xe9, 0xf4, 0x41, 0xd3, 0x4b, 0x04,
+0x00, 0x00, 0x00, 0x42, 0x07, 0xed, 0x5b, 0x1c,
+0xa0, 0xff, 0x32, 0x2d, 0xbb, 0xd7, 0xf4, 0x12,
+0x01, 0x00, 0x00, 0x80, 0xd0, 0x41, 0x03, 0x1d,
+0x74, 0xd5, 0xdb, 0x03, 0xf4, 0xdf, 0xfb, 0xfe,
+0x8d, 0x92, 0x48, 0x41, 0x03, 0x00, 0x00, 0x00,
+0x79, 0x10, 0xcd, 0xf8, 0x59, 0x80, 0xfe, 0x3b,
+0xf6, 0x6c, 0x6a, 0xa9, 0x35, 0xbd, 0x46, 0x00,
+0x00, 0x00, 0x20, 0x74, 0xd0, 0x9e, 0x45, 0xc1,
+0xa6, 0xa0, 0x97, 0x4f, 0x34, 0xbd, 0x44, 0x00,
+0x00, 0x00, 0x20, 0x74, 0xd0, 0x50, 0x0f, 0x5d,
+0xf5, 0xb6, 0x40, 0x53, 0xd0, 0x56, 0x22, 0x66,
+0x7a, 0x95, 0x00, 0x00, 0x00, 0x40, 0xd8, 0x20,
+0x7a, 0xec, 0x87, 0x01, 0xfa, 0xef, 0xa5, 0x6f,
+0x44, 0x0a, 0x1a, 0x00, 0x00, 0x00, 0x28, 0x84,
+0xb6, 0xcd, 0x09, 0x36, 0x05, 0xbd, 0xe6, 0x21,
+0xd3, 0x4b, 0x04, 0x00, 0x00, 0x00, 0x42, 0x07,
+0xf5, 0xb6, 0xd0, 0xe5, 0x6f, 0x0e, 0xd0, 0x7f,
+0x1f, 0xf8, 0xf2, 0xff, 0x07, 0x66, 0x87, 0xe4,
+0x0f, 0x36, 0x10, 0x0e, 0x00,
diff --git a/roms/u-boot/board/esd/voh405/voh405.c b/roms/u-boot/board/esd/voh405/voh405.c
new file mode 100644
index 00000000..3cc2206b
--- /dev/null
+++ b/roms/u-boot/board/esd/voh405/voh405.c
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13806_320_240_4bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	unsigned short *lcd_contrast =
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
+	unsigned short *lcd_backlight =
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Setup EEPROM write protection
+	 */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8(duart0_mcr, 0x08);
+	out_8(duart1_mcr, 0x08);
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	str = getenv("bd_type");
+	if (strcmp(str, "voh405_bw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwbw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_320_240_4bpp,
+			 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwc") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else {
+		printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+		return 0;
+	}
+
+	/*
+	 * Set invert bit in small lcd controller
+	 */
+	out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
+	      in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
+
+	/*
+	 * Set default contrast voltage on epson vga controller
+	 */
+	out_be16(lcd_contrast, 0x4646);
+
+	/*
+	 * Enable backlight
+	 */
+	out_be16(lcd_backlight, 0xffff);
+
+	/*
+	 * Enable external I2C bus
+	 */
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s)", str);
+	} else {
+		puts(" (Missing bd_type!)");
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		out_be16((void *)FPGA_MODE,
+			 in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		out_be16((void *)FPGA_MODE,
+			 in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/roms/u-boot/board/esd/vom405/Makefile b/roms/u-boot/board/esd/vom405/Makefile
new file mode 100644
index 00000000..7cf5c022
--- /dev/null
+++ b/roms/u-boot/board/esd/vom405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+obj-y	= vom405.o flash.o ../common/misc.o $(CPLD)
diff --git a/roms/u-boot/board/esd/vom405/flash.c b/roms/u-boot/board/esd/vom405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/vom405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/vom405/vom405.c b/roms/u-boot/board/esd/vom405/vom405.c
new file mode 100644
index 00000000..7de6f665
--- /dev/null
+++ b/roms/u-boot/board/esd/vom405/vom405.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Init magnetic coupler
+	 */
+	if (!getenv("noinitcoupler"))
+		init_coupler(CAN_BA);
+
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+	int flashcnt;
+	int delay;
+	u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOM405");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n", in_8(led_reg));
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		out_8(led_reg, 0x40);        /* LED_B..D off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		out_8(led_reg, 0x47);        /* LED_B..D on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	out_8(led_reg, 0x40);
+
+	return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/roms/u-boot/board/esd/wuh405/Makefile b/roms/u-boot/board/esd/wuh405/Makefile
new file mode 100644
index 00000000..b9beeffc
--- /dev/null
+++ b/roms/u-boot/board/esd/wuh405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= wuh405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/roms/u-boot/board/esd/wuh405/flash.c b/roms/u-boot/board/esd/wuh405/flash.c
new file mode 100644
index 00000000..23e81642
--- /dev/null
+++ b/roms/u-boot/board/esd/wuh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/roms/u-boot/board/esd/wuh405/fpgadata.c b/roms/u-boot/board/esd/wuh405/fpgadata.c
new file mode 100644
index 00000000..a964f9fd
--- /dev/null
+++ b/roms/u-boot/board/esd/wuh405/fpgadata.c
@@ -0,0 +1,3636 @@
+0x1f, 0x8b, 0x08, 0x08, 0xe2, 0x44, 0xc5, 0x42,
+0x00, 0x03, 0x77, 0x75, 0x68, 0x34, 0x30, 0x35,
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+0x4a, 0x90, 0xe8, 0xf0, 0xb8, 0x61, 0x8c, 0xb3,
+0x6f, 0xc5, 0xf8, 0x37, 0xa6, 0x7c, 0x49, 0x3b,
+0x10, 0x9b, 0x9f, 0x74, 0x7f, 0xdb, 0x75, 0x15,
+0x6c, 0xa2, 0x95, 0x23, 0xae, 0x6f, 0xcf, 0x7e,
+0x05, 0x0e, 0xc4, 0xbe, 0x3e, 0xe2, 0xde, 0x40,
+0xde, 0x60, 0x57, 0xd8, 0x4f, 0x1b, 0xc8, 0x09,
+0xeb, 0xf9, 0x6d, 0xf2, 0x32, 0xf8, 0x30, 0xde,
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+0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0xad, 0xe7,
+0x4b, 0xd6, 0x0e, 0x09, 0x5d, 0x3b, 0x68, 0x69,
+0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
+0x69, 0x3d, 0x5f, 0xb2, 0x76, 0x30, 0x65, 0xed,
+0xf0, 0xbf, 0x0e, 0x45, 0x4b, 0x4b, 0x4b, 0x4b,
+0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0xeb, 0xbf,
+0x28, 0x5f, 0xfc, 0xd1, 0x24, 0xf8, 0xe7, 0x79,
+0x1f, 0xb8, 0xf8, 0xce, 0x53, 0xdc, 0x07, 0xf6,
+0xb9, 0xdf, 0x27, 0xd4, 0x3f, 0x6b, 0xf8, 0x50,
+0x25, 0xd1, 0x39, 0x1f, 0x9f, 0x7e, 0xb6, 0xdf,
+0xbf, 0x00, 0x34, 0x34, 0xbf, 0x69, 0xee, 0x33,
+0x01, 0x00,
diff --git a/roms/u-boot/board/esd/wuh405/wuh405.c b/roms/u-boot/board/esd/wuh405/wuh405.c
new file mode 100644
index 00000000..71d16e48
--- /dev/null
+++ b/roms/u-boot/board/esd/wuh405/wuh405.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10); /* wait 10us */
+	out_be32((void *)GPIO0_OR,
+		 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)(DUART0_BA + 4), 0x08);
+	out_8((void *)(DUART1_BA + 4), 0x08);
+	out_8((void *)(DUART2_BA + 4), 0x08);
+	out_8((void *)(DUART3_BA + 4), 0x08);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming WUH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}