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author | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-17 02:17:46 +0100 |
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committer | GitHub <noreply@github.com> | 2018-03-17 02:17:46 +0100 |
commit | 7a4c7975c2b0932dbc2a81efb999a748f64359a4 (patch) | |
tree | 5ead0c64b15796c31bca72f61ee2201c6cbdd321 /os/hal/ports | |
parent | 272ee7c0d3e5ed4210e81ce03d2ce9a092301ad6 (diff) | |
parent | 708bb829ea4bfe945ada43047b9089768e065707 (diff) | |
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Merge pull request #150 from marcoveeneman/update_tiva_pal_testhal
Changed directory structure of Tiva PAL testhal
Diffstat (limited to 'os/hal/ports')
-rw-r--r-- | os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c | 2 | ||||
-rw-r--r-- | os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index 126959f..2255110 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -258,7 +258,7 @@ void spi_lld_start(SPIDriver *spip) nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); } #endif -#if TIVASPI_USE_SSI2 +#if TIVA_SPI_USE_SSI2 if (&SPID2 == spip) { bool b; b = udmaChannelAllocate(spip->dmarxnr); diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 4dcf6db..c93c189 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -156,7 +156,7 @@ #error "Invalid IRQ priority assigned to SSI2" #endif -#if TM4C123x_SPI_USE_SSI3 && \ +#if TIVA_SPI_USE_SSI3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif |