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| author | Fabio Utzig <utzig@utzig.org> | 2016-03-28 20:38:51 -0300 |
|---|---|---|
| committer | Fabio Utzig <utzig@utzig.org> | 2016-03-28 20:38:51 -0300 |
| commit | 1b08012c7567e7ddabd7483d24c7e11919a76f3c (patch) | |
| tree | 4bae5eb90713a09dd408121c5c35596df27be8f2 /testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h | |
| parent | 778340c65318a9935a2f937ff520a32397fd07ad (diff) | |
| parent | 341cad14a9ca8c2ed6b8a8b3a7e7183c71e00e70 (diff) | |
| download | ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.tar.gz ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.tar.bz2 ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.zip | |
Merge flabbergast-kinetis
Diffstat (limited to 'testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h')
| -rw-r--r-- | testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h b/testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h new file mode 100644 index 0000000..b657ccf --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h @@ -0,0 +1,78 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+
+/* Select the MCU clocking mode below by enabling the appropriate block. */
+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
+
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif /* 0 */
+
+/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
+#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
+#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif /* 0 */
+
+/* FEE mode - 48 MHz */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#endif /* 0 */
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define KINETIS_ADC_USE_ADC0 TRUE
+
+#endif /* _MCUCONF_H_ */
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