diff options
| author | Fabio Utzig <utzig@utzig.org> | 2016-03-28 20:38:51 -0300 |
|---|---|---|
| committer | Fabio Utzig <utzig@utzig.org> | 2016-03-28 20:38:51 -0300 |
| commit | 1b08012c7567e7ddabd7483d24c7e11919a76f3c (patch) | |
| tree | 4bae5eb90713a09dd408121c5c35596df27be8f2 | |
| parent | 778340c65318a9935a2f937ff520a32397fd07ad (diff) | |
| parent | 341cad14a9ca8c2ed6b8a8b3a7e7183c71e00e70 (diff) | |
| download | ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.tar.gz ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.tar.bz2 ChibiOS-Contrib-1b08012c7567e7ddabd7483d24c7e11919a76f3c.zip | |
Merge flabbergast-kinetis
234 files changed, 39139 insertions, 3452 deletions
diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile index be132f5..1453c5e 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile +++ b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h index 198a03d..4a1adfc 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-K20D50M-EXT/mcuconf.h @@ -25,13 +25,13 @@ /* Select the MCU clocking mode below by enabling the appropriate block. */
-/* Disable all clock intialization */
+/* Enable clock initialization by HAL */
#define KINETIS_NO_INIT FALSE
-/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
+/* PEE mode - external (8 MHz) crystal with PLL for 48 MHz core/system clock. */
#if 1
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
-#define KINETIS_XTAL_FREQUENCY 8000000UL
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#endif
@@ -41,28 +41,35 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile b/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile index be132f5..1453c5e 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
diff --git a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h index 6189709..44d2e79 100644 --- a/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h @@ -31,7 +31,7 @@ /* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
#if 1
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
-#define KINETIS_XTAL_FREQUENCY 8000000UL
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#endif
@@ -41,28 +41,35 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile index eb54d34..cb575fb 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile +++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile @@ -84,7 +84,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
@@ -97,7 +97,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/KL25Z128.ld
+LDSCRIPT = $(STARTUPLD)/MKL2xZ128.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h index da7ba95..9118e7b 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h @@ -24,11 +24,23 @@ */
/* Select the MCU clocking mode below by enabling the appropriate block. */
+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
-/* FEI mode */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode - ~24MHz */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
-#define KINETIS_SYSCLK_FREQUENCY 21000000UL
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
@@ -36,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
@@ -49,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile b/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile index eb54d34..cb575fb 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile +++ b/demos/KINETIS/RT-FREEDOM-KL25Z/Makefile @@ -84,7 +84,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
@@ -97,7 +97,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/KL25Z128.ld
+LDSCRIPT = $(STARTUPLD)/MKL2xZ128.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h index 3b77632..d4aa072 100644 --- a/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h +++ b/demos/KINETIS/RT-FREEDOM-KL25Z/mcuconf.h @@ -17,20 +17,6 @@ #ifndef _MCUCONF_H_
#define _MCUCONF_H_
-/*
- * STM32F0xx drivers configuration.
- * The following settings override the default settings present in
- * the various device driver implementation headers.
- * Note that the settings for each driver only have effect if the whole
- * driver is enabled in halconf.h.
- *
- * IRQ priorities:
- * 3...0 Lowest...Highest.
- *
- * DMA priorities:
- * 0...3 Lowest...Highest.
- */
-
#define KL2x_MCUCONF
/*
@@ -38,11 +24,23 @@ */
/* Select the MCU clocking mode below by enabling the appropriate block. */
+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
-/* FEI mode */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode - ~24MHz */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
-#define KINETIS_SYSCLK_FREQUENCY 21000000UL
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz * 732 (~24 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~12MHz) bus/flash clock */
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
@@ -50,12 +48,11 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
@@ -63,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile b/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile index 34796ce..e38ba95 100644 --- a/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile +++ b/demos/KINETIS/RT-MCHCK-K20-GPT/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
@@ -102,7 +102,8 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
+# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader
+LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -196,7 +197,9 @@ CPPWARN = -Wall -Wextra -Wundef #
# List all user C define here, like -D_DEBUG=1
-UDEFS =
+# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader,
+# 0xc00 for a 3k bootloader
+UDEFS = -DCORTEX_VTOR_INIT=0x00001000
# Define ASM defines here
UADEFS =
diff --git a/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h index cc4b581..eace87f 100644 --- a/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h +++ b/demos/KINETIS/RT-MCHCK-K20-GPT/mcuconf.h @@ -32,27 +32,34 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 2
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV2)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV4)
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
@@ -72,7 +79,5 @@ */
#define KINETIS_GPT_USE_PIT0 TRUE
#define KINETIS_GPT_PIT0_IRQ_PRIORITY 8
-/* TODO: Move this to a KINETIS registry */
-#define KINETIS_HAS_PIT0 TRUE
#endif /* _MCUCONF_H_ */
diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile index 34796ce..e38ba95 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
@@ -102,7 +102,8 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
+# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader
+LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -196,7 +197,9 @@ CPPWARN = -Wall -Wextra -Wundef #
# List all user C define here, like -D_DEBUG=1
-UDEFS =
+# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader,
+# 0xc00 for a 3k bootloader
+UDEFS = -DCORTEX_VTOR_INIT=0x00001000
# Define ASM defines here
UADEFS =
diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h index 70b86cf..81cd6cc 100644 --- a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h @@ -32,27 +32,34 @@ #define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 2
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV2)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV4)
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/demos/KINETIS/RT-TEENSY3/Makefile b/demos/KINETIS/RT-TEENSY3/Makefile index 44ad3b4..36145ce 100644 --- a/demos/KINETIS/RT-TEENSY3/Makefile +++ b/demos/KINETIS/RT-TEENSY3/Makefile @@ -89,7 +89,7 @@ PROJECT = ch CHIBIOS = ../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
# Startup files.
-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
diff --git a/demos/KINETIS/RT-TEENSY3/main.c b/demos/KINETIS/RT-TEENSY3/main.c index 591bd0f..ebeb637 100644 --- a/demos/KINETIS/RT-TEENSY3/main.c +++ b/demos/KINETIS/RT-TEENSY3/main.c @@ -27,7 +27,7 @@ static THD_FUNCTION(Thread1, arg) { (void)arg;
chRegSetThreadName("LEDBlinker");
while (true) {
- palTogglePad(IOPORT3, PORTC_TEENSY_PIN13);
+ palTogglePad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
chThdSleepMilliseconds(500);
}
}
diff --git a/demos/KINETIS/RT-TEENSY3/mcuconf.h b/demos/KINETIS/RT-TEENSY3/mcuconf.h index ae35fe3..f4e1f8d 100644 --- a/demos/KINETIS/RT-TEENSY3/mcuconf.h +++ b/demos/KINETIS/RT-TEENSY3/mcuconf.h @@ -25,32 +25,48 @@ /* Select the MCU clocking mode below by enabling the appropriate block. */
-/* FEI mode */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode (~48MHz) */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
-#define KINETIS_SYSCLK_FREQUENCY 21000000UL
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
diff --git a/os/common/ext/CMSIS/KINETIS/k20x5.h b/os/common/ext/CMSIS/KINETIS/k20x5.h new file mode 100644 index 0000000..c309f04 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/k20x5.h @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _K20x5_H_ +#define _K20x5_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + InitialSP_IRQn = -15, + InitialPC_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** K20x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, // Vector40 + DMA1_IRQn = 1, // Vector44 + DMA2_IRQn = 2, // Vector48 + DMA3_IRQn = 3, // Vector4C + DMAError_IRQn = 4, // Vector50 + DMA_IRQn = 5, // Vector54 + FlashMemComplete_IRQn = 6, // Vector58 + FlashMemReadCollision_IRQn = 7, // Vector5C + LowVoltageWarning_IRQn = 8, // Vector60 + LLWU_IRQn = 9, // Vector64 + WDOG_IRQn = 10, // Vector68 + I2C0_IRQn = 11, // Vector6C + SPI0_IRQn = 12, // Vector70 + I2S0_IRQn = 13, // Vector74 + I2S1_IRQn = 14, // Vector78 + UART0LON_IRQn = 15, // Vector7C + UART0Status_IRQn = 16, // Vector80 + UART0Error_IRQn = 17, // Vector84 + UART1Status_IRQn = 18, // Vector88 + UART1Error_IRQn = 19, // Vector8C + UART2Status_IRQn = 20, // Vector90 + UART2Error_IRQn = 21, // Vector94 + ADC0_IRQn = 22, // Vector98 + CMP0_IRQn = 23, // Vector9C + CMP1_IRQn = 24, // VectorA0 + FTM0_IRQn = 25, // VectorA4 + FTM1_IRQn = 26, // VectorA8 + CMT_IRQn = 27, // VectorAC + RTCAlarm_IRQn = 28, // VectorB0 + RTCSeconds_IRQn = 29, // VectorB4 + PITChannel0_IRQn = 30, // VectorB8 + PITChannel1_IRQn = 31, // VectorBC + PITChannel2_IRQn = 32, // VectorC0 + PITChannel3_IRQn = 33, // VectorC4 + PDB_IRQn = 34, // VectorC8 + USB_OTG_IRQn = 35, // VectorCC + USBChargerDetect_IRQn = 36, // VectorD0 + TSI_IRQn = 37, // VectorD4 + MCG_IRQn = 38, // VectorD8 + LPTMR0_IRQn = 39, // VectorDC + PINA_IRQn = 40, // VectorE0 + PINB_IRQn = 41, // VectorE4 + PINC_IRQn = 42, // VectorE8 + PIND_IRQn = 43, // VectorEC + PINE_IRQn = 44, // VectorF0 + SoftInitInt_IRQn = 45, // VectorF4 +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __FPU_PRESENT 0 +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#include "k20xx.h" + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008000) +#define FTFL_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define SPI0_BASE ((uint32_t)0x4002C000) +#define PIT_BASE ((uint32_t)0x40037000) +#define FTM0_BASE ((uint32_t)0x40038000) +#define FTM1_BASE ((uint32_t)0x40039000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define VBAT_BASE ((uint32_t)0x4003E000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define WDOG_BASE ((uint32_t)0x40052000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFL ((FTFL_TypeDef *) FTFL_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define FTM0 ((FTM_TypeDef *) FTM0_BASE) +#define FTM1 ((FTM_TypeDef *) FTM1_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */ +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */ +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) +#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) +#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ +#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ +#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ +#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ +#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) +#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) + +/****** Bits definition for SIM_CLKDIV2 register ***********/ +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) +#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) +#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + +#endif diff --git a/os/common/ext/CMSIS/KINETIS/k20x7.h b/os/common/ext/CMSIS/KINETIS/k20x7.h new file mode 100644 index 0000000..87a4e52 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/k20x7.h @@ -0,0 +1,362 @@ +/* + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _K20x7_H_ +#define _K20x7_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + InitialSP_IRQn = -15, + InitialPC_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** K20x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, // Vector40 + DMA1_IRQn = 1, // Vector44 + DMA2_IRQn = 2, // Vector48 + DMA3_IRQn = 3, // Vector4C + DMA4_IRQn = 4, // Vector50 + DMA5_IRQn = 5, // Vector54 + DMA6_IRQn = 6, // Vector58 + DMA7_IRQn = 7, // Vector5C + DMA8_IRQn = 8, // Vector60 + DMA9_IRQn = 9, // Vector64 + DMA10_IRQn = 10, // Vector68 + DMA11_IRQn = 11, // Vector6C + DMA12_IRQn = 12, // Vector70 + DMA13_IRQn = 13, // Vector74 + DMA14_IRQn = 14, // Vector78 + DMA15_IRQn = 15, // Vector7C + DMAError_IRQn = 16, // Vector80 + //~ DMA_IRQn = 17, // Vector84 + FlashMemComplete_IRQn = 18, // Vector88 + FlashMemReadCollision_IRQn = 19, // Vector8C + LowVoltageWarning_IRQn = 20, // Vector90 + LLWU_IRQn = 21, // Vector94 + WDOG_IRQn = 22, // Vector98 + I2C0_IRQn = 24, // VectorA0 + I2C1_IRQn = 25, // VectorA4 + SPI0_IRQn = 26, // VectorA8 + SPI1_IRQn = 27, // VectorAC + CANMessage_IRQn = 29, // VectorB4 + CANBusOff = 30, // VectorB8 + CANError = 31, // VectorBC + CANTxWarning = 32, // VectorC0 + CANRxWarning = 33, // VectorC4 + CANWakeUp = 34, // VectorC8 + I2S0Tx_IRQn = 35, // VectorCC + I2S1Rx_IRQn = 36, // VectorD0 + UART0LON_IRQn = 44, // VectorF0 + UART0Status_IRQn = 45, // VectorF4 + UART0Error_IRQn = 46, // VectorF8 + UART1Status_IRQn = 47, // VectorFC + UART1Error_IRQn = 48, // Vector100 + UART2Status_IRQn = 49, // Vector104 + UART2Error_IRQn = 50, // Vector108 + ADC0_IRQn = 57, // Vector124 + ADC1_IRQn = 58, // Vector128 + CMP0_IRQn = 59, // Vector12C + CMP1_IRQn = 60, // Vector130 + CMP2_IRQn = 61, // Vector134 + FTM0_IRQn = 62, // Vector138 + FTM1_IRQn = 63, // Vector13C + FTM2_IRQn = 64, // Vector140 + CMT_IRQn = 65, // Vector144 + RTCAlarm_IRQn = 66, // Vector148 + RTCSeconds_IRQn = 67, // Vector14C + PITChannel0_IRQn = 68, // Vector150 + PITChannel1_IRQn = 69, // Vector154 + PITChannel2_IRQn = 70, // Vector158 + PITChannel3_IRQn = 71, // Vector15C + PDB_IRQn = 72, // Vector160 + USB_OTG_IRQn = 73, // Vector164 + USBChargerDetect_IRQn = 74, // Vector168 + DAC0_IRQn = 81, // Vector184 + TSI_IRQn = 83, // Vector18C + MCG_IRQn = 84, // Vector190 + LPTMR0_IRQn = 85, // Vector194 + PINA_IRQn = 87, // Vector19C + PINB_IRQn = 88, // Vector1A0 + PINC_IRQn = 89, // Vector1A4 + PIND_IRQn = 90, // Vector1A8 + PINE_IRQn = 91, // Vector1AC + SoftInitInt_IRQn = 94, // Vector1B8 +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __FPU_PRESENT 0 +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#include "k20xx.h" + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[1]; + __IO uint32_t SCGC2; + __IO uint32_t SCGC3; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define AXBS_BASE ((uint32_t)0x40004000) // +#define DMA_BASE ((uint32_t)0x40008000) +#define FTFL_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define FCAN0_BASE ((uint32_t)0x40024000) // +#define SPI0_BASE ((uint32_t)0x4002C000) +#define SPI1_BASE ((uint32_t)0x4002D000) // +#define I2S0_BASE ((uint32_t)0x4002F000) // +#define USBDCD_BASE ((uint32_t)0x40035000) // +#define PDB_BASE ((uint32_t)0x40036000) // +#define PIT_BASE ((uint32_t)0x40037000) +#define FTM0_BASE ((uint32_t)0x40038000) +#define FTM1_BASE ((uint32_t)0x40039000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) // +#define VBAT_BASE ((uint32_t)0x4003E000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define WDOG_BASE ((uint32_t)0x40052000) +#define EWDOG_BASE ((uint32_t)0x40061000) // +#define CMT_BASE ((uint32_t)0x40062000) // +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) // +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP0_BASE ((uint32_t)0x40073000) // +#define VREF_BASE ((uint32_t)0x40074000) // +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) // +#define RCM_BASE ((uint32_t)0x4007F000) // +#define FTM2_BASE ((uint32_t)0x400B8000) // +#define ADC1_BASE ((uint32_t)0x400BB000) // +#define DAC0_BASE ((uint32_t)0x400CC000) // +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFL ((FTFL_TypeDef *) FTFL_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define FTM0 ((FTM_TypeDef *) FTM0_BASE) +#define FTM1 ((FTM_TypeDef *) FTM1_BASE) +#define FTM2 ((FTM_TypeDef *) FTM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */ +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */ +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) +#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) +#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC2 register ************/ +#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) /*!< DAC0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC3 register ************/ +#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) /*!< ADC1 Clock Gate Control */ +#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) /*!< FTM2 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ +#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ +#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ +#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ +#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC6_FCAN0 ((uint32_t)0x00000010) /*!< FlexCAN 0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) +#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) + +/****** Bits definition for SIM_CLKDIV2 register ***********/ +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) +#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) +#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + +#endif diff --git a/os/hal/ports/KINETIS/K20x/mk20d5.h b/os/common/ext/CMSIS/KINETIS/k20xx.h index aa70723..38855aa 100644 --- a/os/hal/ports/KINETIS/K20x/mk20d5.h +++ b/os/common/ext/CMSIS/KINETIS/k20xx.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Fabio Utzig, http://fabioutzig.com + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the "Software"), @@ -20,77 +20,16 @@ * SOFTWARE. */ -#ifndef _MK20D5_H_ -#define _MK20D5_H_ +#ifndef _K20xx_H_ +#define _K20xx_H_ /* * ============================================================== * ---------- Interrupt Number Definition ----------------------- * ============================================================== */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ****************/ - InitialSP_IRQn = -15, - InitialPC_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - -/****** K20x Specific Interrupt Numbers ***********************/ - DMA0_IRQn = 0, - DMA1_IRQn = 1, - DMA2_IRQn = 2, - DMA3_IRQn = 3, - DMAError_IRQn = 4, - DMA_IRQn = 5, - FlashMemComplete_IRQn = 6, - FlashMemReadCollision_IRQn = 7, - LowVoltageWarning_IRQn = 8, - LLWU_IRQn = 9, - WDOG_IRQn = 10, - I2C0_IRQn = 11, - SPI0_IRQn = 12, - I2S0_IRQn = 13, - I2S1_IRQn = 14, - UART0LON_IRQn = 15, - UART0Status_IRQn = 16, - UART0Error_IRQn = 17, - UART1Status_IRQn = 18, - UART1Error_IRQn = 19, - UART2Status_IRQn = 20, - UART2Error_IRQn = 21, - ADC0_IRQn = 22, - CMP0_IRQn = 23, - CMP1_IRQn = 24, - FTM0_IRQn = 25, - FTM1_IRQn = 26, - CMT_IRQn = 27, - RTCAlarm_IRQn = 28, - RTCSeconds_IRQn = 29, - PITChannel0_IRQn = 30, - PITChannel1_IRQn = 31, - PITChannel2_IRQn = 32, - PITChannel3_IRQn = 33, - PDB_IRQn = 34, - USB_OTG_IRQn = 35, - USBChargerDetect_IRQn = 36, - TSI_IRQn = 37, - MCG_IRQn = 38, - LowPowerTimer_IRQn = 39, - PINA_IRQn = 40, - PINB_IRQn = 41, - PINC_IRQn = 42, - PIND_IRQn = 43, - PINE_IRQn = 44, - SoftInitInt_IRQn = 45, -} IRQn_Type; + +/* Device dependent */ /* * ========================================================================== @@ -103,12 +42,12 @@ typedef enum IRQn * in @ref Library_configuration_section */ #define __MPU_PRESENT 0 -#define __FPU_PRESENT 0 #define __NVIC_PRIO_BITS 4 #define __Vendor_SysTickConfig 0 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* Device dependent typedef struct { __IO uint32_t SOPT1; @@ -136,6 +75,7 @@ typedef struct __I uint32_t UIDML; __I uint32_t UIDL; } SIM_TypeDef; +*/ typedef struct { @@ -521,73 +461,44 @@ typedef struct { __IO uint8_t USBFRMADJUST; // 0x114 } USBOTG_TypeDef; +typedef struct +{ + __IO uint8_t FSTAT; + __IO uint8_t FCNFG; + __I uint8_t FSEC; + __I uint8_t FOPT; + __IO uint8_t FCCOB3; + __IO uint8_t FCCOB2; + __IO uint8_t FCCOB1; + __IO uint8_t FCCOB0; + __IO uint8_t FCCOB7; + __IO uint8_t FCCOB6; + __IO uint8_t FCCOB5; + __IO uint8_t FCCOB4; + __IO uint8_t FCCOBB; + __IO uint8_t FCCOBA; + __IO uint8_t FCCOB9; + __IO uint8_t FCCOB8; + __IO uint8_t FPROT3; + __IO uint8_t FPROT2; + __IO uint8_t FPROT1; + __IO uint8_t FPROT0; + uint8_t RESERVED0[2]; + __IO uint8_t FEPROT; + __IO uint8_t FDPROT; +} FTFL_TypeDef; + /****************************************************************/ /* Peripheral memory map */ /****************************************************************/ -#define DMA_BASE ((uint32_t)0x40008000) -#define DMAMUX_BASE ((uint32_t)0x40021000) -#define SPI0_BASE ((uint32_t)0x4002C000) -#define PIT_BASE ((uint32_t)0x40037000) -#define FTM0_BASE ((uint32_t)0x40038000) -#define FTM1_BASE ((uint32_t)0x40039000) -#define ADC0_BASE ((uint32_t)0x4003B000) -#define LPTMR0_BASE ((uint32_t)0x40040000) -#define TSI0_BASE ((uint32_t)0x40045000) -#define SIM_BASE ((uint32_t)0x40047000) -#define PORTA_BASE ((uint32_t)0x40049000) -#define PORTB_BASE ((uint32_t)0x4004A000) -#define PORTC_BASE ((uint32_t)0x4004B000) -#define PORTD_BASE ((uint32_t)0x4004C000) -#define PORTE_BASE ((uint32_t)0x4004D000) -#define WDOG_BASE ((uint32_t)0x40052000) -#define MCG_BASE ((uint32_t)0x40064000) -#define OSC0_BASE ((uint32_t)0x40065000) -#define I2C0_BASE ((uint32_t)0x40066000) -#define UART0_BASE ((uint32_t)0x4006A000) -#define UART1_BASE ((uint32_t)0x4006B000) -#define UART2_BASE ((uint32_t)0x4006C000) -#define USBOTG_BASE ((uint32_t)0x40072000) -#define LLWU_BASE ((uint32_t)0x4007C000) -#define PMC_BASE ((uint32_t)0x4007D000) -#define GPIOA_BASE ((uint32_t)0x400FF000) -#define GPIOB_BASE ((uint32_t)0x400FF040) -#define GPIOC_BASE ((uint32_t)0x400FF080) -#define GPIOD_BASE ((uint32_t)0x400FF0C0) -#define GPIOE_BASE ((uint32_t)0x400FF100) + + /* Device dependent */ /****************************************************************/ /* Peripheral declaration */ /****************************************************************/ -#define DMA ((DMA_TypeDef *) DMA_BASE) -#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) -#define PIT ((PIT_TypeDef *) PIT_BASE) -#define FTM0 ((FTM_TypeDef *) FTM0_BASE) -#define FTM1 ((FTM_TypeDef *) FTM1_BASE) -#define ADC0 ((ADC_TypeDef *) ADC0_BASE) -#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) -#define TSI0 ((TSI_TypeDef *) TSI0_BASE) -#define SIM ((SIM_TypeDef *) SIM_BASE) -#define LLWU ((LLWU_TypeDef *) LLWU_BASE) -#define PMC ((PMC_TypeDef *) PMC_BASE) -#define PORTA ((PORT_TypeDef *) PORTA_BASE) -#define PORTB ((PORT_TypeDef *) PORTB_BASE) -#define PORTC ((PORT_TypeDef *) PORTC_BASE) -#define PORTD ((PORT_TypeDef *) PORTD_BASE) -#define PORTE ((PORT_TypeDef *) PORTE_BASE) -#define WDOG ((WDOG_TypeDef *) WDOG_BASE) -#define USBOTG ((USBOTG_TypeDef *) USBOTG_BASE) -#define MCG ((MCG_TypeDef *) MCG_BASE) -#define OSC ((OSC_TypeDef *) OSC0_BASE) -#define SPI0 ((SPI_TypeDef *) SPI0_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + + /* Device dependent */ /****************************************************************/ /* Peripheral Registers Bits Definition */ @@ -598,85 +509,8 @@ typedef struct { /* System Integration Module (SIM) */ /* */ /****************************************************************/ -/********* Bits definition for SIM_SOPT1 register *************/ -#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ -#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ -#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ -#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ -#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ -#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) -#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) - -/******* Bits definition for SIM_SOPT1CFG register ************/ -#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ -#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ -#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ - -/******* Bits definition for SIM_SOPT2 register ************/ -#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ -#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ -#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) -#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) -#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 -#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) -#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) -#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ - -/******* Bits definition for SIM_SCGC4 register ************/ -#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ -#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ -#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ -#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ -#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ -#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ -#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ -#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ -#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ - -/******* Bits definition for SIM_SCGC5 register ************/ -#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ -#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ -#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ -#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ -#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ -#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ -#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ -#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ -#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ -#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ -#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ -#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ -#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ -#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ -#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ -#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ -#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ -#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ - -/******* Bits definition for SIM_SCGC6 register ************/ -#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ - -/****** Bits definition for SIM_CLKDIV1 register ***********/ -#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 -#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) -#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) -#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 -#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) -#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) -#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 -#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) -#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) - -/****** Bits definition for SIM_CLKDIV2 register ***********/ -#define SIM_CLKDIV2_USBDIV_SHIFT 1 -#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) -#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) -#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + + /* Device dependent */ /****************************************************************/ /* */ @@ -1742,19 +1576,19 @@ typedef struct { /* MCR Bit Fields */ #define PIT_MCR_FRZ 0x1u #define PIT_MCR_MDIS 0x2u -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) -/* CVAL Bit Fields */ -#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu -#define PIT_CVAL_TVL_SHIFT 0 -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) -/* TCTRL Bit Fields */ -#define PIT_TCTRL_TEN 0x1u -#define PIT_TCTRL_TIE 0x2u -/* TFLG Bit Fields */ -#define PIT_TFLG_TIF 0x1u +/* LDVALn Bit Fields */ +#define PIT_LDVALn_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVALn_TSV_SHIFT 0 +#define PIT_LDVALn_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) +/* CVALn Bit Fields */ +#define PIT_CVALn_TVL_MASK 0xFFFFFFFFu +#define PIT_CVALn_TVL_SHIFT 0 +#define PIT_CVALn_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) +/* TCTRLn Bit Fields */ +#define PIT_TCTRLn_TEN 0x1u +#define PIT_TCTRLn_TIE 0x2u +/* TFLGn Bit Fields */ +#define PIT_TFLGn_TIF 0x1u /****************************************************************/ /* */ @@ -2175,7 +2009,9 @@ typedef struct { #define UARTx_BDH_SBR(x) ((uint8_t)((uint8_t)(x) & UARTx_BDH_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ /********* Bits definition for UARTx_BDL register *************/ -#define UARTx_BDL_SBR_MASK ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) /********* Bits definition for UARTx_C1 register **************/ #define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ @@ -2330,6 +2166,42 @@ typedef struct { /* USB OTG */ /* */ /****************************************************************/ + +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IEHOST ((uint8_t)0x01) /*!< Host mode operation? */ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPHIGH ((uint8_t)0x80) /*!< D+ Data Line pullup resistor enable */ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + /******** Bits definition for USBx_ISTAT register *************/ #define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ #define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ @@ -2340,6 +2212,16 @@ typedef struct { #define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ #define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ +#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ +#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ +#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ +#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ +#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ +#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ + /******** Bits definition for USBx_ERRSTAT register ***********/ #define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ #define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ @@ -2349,6 +2231,14 @@ typedef struct { #define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ #define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ +/******** Bits definition for USBx_STAT register *************/ +#define USBx_STAT_ENDP_MASK ((uint8_t)0xF0) /*!< Endpoint address mask*/ +#define USBx_STAT_ENDP_SHIFT ((uint8_t)0x04) /*!< Endpoint address shift*/ +#define USBx_STAT_TX_MASK ((uint8_t)0x08) /*!< Transmit indicator mask*/ +#define USBx_STAT_TX_SHIFT ((uint8_t)0x03) /*!< Transmit indicator shift*/ +#define USBx_STAT_ODD_MASK ((uint8_t)0x04) /*!< EVEN/ODD bank indicator mask*/ +#define USBx_STAT_ODD_SHIFT ((uint8_t)0x02) /*!< EVEN/ODD bank indicator shift */ + /******** Bits definition for USBx_CTL register *****************/ #define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ #define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ @@ -2359,15 +2249,10 @@ typedef struct { #define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ #define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ -/******** Bits definition for USBx_INTEN register ***************/ -#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ -#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ -#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ -#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ -#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ -#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ -#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ -#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ +#define USBx_ADDR_ADDR_SHIFT 0 /*!< USB Address */ +#define USBx_ADDR_ADDR_MASK ((uint8_t)0x7F) /*!< USB Address */ /******** Bits definition for USBx_ENDPTn register **************/ #define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) @@ -2378,9 +2263,17 @@ typedef struct { #define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ #define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ -/******** Bits definition for USBx_CTRL register ****************/ -#define USBx_CTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ -#define USBx_CTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ +/******** Bits definition for USBx_USBCTRL register *************/ +#define USBx_USBCTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ +#define USBx_USBCTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ + +/******** Bits definition for USBx_OBSERVE register *************/ +#define USBx_OBSERVE_DPPU ((uint8_t)0x80) /*!< Provides observability of the D+ Pullup . signal output from the USB OTG module */ +#define USBx_OBSERVE_DPPD ((uint8_t)0x40) /*!< Provides observability of the D+ Pulldown . signal output from the USB OTG module */ +#define USBx_OBSERVE_DMPD ((uint8_t)0x10) /*!< Provides observability of the D- Pulldown signal output from the USB OTG module */ + +/******** Bits definition for USBx_CONTROL register *************/ +#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ /******** Bits definition for USBx_USBTRC0 register *************/ #define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ @@ -2388,7 +2281,39 @@ typedef struct { #define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ #define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ -/******** Bits definition for USBx_CONTROL register *************/ -#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFL) */ +/* */ +/****************************************************************/ +/********** Bits definition for FTFL_FSTAT register ***********/ +#define FTFL_FSTAT_CCIF ((uint8_t)0x80) /*!< Command Complete Interrupt Flag */ +#define FTFL_FSTAT_RDCOLERR ((uint8_t)0x40) /*!< Flash Read Collision Error Flag */ +#define FTFL_FSTAT_ACCERR ((uint8_t)0x20) /*!< Flash Access Error Flag */ +#define FTFL_FSTAT_FPVIOL ((uint8_t)0x10) /*!< Flash Protection Violation Flag */ +#define FTFL_FSTAT_MGSTAT0 ((uint8_t)0x01) /*!< Memory Controller Command Completion Status Flag */ + +/********** Bits definition for FTFL_FCNFG register ***********/ +#define FTFL_FCNFG_CCIE ((uint8_t)0x80) /*!< Command Complete Interrupt Enable */ +#define FTFL_FCNFG_RDCOLLIE ((uint8_t)0x40) /*!< Read Collision Error Interrupt Enable */ +#define FTFL_FCNFG_ERSAREQ ((uint8_t)0x20) /*!< Erase All Request */ +#define FTFL_FCNFG_ERSSUSP ((uint8_t)0x10) /*!< Erase Suspend */ +#define FTFL_FCNFG_PFLSH ((uint8_t)0x04) /*!< Flash memory configuration */ +#define FTFL_FCNFG_RAMRDY ((uint8_t)0x02) /*!< RAM Ready */ +#define FTFL_FCNFG_EEERDY ((uint8_t)0x01) /*!< EEPROM backup data has been copied to the FlexRAM and is therefore available for read access */ + +/********** Bits definition for FTFL_FSEC register ************/ +#define FTFL_FSEC_KEYEN_MASK ((uint8_t)0xC0) /*!< Backdoor Key Security Enable */ +#define FTFL_FSEC_MEEN_MASK ((uint8_t)0x30) /*!< Mass Erase Enable Bits */ +#define FTFL_FSEC_FSLACC_MASK ((uint8_t)0x0C) /*!< Freescale Failure Analysis Access Code */ +#define FTFL_FSEC_SEC_MASK ((uint8_t)0x03) /*!< Flash Security */ +#define FTFL_FSEC_KEYEN_ENABLED ((uint8_t)0x80) +#define FTFL_FSEC_MEEN_DISABLED ((uint8_t)0x20) +#define FTFL_FSEC_SEC_UNSECURE ((uint8_t)0x02) + +/********** Bits definition for FTFL_FOPT register ************/ +#define FTFL_FOPT_NMI_DIS ((uint8_t)0x04) /*!< Enables/disables control for the NMI function */ +#define FTFL_FOPT_EZPORT_DIS ((uint8_t)0x02) /*!< EzPort operation */ +#define FTFL_FOPT_LPBOOT ((uint8_t)0x01) /*!< Normal/low-power boot*/ #endif diff --git a/os/hal/ports/KINETIS/KL2x/kl25z.h b/os/common/ext/CMSIS/KINETIS/kl25z.h index 4e9547f..bf519ab 100644 --- a/os/hal/ports/KINETIS/KL2x/kl25z.h +++ b/os/common/ext/CMSIS/KINETIS/kl25z.h @@ -23,6 +23,15 @@ #ifndef _KL25Z_H_ #define _KL25Z_H_ +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + /* * ============================================================== * ---------- Interrupt Number Definition ----------------------- @@ -73,77 +82,14 @@ typedef enum IRQn PIND_IRQn = 31, } IRQn_Type; +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + /* * ========================================================================== * ----------- Processor and Core Peripheral Section ------------------------ * ========================================================================== */ -/** - * @brief KL2x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __MPU_PRESENT 0 -#define __VTOR_PRESENT 1 -#define __NVIC_PRIO_BITS 2 -#define __Vendor_SysTickConfig 0 - -#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ - -typedef struct -{ - __IO uint32_t SOPT1; - __IO uint32_t SOPT1CFG; - uint32_t RESERVED0[1023]; - __IO uint32_t SOPT2; - __I uint32_t RESERVED1[1]; - __IO uint32_t SOPT4; - __IO uint32_t SOPT5; - uint32_t RESERVED2[1]; - __IO uint32_t SOPT7; - uint32_t RESERVED3[2]; - __IO uint32_t SDID; - uint32_t RESERVED4[3]; - __IO uint32_t SCGC4; - __IO uint32_t SCGC5; - __IO uint32_t SCGC6; - __IO uint32_t SCGC7; - __IO uint32_t CLKDIV1; - uint32_t RESERVED5[1]; - __IO uint32_t FCFG1; - __IO uint32_t FCFG2; - uint32_t RESERVED6[1]; - __IO uint32_t UIDMH; - __IO uint32_t UIDML; - __IO uint32_t UIDL; - uint32_t RESERVED7[39]; - __IO uint32_t COPC; - __IO uint32_t SRVCOP; -} SIM_TypeDef; - -typedef struct -{ - __IO uint8_t PE1; - __IO uint8_t PE2; - __IO uint8_t PE3; - __IO uint8_t PE4; - __IO uint8_t ME; - __IO uint8_t F1; - __IO uint8_t F2; - __I uint8_t F3; - __IO uint8_t FILT1; - __IO uint8_t FILT2; -} LLWU_TypeDef; - -typedef struct -{ - __IO uint32_t PCR[32]; - __IO uint32_t GPCLR; - __IO uint32_t GPCHR; - uint32_t RESERVED0[6]; - __IO uint32_t ISFR; -} PORT_TypeDef; - typedef struct { __IO uint8_t C1; @@ -152,7 +98,7 @@ typedef struct __IO uint8_t C4; __IO uint8_t C5; __IO uint8_t C6; - __IO uint8_t S; + __I uint8_t S; uint8_t RESERVED0[1]; __IO uint8_t SC; uint8_t RESERVED1[1]; @@ -166,29 +112,6 @@ typedef struct typedef struct { - __IO uint8_t CR; -} OSC_TypeDef; - -typedef struct -{ - __IO uint32_t SAR; - __IO uint32_t DAR; - __IO uint32_t DSR_BCR; - __IO uint32_t DCR; -} DMAChannel_TypeDef; - -typedef struct -{ - DMAChannel_TypeDef ch[4]; -} DMA_TypeDef; - -typedef struct -{ - __IO uint8_t CHCFG[4]; -} DMAMUX_TypeDef; - -typedef struct -{ __IO uint32_t SC; __IO uint32_t CNT; __IO uint32_t MOD; @@ -204,46 +127,6 @@ typedef struct typedef struct { - __IO uint32_t SC1A; // ADC Status and Control Registers 1 - __IO uint32_t SC1B; // ADC Status and Control Registers 1 - __IO uint32_t CFG1; // ADC Configuration Register 1 - __IO uint32_t CFG2; // ADC Configuration Register 2 - __I uint32_t RA; // ADC Data Result Register - __I uint32_t RB; // ADC Data Result Register - __IO uint32_t CV1; // Compare Value Registers - __IO uint32_t CV2; // Compare Value Registers - __IO uint32_t SC2; // Status and Control Register 2 - __IO uint32_t SC3; // Status and Control Register 3 - __IO uint32_t OFS; // ADC Offset Correction Register - __IO uint32_t PG; // ADC Plus-Side Gain Register - __IO uint32_t MG; // ADC Minus-Side Gain Register - __IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register - __IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register - uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register - __IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t PSR; - __IO uint32_t CMR; - __I uint32_t CNR; -} LPTMR_TypeDef; - -typedef struct -{ __IO uint32_t GENCS; __IO uint32_t DATA; __IO uint32_t TSHD; @@ -251,16 +134,6 @@ typedef struct typedef struct { - __IO uint32_t PDOR; - __IO uint32_t PSOR; - __IO uint32_t PCOR; - __IO uint32_t PTOR; - __IO uint32_t PDIR; - __IO uint32_t PDDR; -} GPIO_TypeDef; - -typedef struct -{ __IO uint8_t C1; __IO uint8_t C2; __IO uint8_t BR; @@ -293,7 +166,7 @@ typedef struct __IO uint8_t BDL; __IO uint8_t C1; __IO uint8_t C2; - __IO uint8_t S1; + __I uint8_t S1; __IO uint8_t S2; __IO uint8_t C3; __IO uint8_t D; @@ -316,22 +189,88 @@ typedef struct __IO uint8_t C5; } UARTLP_TypeDef; +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + typedef struct { - __IO uint8_t LVDSC1; - __IO uint8_t LVDSC2; - __IO uint8_t REGSC; -} PMC_TypeDef; + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; +} RCM_TypeDef; /****************************************************************/ /* Peripheral memory map */ /****************************************************************/ #define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) #define DMAMUX_BASE ((uint32_t)0x40021000) +#define PIT_BASE ((uint32_t)0x40037000) #define TPM0_BASE ((uint32_t)0x40038000) #define TPM1_BASE ((uint32_t)0x40039000) #define TPM2_BASE ((uint32_t)0x4003A000) #define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) #define LPTMR0_BASE ((uint32_t)0x40040000) #define TSI0_BASE ((uint32_t)0x40045000) #define SIM_BASE ((uint32_t)0x40047000) @@ -347,25 +286,34 @@ typedef struct #define UART0_BASE ((uint32_t)0x4006A000) #define UART1_BASE ((uint32_t)0x4006B000) #define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) #define SPI0_BASE ((uint32_t)0x40076000) #define SPI1_BASE ((uint32_t)0x40077000) #define LLWU_BASE ((uint32_t)0x4007C000) #define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) #define GPIOA_BASE ((uint32_t)0x400FF000) #define GPIOB_BASE ((uint32_t)0x400FF040) #define GPIOC_BASE ((uint32_t)0x400FF080) #define GPIOD_BASE ((uint32_t)0x400FF0C0) #define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) /****************************************************************/ /* Peripheral declaration */ /****************************************************************/ #define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) #define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) #define TPM0 ((TPM_TypeDef *) TPM0_BASE) #define TPM1 ((TPM_TypeDef *) TPM1_BASE) #define TPM2 ((TPM_TypeDef *) TPM2_BASE) #define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) #define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) #define TSI0 ((TSI_TypeDef *) TSI0_BASE) #define SIM ((SIM_TypeDef *) SIM_BASE) @@ -376,6 +324,8 @@ typedef struct #define PORTC ((PORT_TypeDef *) PORTC_BASE) #define PORTD ((PORT_TypeDef *) PORTD_BASE) #define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) #define MCG ((MCG_TypeDef *) MCG_BASE) #define OSC0 ((OSC_TypeDef *) OSC0_BASE) #define SPI0 ((SPI_TypeDef *) SPI0_BASE) @@ -385,11 +335,14 @@ typedef struct #define UART0 ((UARTLP_TypeDef *) UART0_BASE) #define UART1 ((UART_TypeDef *) UART1_BASE) #define UART2 ((UART_TypeDef *) UART2_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) /****************************************************************/ /* Peripheral Registers Bits Definition */ @@ -427,6 +380,49 @@ typedef struct #define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ #define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC ((uint32_t)0x00040000) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_UART1ODE ((uint32_t)0x00020000) /*!< UART1 Open Drain Enable */ +#define SIM_SOPT5_UART0ODE ((uint32_t)0x00010000) /*!< UART0 Open Drain Enable */ +#define SIM_SOPT5_UART1RXSRC ((uint32_t)0x00000040) /*!< UART1 receive data source select */ +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 /*!< UART1 transmit data source select (shift) */ +#define SIM_SOPT5_UART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART1TXSRC_SHIFT)) /*!< UART1 transmit data source select (mask) */ +#define SIM_SOPT5_UART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART1TXSRC_SHIFT) & SIM_SOPT5_UART1TXSRC_MASK)) /*!< UART1 transmit data source select */ +#define SIM_SOPT5_UART0RXSRC ((uint32_t)0x00000040) /*!< UART0 receive data source select */ +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 /*!< UART0 transmit data source select (shift) */ +#define SIM_SOPT5_UART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART0TXSRC_SHIFT)) /*!< UART0 transmit data source select (mask) */ +#define SIM_SOPT5_UART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART0TXSRC_SHIFT) & SIM_SOPT5_UART0TXSRC_MASK)) /*!< UART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_DIEID_SHIFT 7 /*!< Device die number (shift) */ +#define SIM_SDID_DIEID_MASK ((uint32_t)((uint32_t)0x1F << SIM_SDID_DIEID_SHIFT)) /*!< Device die number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + /******* Bits definition for SIM_SCGC4 register ************/ #define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ #define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ @@ -456,9 +452,9 @@ typedef struct #define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ #define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ #define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ -#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ -/******* Bits definition for SIM_SCGC6 register ************/ +/******* Bits definition for SIM_SCGC7 register ************/ #define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ /****** Bits definition for SIM_CLKDIV1 register ***********/ @@ -469,313 +465,100 @@ typedef struct #define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ #define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address block (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address block (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + /****************************************************************/ /* */ /* Low-Leakage Wakeup Unit (LLWU) */ /* */ /****************************************************************/ -/********** Bits definition for LLWU_PE1 register *************/ -#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ -#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ -#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ -#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ -#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ -#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ -#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ -#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ -#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ -#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ -#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ -#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ - -/********** Bits definition for LLWU_PE2 register *************/ -#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ -#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ -#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ -#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ -#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ -#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ -#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ -#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ -#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ -#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ -#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ -#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ - -/********** Bits definition for LLWU_PE3 register *************/ -#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ -#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ -#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ -#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ -#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ -#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ -#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ -#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ -#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ -#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ -#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ -#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ - -/********** Bits definition for LLWU_PE4 register *************/ -#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ -#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ -#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ -#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ -#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ -#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ -#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ -#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ -#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ -#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ -#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ -#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ - -/********** Bits definition for LLWU_ME register *************/ -#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ -#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ -#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ -#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ -#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ -#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ -#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ -#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ - -/********** Bits definition for LLWU_F1 register *************/ -#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ -#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ -#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ -#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ -#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ -#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ -#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ -#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ - -/********** Bits definition for LLWU_F2 register *************/ -#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ -#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ -#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ -#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ -#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ -#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ -#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ -#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ - -/********** Bits definition for LLWU_F3 register *************/ -#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ -#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ -#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ -#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ -#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ -#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ -#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ -#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ - -/********** Bits definition for LLWU_FILT1 register *************/ -#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ - -/********** Bits definition for LLWU_FILT2 register *************/ -#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ -#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ -#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ -#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ -#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ -#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ -#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ -#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ -#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ -#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ -#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/* Device independent */ /****************************************************************/ /* */ /* Port Control and interrupts (PORT) */ /* */ /****************************************************************/ -/******** Bits definition for PORTx_PCRn register *************/ -#define PORTx_PCRn_ISR ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ -#define PORTx_PCRn_IRQC_SHIFT 16 -#define PORTx_PCRn_IRQC_MASK ((uint32_t)0x000F0000) /*!< Interrupt Configuration */ -#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) -#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ -#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */ -#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ -#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ -#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ -#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ -#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ -#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/* Device independent */ /****************************************************************/ /* */ /* Oscillator (OSC) */ /* */ /****************************************************************/ -/*********** Bits definition for OSC_CR register **************/ -#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ -#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ -#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ -#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ -#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ -#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/* Device independent */ /****************************************************************/ /* */ /* Direct Memory Access (DMA) */ /* */ /****************************************************************/ -/*********** Bits definition for DMA_BCRn register ************/ -#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */ -#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */ -#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */ -#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */ -#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */ -#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */ -#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */ -#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */ -#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */ - -/*********** Bits definition for DMA_DCRn register ************/ -#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */ -#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */ -#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */ -#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */ -#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */ -#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */ -#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */ -#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */ -#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */ -#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */ -#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */ -#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */ -#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */ -#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */ -#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */ -#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */ -#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */ -#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */ -#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */ -#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */ -#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */ -#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */ -#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */ -#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */ -#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */ -#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */ -#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */ -#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */ -#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */ -#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */ + +/* Device independent */ /****************************************************************/ /* */ /* Direct Memory Access Multiplexer (DMAMUX) */ /* */ /****************************************************************/ -/******** Bits definition for DMAMUX_CHCFGn register **********/ -#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ -#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ -#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ -#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ -#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ /****************************************************************/ /* */ /* Analog-to-Digital Converter (ADC) */ /* */ /****************************************************************/ -/*********** Bits definition for ADCx_SC1n register ***********/ -#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ -#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ -#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ -#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ -#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ -#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ - -/*********** Bits definition for ADCx_CFG1 register ***********/ -#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ -#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ -#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ -#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ -#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ -#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ -#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ -#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ -#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ -#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ -#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ - -/*********** Bits definition for ADCx_CFG2 register ***********/ -#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ -#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ -#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ -#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ -#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ -#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ - -/*********** Bits definition for ADCx_SC2 register ***********/ -#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ -#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ -#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ -#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ -#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ -#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ -#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ -#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ -#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ - -/*********** Bits definition for ADCx_SC3 register ***********/ -#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ -#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ -#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ -#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ -#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ -#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ -#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/* Device independent */ /****************************************************************/ /* */ /* Low-Power Timer (LPTMR) */ /* */ /****************************************************************/ -/********** Bits definition for LPTMRx_CSR register ***********/ -#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ -#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ -#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ -#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ -#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ -#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ -#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ -#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ -#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ - -/********** Bits definition for LPTMRx_PSR register ***********/ -#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ -#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ -#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ -#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ -#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ -#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ -#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ - -/********** Bits definition for LPTMRx_CMR register ***********/ -#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ -#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ -#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ - -/********** Bits definition for LPTMRx_CNR register ***********/ -#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ -#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ -#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/* Device independent */ /****************************************************************/ /* */ @@ -969,10 +752,12 @@ typedef struct #define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ /*********** Bits definition for SPIx_BR register *************/ -#define SPIx_BR_SPPR ((uint8_t)0x70) /*!< SPI Baud rate Prescaler Divisor */ -#define SPIx_BR_SPR ((uint8_t)0x0F) /*!< SPI Baud rate Divisor */ - -#define SPIx_BR_SPPR_SHIFT 4 +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) /*********** Bits definition for SPIx_S register **************/ #define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ @@ -981,10 +766,14 @@ typedef struct #define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ /*********** Bits definition for SPIx_D register **************/ -#define SPIx_D_DATA ((uint8_t)0xFF) /*!< Data */ +#define SPIx_D_DATA_SHIFT 0 /*!< Data */ +#define SPIx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_D_DATA_SHIFT)) +#define SPIx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_D_DATA_SHIFT) & SPIx_D_DATA_MASK)) /*********** Bits definition for SPIx_M register **************/ -#define SPIx_M_DATA ((uint8_t)0xFF) /*!< SPI HW Compare value for Match */ +#define SPIx_M_DATA_SHIFT 0 /*!< SPI HW Compare value for Match */ +#define SPIx_M_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_M_DATA_SHIFT)) +#define SPIx_M_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_M_DATA_SHIFT) & SPIx_M_DATA_MASK)) /****************************************************************/ /* */ @@ -992,15 +781,17 @@ typedef struct /* */ /****************************************************************/ /*********** Bits definition for I2Cx_A1 register *************/ -#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ - -#define I2Cx_A1_AD_SHIT 1 +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) /*********** Bits definition for I2Cx_F register **************/ -#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ -#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ - -#define I2Cx_F_MULT_SHIFT 5 +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) /*********** Bits definition for I2Cx_C1 register *************/ #define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ @@ -1023,7 +814,9 @@ typedef struct #define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ /*********** Bits definition for I2Cx_D register **************/ -#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) /*********** Bits definition for I2Cx_C2 register *************/ #define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ @@ -1031,18 +824,22 @@ typedef struct #define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ #define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ #define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ -#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) /*********** Bits definition for I2Cx_FLT register ************/ #define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ #define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ #define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ -#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) /*********** Bits definition for I2Cx_RA register *************/ -#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ - -#define I2Cx_RA_RAD_SHIFT 1 +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) /*********** Bits definition for I2Cx_SMB register ************/ #define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ @@ -1055,15 +852,19 @@ typedef struct #define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ /*********** Bits definition for I2Cx_A2 register *************/ -#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ - -#define I2Cx_A2_SAD_SHIFT 1 +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) /*********** Bits definition for I2Cx_SLTH register ***********/ -#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) /*********** Bits definition for I2Cx_SLTL register ***********/ -#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) /****************************************************************/ /* */ @@ -1074,10 +875,14 @@ typedef struct #define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ #define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ #define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ -#define UARTx_BDH_SBR ((uint8_t)0x1F) /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) /********* Bits definition for UARTx_BDL register *************/ -#define UARTx_BDL_SBR ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) /********* Bits definition for UARTx_C1 register **************/ #define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ @@ -1141,50 +946,233 @@ typedef struct #define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ #define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ #define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) /********* Bits definition for UARTx_MA1 register *************/ -#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) /********* Bits definition for UARTx_MA2 register *************/ -#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) /********* Bits definition for UARTx_C4 register **************/ -#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ #define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ +#define UARTx_C4_RDMAS ((uint8_t)0x20) /*!< Receiver Full DMA Select */ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ #define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ #define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ -#define UARTx_C4_RDMAS ((uint8_t)0x80) /*!< Receiver Full DMA Select */ -#define UARTx_C4_OSR ((uint8_t)0x1F) /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) /********* Bits definition for UARTx_C5 register **************/ #define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ #define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ #define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ #define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + /****************************************************************/ /* */ /* Power Management Controller (PMC) */ /* */ /****************************************************************/ -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ -#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ -#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ -#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ -#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) -/********* Bits definition for PMC_LVDSC1 register *************/ -#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ -#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ -#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ -#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ -#define PMC_LVDSC2_LVWV_SHIFT 0 -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) -/********* Bits definition for PMC_REGSC register *************/ -#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ -#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ -#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ -#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ - -#endif + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +#define TPMx_SC_CMOD_DISABLE TPMx_SC_CMOD(0) +#define TPMx_SC_CMOD_LPTPM_CLK TPMx_SC_CMOD(1) +#define TPMx_SC_CMOD_LPTPM_EXTCLK TPMx_SC_CMOD(2) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +#define TPMx_CONF_DBGMODE_CONT TPMx_CONF_DBGMODE(3) +#define TPMx_CONF_DBGMODE_PAUSE TPMx_CONF_DBGMODE(0) + +/****************************************************************/ +/* */ +/* USB OTG: device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ + +/******** Bits definition for USBx_TOKEN register ***************/ +#define USBx_TOKEN_TOKENPID_SHIFT 4 /*!< Contains the token type executed by the USB module. */ +#define USBx_TOKEN_TOKENPID_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENPID_SHIFT)) +#define USBx_TOKEN_TOKENPID(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENPID_SHIFT) & USBx_TOKEN_TOKENPID_MASK)) +#define USBx_TOKEN_TOKENENDPT_SHIFT 0 /*!< Holds the Endpoint address for the token command. */ +#define USBx_TOKEN_TOKENENDPT_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENENDPT_SHIFT)) +#define USBx_TOKEN_TOKENENDPT(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENENDPT_SHIFT) & USBx_TOKEN_TOKENENDPT_MASK)) +#define USBx_TOKEN_TOKENPID_OUT 0x1 +#define USBx_TOKEN_TOKENPID_IN 0x9 +#define USBx_TOKEN_TOKENPID_SETUP 0xD + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ + +/* Only device independent parts */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 2 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x01 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0 +#define DACx_C1_DACBFMD_MODE_OTS 1 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +#endif /* _KL25Z_H_ */ diff --git a/os/common/ext/CMSIS/KINETIS/kl26z.h b/os/common/ext/CMSIS/KINETIS/kl26z.h new file mode 100644 index 0000000..2c63f12 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/kl26z.h @@ -0,0 +1,1247 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL26Z_H_ +#define _KL26Z_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + I2S0_IRQn = 23, + USB_OTG_IRQn = 24, + DAC0_IRQn = 25, + TSI0_IRQn = 26, + MCG_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved2_IRQn = 29, + PINA_IRQn = 30, + PINCD_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __I uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; + __IO uint8_t C9; + __IO uint8_t C10; +} MCG_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[12]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S1; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t C4; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UARTLP_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; +} RCM_TypeDef; + +typedef struct { + __IO uint32_t TCSR; // 0x00 + uint32_t RESERVED0[1]; + __IO uint32_t TCR2; // 0x08 + __IO uint32_t TCR3; // 0x0C + __IO uint32_t TCR4; // 0x10 + __IO uint32_t TCR5; // 0x14 + uint32_t RESERVED1[2]; + __O uint32_t TDR0; // 0x20 + uint32_t RESERVED2[15]; + __IO uint32_t TMR; // 0x60 + uint32_t RESERVED3[7]; + __IO uint32_t RCSR; // 0x80 + uint32_t RESERVED4[1]; + __IO uint32_t RCR2; // 0x88 + __IO uint32_t RCR3; // 0x8C + __IO uint32_t RCR4; // 0x90 + __IO uint32_t RCR5; // 0x94 + uint32_t RESERVED5[2]; + __I uint32_t RDR0; // 0xA0 + uint32_t RESERVED6[15]; + __IO uint32_t RMR; // 0xE0 + uint32_t RESERVED7[7]; + __IO uint32_t MCR; // 0x100 +} I2S_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define I2S0_BASE ((uint32_t)0x4002F000) // TODO: registers not implemented +#define PIT_BASE ((uint32_t)0x40037000) +#define TPM0_BASE ((uint32_t)0x40038000) +#define TPM1_BASE ((uint32_t)0x40039000) +#define TPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define I2S0 ((I2S_TypeDef *) I2S0_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) TPM0_BASE) +#define TPM1 ((TPM_TypeDef *) TPM1_BASE) +#define TPM2 ((TPM_TypeDef *) TPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UARTLP_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */ +#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */ +#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_UART1ODE ((uint32_t)0x00020000) /*!< UART1 Open Drain Enable */ +#define SIM_SOPT5_UART0ODE ((uint32_t)0x00010000) /*!< UART0 Open Drain Enable */ +#define SIM_SOPT5_UART1RXSRC ((uint32_t)0x00000040) /*!< UART1 receive data source select */ +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 /*!< UART1 transmit data source select (shift) */ +#define SIM_SOPT5_UART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART1TXSRC_SHIFT)) /*!< UART1 transmit data source select (mask) */ +#define SIM_SOPT5_UART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART1TXSRC_SHIFT) & SIM_SOPT5_UART1TXSRC_MASK)) /*!< UART1 transmit data source select */ +#define SIM_SOPT5_UART0RXSRC ((uint32_t)0x00000040) /*!< UART0 receive data source select */ +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 /*!< UART0 transmit data source select (shift) */ +#define SIM_SOPT5_UART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART0TXSRC_SHIFT)) /*!< UART0 transmit data source select (mask) */ +#define SIM_SOPT5_UART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART0TXSRC_SHIFT) & SIM_SOPT5_UART0TXSRC_MASK)) /*!< UART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_DIEID_SHIFT 7 /*!< Device die number (shift) */ +#define SIM_SDID_DIEID_MASK ((uint32_t)((uint32_t)0x1F << SIM_SDID_DIEID_SHIFT)) /*!< Device die number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< I2S0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_FCFTRIM ((uint8_t)((uint8_t)1 << 6)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C3 register **************/ +#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */ +#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */ +#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */ +#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */ + +/*********** Bits definition for MCG_ATCVH register ************/ +#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */ +#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */ +#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */ + +/*********** Bits definition for MCG_ATCVL register ************/ +#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */ +#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */ +#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */ + +/************ Bits definition for MCG_C7 register **************/ +#define MCG_C7_OSCSEL ((uint8_t)((uint8_t)1 << 0) + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */ + +/************ Bits definition for MCG_C9 register **************/ +/* All MCG_C9 bits are reserved on the KL26Z. */ + +/************ Bits definition for MCG_C10 register *************/ +/* All MCG_C10 bits are reserved on the KL26Z. */ + + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S1 register *************/ +#define I2Cx_S1_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S1_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S1_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S1_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S1_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S1_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S1_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S1_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ +#define UARTx_C4_RDMAS ((uint8_t)0x20) /*!< Receiver Full DMA Select */ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +#define TPMx_SC_CMOD_DISABLE TPMx_SC_CMOD(0) +#define TPMx_SC_CMOD_LPTPM_CLK TPMx_SC_CMOD(1) +#define TPMx_SC_CMOD_LPTPM_EXTCLK TPMx_SC_CMOD(2) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USB OTG: device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ + +/******** Bits definition for USBx_TOKEN register ***************/ +#define USBx_TOKEN_TOKENPID_SHIFT 4 /*!< Contains the token type executed by the USB module. */ +#define USBx_TOKEN_TOKENPID_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENPID_SHIFT)) +#define USBx_TOKEN_TOKENPID(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENPID_SHIFT) & USBx_TOKEN_TOKENPID_MASK)) +#define USBx_TOKEN_TOKENENDPT_SHIFT 0 /*!< Holds the Endpoint address for the token command. */ +#define USBx_TOKEN_TOKENENDPT_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENENDPT_SHIFT)) +#define USBx_TOKEN_TOKENENDPT(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENENDPT_SHIFT) & USBx_TOKEN_TOKENENDPT_MASK)) +#define USBx_TOKEN_TOKENPID_OUT 0x1 +#define USBx_TOKEN_TOKENPID_IN 0x9 +#define USBx_TOKEN_TOKENPID_SETUP 0xD + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ + +/* Only device independent parts */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 2 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x01 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0 +#define DACx_C1_DACBFMD_MODE_OTS 1 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +#endif /* _KL26Z_H_ */ diff --git a/os/common/ext/CMSIS/KINETIS/kl27zxx.h b/os/common/ext/CMSIS/KINETIS/kl27zxx.h new file mode 100644 index 0000000..2a64906 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/kl27zxx.h @@ -0,0 +1,1307 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL27ZXX_H_ +#define _KL27ZXX_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + LPUART0_IRQn = 12, + LPUART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + Reserved1_IRQn = 23, + USB_IRQn = 24, + Reserved5_IRQn = 25, + Reserved2_IRQn = 26, + Reserved3_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved4_IRQn = 29, + PINA_IRQn = 30, + PINBCDE_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + uint8_t RESERVED0[4]; + __I uint8_t S; + uint8_t RESERVED1[1]; + __IO uint8_t SC; + uint8_t RESERVED2[15]; + __IO uint8_t MC; +} MCGLite_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[7]; + __IO uint32_t POL; + uint32_t RESERVED2[4]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; + __IO uint8_t S2; +} I2C_TypeDef; + +typedef struct +{ + __IO uint32_t BAUD; + __IO uint32_t STAT; + __IO uint32_t CTRL; + __IO uint32_t DATA; + __IO uint32_t MATCH; +} LPUART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UART_TypeDef; + +typedef struct +{ + __I uint32_t VERID; + __I uint32_t PARAM; + __IO uint32_t CTRL; + uint32_t RESERVED0[1]; + __IO uint32_t SHIFTSTAT; + __IO uint32_t SHIFTERR; + __IO uint32_t TIMSTAT; + uint32_t RESERVED1[1]; + __IO uint32_t SHIFTSIEN; + __IO uint32_t SHIFTEIEN; + __IO uint32_t TIMIEN; + uint32_t RESERVED2[1]; + __IO uint32_t SHIFTSDEN; + uint32_t RESERVED3[19]; + __IO uint32_t SHIFTCTL[4]; + uint32_t RESERVED4[28]; + __IO uint32_t SHIFTCFG[4]; + uint32_t RESERVED5[60]; + __IO uint32_t SHIFTBUF[4]; + uint32_t RESERVED6[28]; + __IO uint32_t SHIFTBUFBIS[4]; + uint32_t RESERVED7[28]; + __IO uint32_t SHIFTBUFBYS[4]; + uint32_t RESERVED8[28]; + __IO uint32_t SHIFTBUFBBS[4]; + uint32_t RESERVED9[28]; + __IO uint32_t TIMCTL[4]; + uint32_t RESERVED10[28]; + __IO uint32_t TIMCFG[4]; + uint32_t RESERVED11[28]; + __IO uint32_t TIMCMP[4]; +} FlexIO_TypeDef; + +typedef struct +{ + __IO uint8_t TRM; + __IO uint8_t SC; +} VREF_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED7[115]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[11]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 + uint8_t RESERVED26[15]; + __IO uint8_t KEEP_ALIVE_CTRL; // 0x124 + uint8_t RESERVED30[3]; + __IO uint8_t KEEP_ALIVE_WKCTRL; // 0x128 + uint8_t RESERVED31[23] + __IO uint8_t CLK_RECOVER_CTRL; // 0x140 + uint8_t RESERVED27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; // 0x144 + uint8_t RESERVED28[15]; + __IO uint8_t CLK_RECOVER_INT_EN; // 0x154 + uint8_t RESERVED29[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; // 0x15c +} USBFS_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; + __IO uint8_t FM; + __IO uint8_t MR; + __IO uint8_t SSRS0; + __IO uint8_t SSRS1; +} RCM_TypeDef; + +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t GPOLY; + __IO uint32_t CTRL; +} CRC_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define CRC_BASE ((uint32_t)0x40032000) +#define PIT_BASE ((uint32_t)0x40037000) +#define LPTPM0_BASE ((uint32_t)0x40038000) +#define LPTPM1_BASE ((uint32_t)0x40039000) +#define LPTPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define LPUART0_BASE ((uint32_t)0x40054000) +#define LPUART1_BASE ((uint32_t)0x40055000) +#define FLEXIO_BASE ((uint32_t)0x4005F000) // TODO: register defs +#define MCGLITE_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBFS_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define VREF_BASE ((uint32_t)0x40074000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define USB_RAM_BASE ((uint32_t)0x400FE000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) LPTPM0_BASE) +#define TPM1 ((TPM_TypeDef *) LPTPM1_BASE) +#define TPM2 ((TPM_TypeDef *) LPTPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBFS_TypeDef *) USBFS_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define VREF ((VREF_TypeDef *) VREF_BASE) +#define MCG ((MCGLite_TypeDef *) MCGLITE_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define LPUART0 ((LPUART_TypeDef *) LPUART0_BASE) +#define LPUART1 ((LPUART_TypeDef *) LPUART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define FLEXIO ((FlexIO_TypeDef *) FLEXIO_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *) SRF_BASE) /* 32 bytes */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) +#define USB_RAM ((volatile uint8_t *) USB_RAM_BASE) /* 512 bytes */ + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_OSC32KOUT_SHIFT 16 /*!< 32K oscillator clock output (shift) */ +#define SIM_SOPT1_OSC32KOUT_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock output (mask) */ +#define SIM_SOPT1_OSC32KOUT(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock output */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_LPUART1SRC_SHIFT 28 /*!< LPUART1 clock source select (shift) */ +#define SIM_SOPT2_LPUART1SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART1SRC_SHIFT)) /*!< LPUART1 clock source select (mask) */ +#define SIM_SOPT2_LPUART1SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART1SRC_SHIFT) & SIM_SOPT2_LPUART1SRC_MASK)) /*!< LPUART1 clock source select */ +#define SIM_SOPT2_LPUART0SRC_SHIFT 26 /*!< LPUART0 clock source select (shift) */ +#define SIM_SOPT2_LPUART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART0SRC_SHIFT)) /*!< LPUART0 clock source select (mask) */ +#define SIM_SOPT2_LPUART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART0SRC_SHIFT) & SIM_SOPT2_LPUART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_FLEXIOSRC_SHIFT 22 /*!< FlexIO Module Clock Source Select (shift) */ +#define SIM_SOPT2_FLEXIOSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_FLEXIO_SHIFT)) /*!< FlexIO Module Clock Source Select (mask) */ +#define SIM_SOPT2_FLEXIOSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_FLEXIO_SHIFT) & SIM_SOPT2_FLEXIO_MASK)) /*!< FlexIO Module Clock Source Select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_LPUART1ODE ((uint32_t)0x00020000) /*!< LPUART1 Open Drain Enable */ +#define SIM_SOPT5_LPUART0ODE ((uint32_t)0x00010000) /*!< LPUART0 Open Drain Enable */ +#define SIM_SOPT5_LPUART1RXSRC ((uint32_t)0x00000040) /*!< LPUART1 receive data source select */ +#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4 /*!< LPUART1 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART1TXSRC_SHIFT)) /*!< LPUART1 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART1TXSRC_SHIFT) & SIM_SOPT5_LPUART1TXSRC_MASK)) /*!< LPUART1 transmit data source select */ +#define SIM_SOPT5_LPUART0RXSRC ((uint32_t)0x00000040) /*!< LPUART0 receive data source select */ +#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0 /*!< LPUART0 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART0TXSRC_SHIFT)) /*!< LPUART0 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART0TXSRC_SHIFT) & SIM_SOPT5_LPUART0TXSRC_MASK)) /*!< LPUART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP0 ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBFS ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_FLEXIO ((uint32_t)0x80000000) /*!< FlexIO Module */ +#define SIM_SCGC5_LPUART1 ((uint32_t)0x00200000) /*!< LPUART1 Clock Gate Control */ +#define SIM_SCGC5_LPUART0 ((uint32_t)0x00100000) /*!< LPUART0 Clock Gate Control */ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPCLKSEL_SHIFT 6 /*!< COP Clock Select (shift) */ +#define SIM_COPC_COPCLKSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPCLKSEL_SHIFT)) /*!< COP Clock Select (mask) */ +#define SIM_COPC_COPCLKSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPCLKSEL_SHIFT) & SIM_COPC_COPCLKSEL_MASK)) /*!< COP Clock Select */ +#define SIM_COPC_COPDBGEN ((uint32_t)0x00000020) /*!< COP Debug Enable */ +#define SIM_COPC_COPSTPEN ((uint32_t)0x00000010) /*!< COP Stop Enable */ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator Lite (MCG_Lite) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_HIRC MCG_C1_CLKS(0) /*!< HIRC */ +#define MCG_C1_CLKS_LIRC MCG_C1_CLKS(1) /*!< LIRC (either LIRC2M or LIRC8M) */ +#define MCG_C1_CLKS_EXT MCG_C1_CLKS(2) /*!< EXT (external ref) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_HIRC MCG_S_CLKST(0) +#define MCG_S_CLKST_LIRC MCG_S_CLKST(1) +#define MCG_S_CLKST_EXT MCG_S_CLKST(2) +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ + +/************ Bits definition for MCG_MC register *************/ +#define MCG_MC_HIRCEN ((uint8_t)0x80) /*!< High-frequency IRC Enable */ +#define MCG_MC_LIRC_DIV2_SHIFT 0 /*!< Second Low-frequency Internal Reference Clock Divider (shift) */ +#define MCG_MC_LIRC_DIV2_MASK ((uint8_t)((uint8_t)0x07 << MCG_MC_LIRC_DIV2_SHIFT)) /*!< Second Low-frequency Internal Reference Clock Divider (mask) */ +#define MCG_MC_LIRC_DIV2(x) ((uint8_t)(((uint8_t)(x) << MCG_MC_LIRC_DIV2_SHIFT) & MCG_MC_LIRC_DIV2_MASK)) /*!< Second Low-frequency Internal Reference Clock Divider */ +#define MCG_MC_LIRC_DIV2_DIV1 MCG_MC_LIRC_DIV2(0) /*!< Divide Factor is 1 */ +#define MCG_MC_LIRC_DIV2_DIV2 MCG_MC_LIRC_DIV2(1) /*!< Divide Factor is 2 */ +#define MCG_MC_LIRC_DIV2_DIV4 MCG_MC_LIRC_DIV2(2) /*!< Divide Factor is 4 */ +#define MCG_MC_LIRC_DIV2_DIV8 MCG_MC_LIRC_DIV2(3) /*!< Divide Factor is 8 */ +#define MCG_MC_LIRC_DIV2_DIV16 MCG_MC_LIRC_DIV2(4) /*!< Divide Factor is 16 */ +#define MCG_MC_LIRC_DIV2_DIV32 MCG_MC_LIRC_DIV2(5) /*!< Divide Factor is 32 */ +#define MCG_MC_LIRC_DIV2_DIV64 MCG_MC_LIRC_DIV2(6) /*!< Divide Factor is 64 */ +#define MCG_MC_LIRC_DIV2_DIV128 MCG_MC_LIRC_DIV2(7) /*!< Divide Factor is 128 */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_SSIE ((uint8_t)0x20) /*!< I2C Bus Stop or Start Interrupt Enable */ +#define I2Cx_FLT_STARTF ((uint8_t)0x10) /*!< I2C Bus Start Detect Flag */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) + +/*********** Bits definition for I2Cx_S2 register *************/ +#define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ +#define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/*Low Power Universal asynchronous receiver/transmitter (LPUART)*/ +/* */ +/****************************************************************/ +/********* Bits definition for LPUARTx_BAUD register **********/ +#define LPUARTx_BAUD_MAEN1 ((uint32_t)0x80000000) /*!< Match Address Mode Enable 1 */ +#define LPUARTx_BAUD_MAEN2 ((uint32_t)0x40000000) /*!< Match Address Mode Enable 2 */ +#define LPUARTx_BAUD_M10 ((uint32_t)0x20000000) /*!< 10-bit Mode select */ +#define LPUARTx_BAUD_OSR_SHIFT 24 /*!< Over Sampling Ratio (shift) */ +#define LPUARTx_BAUD_OSR_MASK ((uint32_t)((uint32_t)0x1F << LPUARTx_BAUD_OSR_SHIFT)) /*!< Over Sampling Ratio (mask) */ +#define LPUARTx_BAUD_OSR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_OSR_SHIFT) & LPUARTx_BAUD_OSR_MASK)) /*!< Over Sampling Ratio */ +#define LPUARTx_BAUD_TDMAE ((uint32_t)0x00800000) /*!< Transmitter DMA Enable */ +#define LPUARTx_BAUD_RDMAE ((uint32_t)0x00200000) /*!< Receiver Full DMA Enable */ +#define LPUARTx_BAUD_MATCFG_SHIFT 18 /*!< Match Configuration (shift) */ +#define LPUARTx_BAUD_MATCFG_MASK ((uint32_t)((uint32_t)0x03 << LPUARTx_BAUD_MATCFG_SHIFT)) /*!< Match Configuration (mask) */ +#define LPUARTx_BAUD_MATCFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_MATCFG_SHIFT) & LPUARTx_BAUD_MATCFG_MASK)) /*!< Match Configuration */ +#define LPUARTx_BAUD_BOTHEDGE ((uint32_t)0x00020000) /*!< Both Edge Sampling */ +#define LPUARTx_BAUD_RESYNCDIS ((uint32_t)0x00010000) /*!< Resynchronization Disable */ +#define LPUARTx_BAUD_LBKDIE ((uint32_t)0x00008000) /*!< LIN Break Detect Interrupt Enable */ +#define LPUARTx_BAUD_RXEDGIE ((uint32_t)0x00004000) /*!< RX Input Active Edge Interrupt Enable */ +#define LPUARTx_BAUD_SBNS ((uint32_t)0x00002000) /*!< Stop Bit Number Select */ +#define LPUARTx_BAUD_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor (shift) */ +#define LPUARTx_BAUD_SBR_MASK ((uint32_t)((uint32_t)0x1FFF << LPUARTx_BAUD_SBR_SHIFT)) /*!< Baud Rate Modulo Divisor (mask) */ +#define LPUARTx_BAUD_SBR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_SBR_SHIFT) & LPUARTx_BAUD_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for LPUARTx_STAT register **********/ +#define LPUARTx_STAT_LBKDIF ((uint32_t)0x80000000) /*!< LIN Break Detect Interrupt Flag */ +#define LPUARTx_STAT_RXEDGIF ((uint32_t)0x40000000) /*!< LPUART_RX Pin Active Edge Interrupt Flag */ +#define LPUARTx_STAT_MSBF ((uint32_t)0x20000000) /*!< MSB First */ +#define LPUARTx_STAT_RXINV ((uint32_t)0x10000000) /*!< Receive Data Inversion */ +#define LPUARTx_STAT_RWUID ((uint32_t)0x08000000) /*!< Receive Wake Up Idle Detect */ +#define LPUARTx_STAT_BRK13 ((uint32_t)0x04000000) /*!< Break Character Generation Length */ +#define LPUARTx_STAT_LBKDE ((uint32_t)0x02000000) /*!< LIN Break Detection Enable */ +#define LPUARTx_STAT_RAF ((uint32_t)0x01000000) /*!< Receiver Active Flag */ +#define LPUARTx_STAT_TDRE ((uint32_t)0x00800000) /*!< Transmit Data Register Empty Flag */ +#define LPUARTx_STAT_TC ((uint32_t)0x00400000) /*!< Transmission Complete Flag */ +#define LPUARTx_STAT_RDRF ((uint32_t)0x00200000) /*!< Receive Data Register Full Flag */ +#define LPUARTx_STAT_IDLE ((uint32_t)0x00100000) /*!< Idle Line Flag */ +#define LPUARTx_STAT_OR ((uint32_t)0x00080000) /*!< Receiver Overrun Flag */ +#define LPUARTx_STAT_NF ((uint32_t)0x00040000) /*!< Noise Flag */ +#define LPUARTx_STAT_FE ((uint32_t)0x00020000) /*!< Framing Error Flag */ +#define LPUARTx_STAT_PF ((uint32_t)0x00010000) /*!< Parity Error Flag */ +#define LPUARTx_STAT_MA1F ((uint32_t)0x00008000) /*!< Match 1 Flag */ +#define LPUARTx_STAT_MA2F ((uint32_t)0x00004000) /*!< Match 2 Flag */ + +/********* Bits definition for LPUARTx_CTRL register **********/ +#define LPUARTx_CTRL_R8T9 ((uint32_t)0x80000000) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define LPUARTx_CTRL_R9T8 ((uint32_t)0x40000000) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define LPUARTx_CTRL_TXDIR ((uint32_t)0x20000000) /*!< LPUART_TX Pin Direction in Single-Wire Mode */ +#define LPUARTx_CTRL_TXINV ((uint32_t)0x10000000) /*!< Transmit Data Inversion */ +#define LPUARTx_CTRL_ORIE ((uint32_t)0x08000000) /*!< Overrun Interrupt Enable */ +#define LPUARTx_CTRL_NEIE ((uint32_t)0x04000000) /*!< Noise Error Interrupt Enable */ +#define LPUARTx_CTRL_FEIE ((uint32_t)0x02000000) /*!< Framing Error Interrupt Enable */ +#define LPUARTx_CTRL_PEIE ((uint32_t)0x01000000) /*!< Parity Error Interrupt Enable */ +#define LPUARTx_CTRL_TIE ((uint32_t)0x00800000) /*!< Transmit Interrupt Enable */ +#define LPUARTx_CTRL_TCIE ((uint32_t)0x00400000) /*!< Transmission Complete Interrupt Enable */ +#define LPUARTx_CTRL_RIE ((uint32_t)0x00200000) /*!< Receiver Interrupt Enable */ +#define LPUARTx_CTRL_ILIE ((uint32_t)0x00100000) /*!< Idle Line Interrupt Enable */ +#define LPUARTx_CTRL_TE ((uint32_t)0x00080000) /*!< Transmitter Enable */ +#define LPUARTx_CTRL_RE ((uint32_t)0x00040000) /*!< Receiver Enable */ +#define LPUARTx_CTRL_RWU ((uint32_t)0x00020000) /*!< Receiver Wakeup Control */ +#define LPUARTx_CTRL_SBK ((uint32_t)0x00010000) /*!< Send Break */ +#define LPUARTx_CTRL_MA1IE ((uint32_t)0x00008000) /*!< Match 1 Interrupt Enable */ +#define LPUARTx_CTRL_MA2IE ((uint32_t)0x00004000) /*!< Match 2 Interrupt Enable */ +#define LPUARTx_CTRL_IDLECFG_SHIFT 8 /*!< Idle Configuration (shift) */ +#define LPUARTx_CTRL_IDLECFG_MASK ((uint32_t)((uint32_t)0x7 << LPUARTx_CTRL_IDLECFG_SHIFT)) /*!< Idle Configuration (mask) */ +#define LPUARTx_CTRL_IDLECFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_CTRL_IDLECFG_SHIFT) & LPUARTx_CTRL_IDLECFG_MASK)) /*!< Idle Configuration */ +#define LPUARTx_CTRL_LOOPS ((uint32_t)0x00000080) /*!< Loop Mode Select */ +#define LPUARTx_CTRL_DOZEEN ((uint32_t)0x00000040) /*!< Doze Enable */ +#define LPUARTx_CTRL_RSRC ((uint32_t)0x00000020) /*!< Receiver Source Select */ +#define LPUARTx_CTRL_M ((uint32_t)0x00000010) /*!< 9-Bit or 8-Bit Mode Select */ +#define LPUARTx_CTRL_WAKE ((uint32_t)0x00000008) /*!< Receiver Wakeup Method Select */ +#define LPUARTx_CTRL_ILT ((uint32_t)0x00000004) /*!< Idle Line Type Select */ +#define LPUARTx_CTRL_PE ((uint32_t)0x00000002) /*!< Parity Enable */ +#define LPUARTx_CTRL_PT ((uint32_t)0x00000001) /*!< Parity Type */ + +/********* Bits definition for LPUARTx_DATA register **********/ +#define LPUARTx_DATA_NOISY ((uint32_t)0x00008000) /*!< The current received dataword contained in DATA[R9:R0] was received with noise */ +#define LPUARTx_DATA_PARITYE ((uint32_t)0x00004000) /*!< The current received dataword contained in DATA[R9:R0] was received with a parity error */ +#define LPUARTx_DATA_FRETSC ((uint32_t)0x00002000) /*!< Frame Error / Transmit Special Character */ +#define LPUARTx_DATA_RXEMPT ((uint32_t)0x00001000) /*!< Receive Buffer Empty */ +#define LPUARTx_DATA_IDLINE ((uint32_t)0x00000800) /*!< Idle Line */ +#define LPUARTx_DATA_R9T9 ((uint32_t)0x00000200) /*!< Read receive data buffer 9 or write transmit data buffer 9 */ +#define LPUARTx_DATA_R8T8 ((uint32_t)0x00000100) /*!< Read receive data buffer 8 or write transmit data buffer 8 */ +#define LPUARTx_DATA_R7T7 ((uint32_t)0x00000080) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define LPUARTx_DATA_R6T6 ((uint32_t)0x00000040) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define LPUARTx_DATA_R5T5 ((uint32_t)0x00000020) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define LPUARTx_DATA_R4T4 ((uint32_t)0x00000010) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define LPUARTx_DATA_R3T3 ((uint32_t)0x00000008) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define LPUARTx_DATA_R2T2 ((uint32_t)0x00000004) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define LPUARTx_DATA_R1T1 ((uint32_t)0x00000002) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define LPUARTx_DATA_R0T0 ((uint32_t)0x00000001) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define LPUARTx_DATA_DATA_SHIFT 0 /*!< Data (shift) */ +#define LPUARTx_DATA_DATA_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_DATA_DATA_SHIFT)) /*!< Data (mask) */ +#define LPUARTx_DATA_DATA(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_DATA_DATA_SHIFT) & LPUARTx_DATA_DATA_MASK)) /*!< Data */ + +/********* Bits definition for LPUARTx_MATCH register *********/ +#define LPUARTx_MATCH_MA2_SHIFT 16 /*!< Match Address 2 (shift) */ +#define LPUARTx_MATCH_MA2_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA2_SHIFT)) /*!< Match Address 2 (mask) */ +#define LPUARTx_MATCH_MA2(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA2_SHIFT) & LPUARTx_MATCH_MA2_MASK)) /*!< Match Address 2 */ +#define LPUARTx_MATCH_MA1_SHIFT 0 /*!< Match Address 1 (shift) */ +#define LPUARTx_MATCH_MA1_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA1_SHIFT)) /*!< Match Address 1 (mask) */ +#define LPUARTx_MATCH_MA1(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA1_SHIFT) & LPUARTx_MATCH_MA1_MASK)) /*!< Match Address 1 */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_POL register **************/ +#define TPMx_POL_POL5 ((uint32_t)0x20) /*!< Channel 5 Polarity */ +#define TPMx_POL_POL4 ((uint32_t)0x10) /*!< Channel 4 Polarity */ +#define TPMx_POL_POL3 ((uint32_t)0x08) /*!< Channel 3 Polarity */ +#define TPMx_POL_POL2 ((uint32_t)0x04) /*!< Channel 2 Polarity */ +#define TPMx_POL_POL1 ((uint32_t)0x02) /*!< Channel 1 Polarity */ +#define TPMx_POL_POL0 ((uint32_t)0x01) /*!< Channel 0 Polarity */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_TRGSRC ((uint32_t)0x800000) /*!< Trigger Source */ +#define TPMx_CONF_TRGPOL ((uint32_t)0x400000) /*!< Trigger Polarity */ +#define TPMx_CONF_CPOT ((uint32_t)0x80000) /*!< Counter Pause On Trigger */ +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_GTBSYNC ((uint32_t)0x100) /*!< Global Time Base Synchronization */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USBFS: Device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USB_CLK_RECOVERY_INT ((uint8_t)0x04) /* Combined USB Clock Recovery interrupt status */ + +/****** Bits definition for USBx_KEEP_ALIVE_CTRL register *******/ +#define USBx_KEEP_ALIVE_CTRL_WAKE_INT_STS ((uint8_t)0x80) /*!< Wakeup Interrupt Status. */ +#define USBx_KEEP_ALIVE_CTRL_WAKE_INT_EN ((uint8_t)0x10) /*!< Wakeup Interrupt Enable. */ +#define USBx_KEEP_ALIVE_CTRL_AHB_DLY_EN ((uint8_t)0x08) /*!< Set to 1 to delay the first USB AHB bus transfer until after the USB has exited KEEP_ALIVE mode. */ +#define USBx_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN ((uint8_t)0x04) /*!< ... see manual ... */ +#define USBx_KEEP_ALIVE_CTRL_OWN_OVERRD_EN ((uint8_t)0x02) /*!< When set to 1, during KEEP_ALIVE mode, if received token is not SETUP, the OWN bit of current BD will be forced to 0, so usb core will response with NAK. */ +#define USBx_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN ((uint8_t)0x01) /*!< Global enable for USB_KEEP_ALIVE mode. */ + +/****** Bits definition for USBx_KEEP_ALIVE_WKCTRL register *****/ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT 4 /*!< Which endpoint caused the wakeup interrupt. */ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK ((uint8_t)((uint8_t)0xF << USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT 0 /*!< Which token can wakeup usb */ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK ((uint8_t)((uint8_t)0xF << USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) ((uint8_t)(((uint8_t)(x) << USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT) & USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_OUTSETUP USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(1) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SETUPONLY USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(0xD) + +/****** Bits definition for USBx_CLK_RECOVER_CTRL register ******/ +#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN ((uint8_t)0x80) /*!< Crystal-less USB enable */ +#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN ((uint8_t)0x40) /*!< Reset/resume to rough phase enable */ +#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN ((uint8_t)0x20) /*!< Restart from IFR trim value */ + +/****** Bits definition for USBx_CLK_RECOVER_IRC_EN register ****/ +#define USBx_CLK_RECOVER_IRC_EN_IRC_EN ((uint8_t)0x02) /*!< IRC48M enable */ + +/****** Bits definition for USBx_CLK_RECOVER_INT_EN register ****/ +#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN ((uint8_t)0x10) /*!< Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. */ + +/*** Bits definition for USBx_CLK_RECOVER_INT_STATUS register ***/ +#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR ((uint8_t)0x10) /*!< frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ +/* Device independent parts, plus: */ +/*********** Bits definition for RCM_FM register ****************/ +#define RCM_FM_FORCEROM_SHIFT 1 /*!< Force ROM Boot */ +#define RCM_FM_FORCEROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_FM_FORCEROM_SHIFT)) +#define RCM_FM_FORCEROM(x) ((uint8_t)(((uint8_t)(x) << RCM_FM_FORCEROM_SHIFT) & RCM_FM_FORCEROM_MASK)) + +/*********** Bits definition for RCM_MR register ****************/ +#define RCM_MR_BOOTROM_SHIFT 1 /*!< Boot ROM Configuration */ +#define RCM_MR_BOOTROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_MR_BOOTROM_SHIFT)) +#define RCM_MR_BOOTROM(x) ((uint8_t)(((uint8_t)(x) << RCM_MR_BOOTROM_SHIFT) & RCM_MR_BOOTROM_MASK)) +#define RCM_MR_BOOTROM_FROM_FLASH RCM_MR_BOOTROM(0) +#define RCM_MR_BOOTROM_FROM_ROM_BOOTCFG0 RCM_MR_BOOTROM(1) +#define RCM_MR_BOOTROM_FROM_ROM_FOPT RCM_MR_BOOTROM(2) +#define RCM_MR_BOOTROM_FROM_ROM_BOTH RCM_MR_BOOTROM(3) + +/********** Bits definition for RCM_SSRS0 register ************/ +#define RCM_SSRS0_SPOR ((uint8_t)0x80) /*!< Sticky Power-On Reset */ +#define RCM_SSRS0_SPIN ((uint8_t)0x40) /*!< Sticky External Reset Pin */ +#define RCM_SSRS0_SWDOG ((uint8_t)0x20) /*!< Sticky Watchdog */ +#define RCM_SSRS0_SLVD ((uint8_t)0x02) /*!< Sticky Low-Voltage Detect Reset */ +#define RCM_SSRS0_SWAKEUP ((uint8_t)0x01) /*!< Sticky Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SSRS1 register *************/ +#define RCM_SSRS1_SSACKERR ((uint8_t)0x20) /*!< Sticky Stop Mode Acknowledge Error Reset */ +#define RCM_SSRS1_SMDM_AP ((uint8_t)0x08) /*!< Sticky MDM-AP System Reset Request */ +#define RCM_SSRS1_SSW ((uint8_t)0x04) /*!< Sticky Software */ +#define RCM_SSRS1_SLOCKUP ((uint8_t)0x02) /*!< Sticky Core Lockup */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Voltage Reference (VREFV1) */ +/* */ +/****************************************************************/ +/********** Bits definition for VREF_TRM register ***************/ +#define VREF_TRM_CHOPEN ((uint8_t)0x40) /*!< Chop oscillator enable. */ +#define VREF_TRM_TRIM_SHIFT 0 /*!< Trim bits */ +#define VREF_TRM_TRIM_MASK ((uint8_t)((uint8_t)0x3F << VREF_TRM_TRIM_SHIFT)) +#define VREF_TRM_TRIM(x) ((uint8_t)(((uint8_t)(x) << VREF_TRM_TRIM_SHIFT) & VREF_TRM_TRIM_MASK)) + +/********** Bits definition for VREF_SC register ****************/ +#define VREF_SC_VREFEN ((uint8_t)0x80) /*!< Internal Voltage Reference enable */ +#define VREF_SC_REGEN ((uint8_t)0x40) /*!< Regulator enable */ +#define VREF_SC_ICOMPEN ((uint8_t)0x20) /*!< Second order curvature compensation enable */ +#define VREF_SC_VREFST ((uint8_t)0x04) /*!< Internal Voltage Reference stable */ +#define VREF_SC_MODE_LV_SHIFT 0 /*!< Buffer Mode selection */ +#define VREF_SC_MODE_LV_MASK ((uint8_t)((uint8_t)0x3 << VREF_SC_MODE_LV_SHIFT)) +#define VREF_SC_MODE_LV(x) ((uint8_t)(((uint8_t)(x) << VREF_SC_MODE_LV_SHIFT) & VREF_SC_MODE_LV_MASK)) + +#define VREF_SC_MODE_LV_BANDGAP_ONLY VREF_SC_MODE_LV(0) +#define VREF_SC_MODE_LV_HIGH_POWER VREF_SC_MODE_LV(1) +#define VREF_SC_MODE_LV_LOW_POWER VREF_SC_MODE_LV(2) + +/****************************************************************/ +/* */ +/* Cyclic Redundancy Check (CRC) */ +/* */ +/****************************************************************/ +/********** Bits definition for CRC_DATA register ***************/ +#define CRC_DATA_HU_SHIFT 24 /*!< CRC High Upper Byte */ +#define CRC_DATA_HU_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_HU_SHIFT)) +#define CRC_DATA_HU(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_HU_SHIFT) & CRC_DATA_HU_MASK)) +#define CRC_DATA_HL_SHIFT 16 /*!< CRC High Lower Byte */ +#define CRC_DATA_HL_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_HL_SHIFT)) +#define CRC_DATA_HL(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_HL_SHIFT) & CRC_DATA_HL_MASK)) +#define CRC_DATA_LU_SHIFT 8 /*!< CRC Low Upper Byte */ +#define CRC_DATA_LU_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_LU_SHIFT)) +#define CRC_DATA_LU(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_LU_SHIFT) & CRC_DATA_LU_MASK)) +#define CRC_DATA_LL_SHIFT 0 /*!< CRC Low Lower Byte */ +#define CRC_DATA_LL_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_LL_SHIFT)) +#define CRC_DATA_LL(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_LL_SHIFT) & CRC_DATA_LL_MASK)) + +/********** Bits definition for CRC_GPOLY register **************/ +#define CRC_GPOLY_HIGH_SHIFT 16 /*!< High Polynominal Half-word */ +#define CRC_GPOLY_HIGH_MASK ((uint32_t)((uint32_t)0xFFFF << CRC_GPOLY_HIGH_SHIFT)) +#define CRC_GPOLY_HIGH(x) ((uint32_t)(((uint32_t)(x) << CRC_GPOLY_HIGH_SHIFT) & CRC_GPOLY_HIGH_MASK)) +#define CRC_GPOLY_LOW_SHIFT 0 /*!< Low Polynominal Half-word */ +#define CRC_GPOLY_LOW_MASK ((uint32_t)((uint32_t)0xFFFF << CRC_GPOLY_LOW_SHIFT)) +#define CRC_GPOLY_LOW(x) ((uint32_t)(((uint32_t)(x) << CRC_GPOLY_LOW_SHIFT) & CRC_GPOLY_LOW_MASK)) + +/********** Bits definition for CRC_CTRL register ***************/ +#define CRC_CTRL_TOT_SHIFT 30 /*!< Type Of Transpose For Writes */ +#define CRC_CTRL_TOT_MASK ((uint32_t)((uint32_t)0x3 << CRC_CTRL_TOT_SHIFT)) +#define CRC_CTRL_TOT(x) ((uint32_t)(((uint32_t)(x) << CRC_CTRL_TOT_SHIFT) & CRC_CTRL_TOT_MASK)) +#define CRC_CTRL_TOTR_SHIFT 28 /*!< Type Of Transpose For Read */ +#define CRC_CTRL_TOTR_MASK ((uint32_t)((uint32_t)0x3 << CRC_CTRL_TOTR_SHIFT)) +#define CRC_CTRL_TOTR(x) ((uint32_t)(((uint32_t)(x) << CRC_CTRL_TOTR_SHIFT) & CRC_CTRL_TOTR_MASK)) +#define CRC_CTRL_FXOR ((uint32_t)0x04000000) /*!< Complement Read Of CRC Data Register */ +#define CRC_CTRL_WAS ((uint32_t)0x02000000) /*!< Write CRC Data Register As Seed */ +#define CRC_CTRL_TCRC ((uint32_t)0x01000000) /*!< Width of CRC protocol. */ + +#endif /* _KL27ZXX_H_ */ diff --git a/os/common/ext/CMSIS/KINETIS/kl27zxxx.h b/os/common/ext/CMSIS/KINETIS/kl27zxxx.h new file mode 100644 index 0000000..76238c0 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/kl27zxxx.h @@ -0,0 +1,1294 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL27ZXXX_H_ +#define _KL27ZXXX_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + LPUART0_IRQn = 12, + LPUART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + I2S0_IRQn = 23, + USB_IRQn = 24, + DAC0_IRQn = 25, + Reserved2_IRQn = 26, + Reserved3_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved4_IRQn = 29, + PINA_IRQn = 30, + PINCD_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + uint8_t RESERVED0[4]; + __I uint8_t S; + uint8_t RESERVED1[1]; + __IO uint8_t SC; + uint8_t RESERVED2[15]; + __IO uint8_t MC; +} MCGLite_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[7]; + __IO uint32_t POL; + uint32_t RESERVED2[4]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; + __IO uint8_t S2; +} I2C_TypeDef; + +typedef struct +{ + __IO uint32_t BAUD; + __IO uint32_t STAT; + __IO uint32_t CTRL; + __IO uint32_t DATA; + __IO uint32_t MATCH; +} LPUART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UART_TypeDef; + +typedef struct +{ + __I uint32_t VERID; + __I uint32_t PARAM; + __IO uint32_t CTRL; + uint32_t RESERVED0[1]; + __IO uint32_t SHIFTSTAT; + __IO uint32_t SHIFTERR; + __IO uint32_t TIMSTAT; + uint32_t RESERVED1[1]; + __IO uint32_t SHIFTSIEN; + __IO uint32_t SHIFTEIEN; + __IO uint32_t TIMIEN; + uint32_t RESERVED2[1]; + __IO uint32_t SHIFTSDEN; + uint32_t RESERVED3[19]; + __IO uint32_t SHIFTCTL[4]; + uint32_t RESERVED4[28]; + __IO uint32_t SHIFTCFG[4]; + uint32_t RESERVED5[60]; + __IO uint32_t SHIFTBUF[4]; + uint32_t RESERVED6[28]; + __IO uint32_t SHIFTBUFBIS[4]; + uint32_t RESERVED7[28]; + __IO uint32_t SHIFTBUFBYS[4]; + uint32_t RESERVED8[28]; + __IO uint32_t SHIFTBUFBBS[4]; + uint32_t RESERVED9[28]; + __IO uint32_t TIMCTL[4]; + uint32_t RESERVED10[28]; + __IO uint32_t TIMCFG[4]; + uint32_t RESERVED11[28]; + __IO uint32_t TIMCMP[4]; +} FlexIO_TypeDef; + +typedef struct +{ + __IO uint8_t TRM; + __IO uint8_t SC; +} VREF_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[15]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[11]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 + uint8_t RESERVED26[43]; + __IO uint8_t CLK_RECOVER_CTRL; // 0x140 + uint8_t RESERVED27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; // 0x144 + uint8_t RESERVED28[15]; + __IO uint8_t CLK_RECOVER_INT_EN; // 0x154 + uint8_t RESERVED29[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; // 0x15c +} USBFS_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; + __IO uint8_t FM; + __IO uint8_t MR; + __IO uint8_t SSRS0; + __IO uint8_t SSRS1; +} RCM_TypeDef; + +typedef struct { + __IO uint32_t TCSR; // 0x00 + uint32_t RESERVED0[1]; + __IO uint32_t TCR2; // 0x08 + __IO uint32_t TCR3; // 0x0C + __IO uint32_t TCR4; // 0x10 + __IO uint32_t TCR5; // 0x14 + uint32_t RESERVED1[2]; + __O uint32_t TDR0; // 0x20 + uint32_t RESERVED2[15]; + __IO uint32_t TMR; // 0x60 + uint32_t RESERVED3[7]; + __IO uint32_t RCSR; // 0x80 + uint32_t RESERVED4[1]; + __IO uint32_t RCR2; // 0x88 + __IO uint32_t RCR3; // 0x8C + __IO uint32_t RCR4; // 0x90 + __IO uint32_t RCR5; // 0x94 + uint32_t RESERVED5[2]; + __I uint32_t RDR0; // 0xA0 + uint32_t RESERVED6[15]; + __IO uint32_t RMR; // 0xE0 + uint32_t RESERVED7[7]; + __IO uint32_t MCR; // 0x100 +} I2S_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define I2S0_BASE ((uint32_t)0x4002F000) // TODO: registers not implemented +#define PIT_BASE ((uint32_t)0x40037000) +#define LPTPM0_BASE ((uint32_t)0x40038000) +#define LPTPM1_BASE ((uint32_t)0x40039000) +#define LPTPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define LPUART0_BASE ((uint32_t)0x40054000) +#define LPUART1_BASE ((uint32_t)0x40055000) +#define FLEXIO_BASE ((uint32_t)0x4005F000) // TODO: register defs +#define MCGLITE_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBFS_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define VREF_BASE ((uint32_t)0x40074000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define I2S0 ((I2S_TypeDef *) I2S0_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) LPTPM0_BASE) +#define TPM1 ((TPM_TypeDef *) LPTPM1_BASE) +#define TPM2 ((TPM_TypeDef *) LPTPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBFS_TypeDef *) USBFS_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define VREF ((VREF_TypeDef *) VREF_BASE) +#define MCG ((MCGLite_TypeDef *) MCGLITE_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define LPUART0 ((LPUART_TypeDef *) LPUART0_BASE) +#define LPUART1 ((LPUART_TypeDef *) LPUART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define FLEXIO ((FlexIO_TypeDef *) FLEXIO_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *) SRF_BASE) /* 32 bytes */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_OSC32KOUT_SHIFT 16 /*!< 32K oscillator clock output (shift) */ +#define SIM_SOPT1_OSC32KOUT_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock output (mask) */ +#define SIM_SOPT1_OSC32KOUT(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock output */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_LPUART1SRC_SHIFT 28 /*!< LPUART1 clock source select (shift) */ +#define SIM_SOPT2_LPUART1SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART1SRC_SHIFT)) /*!< LPUART1 clock source select (mask) */ +#define SIM_SOPT2_LPUART1SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART1SRC_SHIFT) & SIM_SOPT2_LPUART1SRC_MASK)) /*!< LPUART1 clock source select */ +#define SIM_SOPT2_LPUART0SRC_SHIFT 26 /*!< LPUART0 clock source select (shift) */ +#define SIM_SOPT2_LPUART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART0SRC_SHIFT)) /*!< LPUART0 clock source select (mask) */ +#define SIM_SOPT2_LPUART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART0SRC_SHIFT) & SIM_SOPT2_LPUART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_FLEXIOSRC_SHIFT 22 /*!< FlexIO Module Clock Source Select (shift) */ +#define SIM_SOPT2_FLEXIOSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_FLEXIO_SHIFT)) /*!< FlexIO Module Clock Source Select (mask) */ +#define SIM_SOPT2_FLEXIOSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_FLEXIO_SHIFT) & SIM_SOPT2_FLEXIO_MASK)) /*!< FlexIO Module Clock Source Select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_LPUART1ODE ((uint32_t)0x00020000) /*!< LPUART1 Open Drain Enable */ +#define SIM_SOPT5_LPUART0ODE ((uint32_t)0x00010000) /*!< LPUART0 Open Drain Enable */ +#define SIM_SOPT5_LPUART1RXSRC ((uint32_t)0x00000040) /*!< LPUART1 receive data source select */ +#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4 /*!< LPUART1 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART1TXSRC_SHIFT)) /*!< LPUART1 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART1TXSRC_SHIFT) & SIM_SOPT5_LPUART1TXSRC_MASK)) /*!< LPUART1 transmit data source select */ +#define SIM_SOPT5_LPUART0RXSRC ((uint32_t)0x00000040) /*!< LPUART0 receive data source select */ +#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0 /*!< LPUART0 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART0TXSRC_SHIFT)) /*!< LPUART0 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART0TXSRC_SHIFT) & SIM_SOPT5_LPUART0TXSRC_MASK)) /*!< LPUART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP0 ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBFS ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_FLEXIO ((uint32_t)0x80000000) /*!< FlexIO Module */ +#define SIM_SCGC5_LPUART1 ((uint32_t)0x00200000) /*!< LPUART1 Clock Gate Control */ +#define SIM_SCGC5_LPUART0 ((uint32_t)0x00100000) /*!< LPUART0 Clock Gate Control */ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< I2S0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPCLKSEL_SHIFT 6 /*!< COP Clock Select (shift) */ +#define SIM_COPC_COPCLKSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPCLKSEL_SHIFT)) /*!< COP Clock Select (mask) */ +#define SIM_COPC_COPCLKSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPCLKSEL_SHIFT) & SIM_COPC_COPCLKSEL_MASK)) /*!< COP Clock Select */ +#define SIM_COPC_COPDBGEN ((uint32_t)0x00000020) /*!< COP Debug Enable */ +#define SIM_COPC_COPSTPEN ((uint32_t)0x00000010) /*!< COP Stop Enable */ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator Lite (MCG_Lite) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_HIRC MCG_C1_CLKS(0) /*!< HIRC */ +#define MCG_C1_CLKS_LIRC MCG_C1_CLKS(1) /*!< LIRC (either LIRC2M or LIRC8M) */ +#define MCG_C1_CLKS_EXT MCG_C1_CLKS(2) /*!< EXT (external ref) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_HIRC MCG_S_CLKST(0) +#define MCG_S_CLKST_LIRC MCG_S_CLKST(1) +#define MCG_S_CLKST_EXT MCG_S_CLKST(2) +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ + +/************ Bits definition for MCG_MC register *************/ +#define MCG_MC_HIRCEN ((uint8_t)0x80) /*!< High-frequency IRC Enable */ +#define MCG_MC_LIRC_DIV2_SHIFT 0 /*!< Second Low-frequency Internal Reference Clock Divider (shift) */ +#define MCG_MC_LIRC_DIV2_MASK ((uint8_t)((uint8_t)0x07 << MCG_MC_LIRC_DIV2_SHIFT)) /*!< Second Low-frequency Internal Reference Clock Divider (mask) */ +#define MCG_MC_LIRC_DIV2(x) ((uint8_t)(((uint8_t)(x) << MCG_MC_LIRC_DIV2_SHIFT) & MCG_MC_LIRC_DIV2_MASK)) /*!< Second Low-frequency Internal Reference Clock Divider */ +#define MCG_MC_LIRC_DIV2_DIV1 MCG_MC_LIRC_DIV2(0) /*!< Divide Factor is 1 */ +#define MCG_MC_LIRC_DIV2_DIV2 MCG_MC_LIRC_DIV2(1) /*!< Divide Factor is 2 */ +#define MCG_MC_LIRC_DIV2_DIV4 MCG_MC_LIRC_DIV2(2) /*!< Divide Factor is 4 */ +#define MCG_MC_LIRC_DIV2_DIV8 MCG_MC_LIRC_DIV2(3) /*!< Divide Factor is 8 */ +#define MCG_MC_LIRC_DIV2_DIV16 MCG_MC_LIRC_DIV2(4) /*!< Divide Factor is 16 */ +#define MCG_MC_LIRC_DIV2_DIV32 MCG_MC_LIRC_DIV2(5) /*!< Divide Factor is 32 */ +#define MCG_MC_LIRC_DIV2_DIV64 MCG_MC_LIRC_DIV2(6) /*!< Divide Factor is 64 */ +#define MCG_MC_LIRC_DIV2_DIV128 MCG_MC_LIRC_DIV2(7) /*!< Divide Factor is 128 */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_SSIE ((uint8_t)0x20) /*!< I2C Bus Stop or Start Interrupt Enable */ +#define I2Cx_FLT_STARTF ((uint8_t)0x10) /*!< I2C Bus Start Detect Flag */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) + +/*********** Bits definition for I2Cx_S2 register *************/ +#define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ +#define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/*Low Power Universal asynchronous receiver/transmitter (LPUART)*/ +/* */ +/****************************************************************/ +/********* Bits definition for LPUARTx_BAUD register **********/ +#define LPUARTx_BAUD_MAEN1 ((uint32_t)0x80000000) /*!< Match Address Mode Enable 1 */ +#define LPUARTx_BAUD_MAEN2 ((uint32_t)0x40000000) /*!< Match Address Mode Enable 2 */ +#define LPUARTx_BAUD_M10 ((uint32_t)0x20000000) /*!< 10-bit Mode select */ +#define LPUARTx_BAUD_OSR_SHIFT 24 /*!< Over Sampling Ratio (shift) */ +#define LPUARTx_BAUD_OSR_MASK ((uint32_t)((uint32_t)0x1F << LPUARTx_BAUD_OSR_SHIFT)) /*!< Over Sampling Ratio (mask) */ +#define LPUARTx_BAUD_OSR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_OSR_SHIFT) & LPUARTx_BAUD_OSR_MASK)) /*!< Over Sampling Ratio */ +#define LPUARTx_BAUD_TDMAE ((uint32_t)0x00800000) /*!< Transmitter DMA Enable */ +#define LPUARTx_BAUD_RDMAE ((uint32_t)0x00200000) /*!< Receiver Full DMA Enable */ +#define LPUARTx_BAUD_MATCFG_SHIFT 18 /*!< Match Configuration (shift) */ +#define LPUARTx_BAUD_MATCFG_MASK ((uint32_t)((uint32_t)0x03 << LPUARTx_BAUD_MATCFG_SHIFT)) /*!< Match Configuration (mask) */ +#define LPUARTx_BAUD_MATCFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_MATCFG_SHIFT) & LPUARTx_BAUD_MATCFG_MASK)) /*!< Match Configuration */ +#define LPUARTx_BAUD_BOTHEDGE ((uint32_t)0x00020000) /*!< Both Edge Sampling */ +#define LPUARTx_BAUD_RESYNCDIS ((uint32_t)0x00010000) /*!< Resynchronization Disable */ +#define LPUARTx_BAUD_LBKDIE ((uint32_t)0x00008000) /*!< LIN Break Detect Interrupt Enable */ +#define LPUARTx_BAUD_RXEDGIE ((uint32_t)0x00004000) /*!< RX Input Active Edge Interrupt Enable */ +#define LPUARTx_BAUD_SBNS ((uint32_t)0x00002000) /*!< Stop Bit Number Select */ +#define LPUARTx_BAUD_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor (shift) */ +#define LPUARTx_BAUD_SBR_MASK ((uint32_t)((uint32_t)0x1FFF << LPUARTx_BAUD_SBR_SHIFT)) /*!< Baud Rate Modulo Divisor (mask) */ +#define LPUARTx_BAUD_SBR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_SBR_SHIFT) & LPUARTx_BAUD_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for LPUARTx_STAT register **********/ +#define LPUARTx_STAT_LBKDIF ((uint32_t)0x80000000) /*!< LIN Break Detect Interrupt Flag */ +#define LPUARTx_STAT_RXEDGIF ((uint32_t)0x40000000) /*!< LPUART_RX Pin Active Edge Interrupt Flag */ +#define LPUARTx_STAT_MSBF ((uint32_t)0x20000000) /*!< MSB First */ +#define LPUARTx_STAT_RXINV ((uint32_t)0x10000000) /*!< Receive Data Inversion */ +#define LPUARTx_STAT_RWUID ((uint32_t)0x08000000) /*!< Receive Wake Up Idle Detect */ +#define LPUARTx_STAT_BRK13 ((uint32_t)0x04000000) /*!< Break Character Generation Length */ +#define LPUARTx_STAT_LBKDE ((uint32_t)0x02000000) /*!< LIN Break Detection Enable */ +#define LPUARTx_STAT_RAF ((uint32_t)0x01000000) /*!< Receiver Active Flag */ +#define LPUARTx_STAT_TDRE ((uint32_t)0x00800000) /*!< Transmit Data Register Empty Flag */ +#define LPUARTx_STAT_TC ((uint32_t)0x00400000) /*!< Transmission Complete Flag */ +#define LPUARTx_STAT_RDRF ((uint32_t)0x00200000) /*!< Receive Data Register Full Flag */ +#define LPUARTx_STAT_IDLE ((uint32_t)0x00100000) /*!< Idle Line Flag */ +#define LPUARTx_STAT_OR ((uint32_t)0x00080000) /*!< Receiver Overrun Flag */ +#define LPUARTx_STAT_NF ((uint32_t)0x00040000) /*!< Noise Flag */ +#define LPUARTx_STAT_FE ((uint32_t)0x00020000) /*!< Framing Error Flag */ +#define LPUARTx_STAT_PF ((uint32_t)0x00010000) /*!< Parity Error Flag */ +#define LPUARTx_STAT_MA1F ((uint32_t)0x00008000) /*!< Match 1 Flag */ +#define LPUARTx_STAT_MA2F ((uint32_t)0x00004000) /*!< Match 2 Flag */ + +/********* Bits definition for LPUARTx_CTRL register **********/ +#define LPUARTx_CTRL_R8T9 ((uint32_t)0x80000000) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define LPUARTx_CTRL_R9T8 ((uint32_t)0x40000000) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define LPUARTx_CTRL_TXDIR ((uint32_t)0x20000000) /*!< LPUART_TX Pin Direction in Single-Wire Mode */ +#define LPUARTx_CTRL_TXINV ((uint32_t)0x10000000) /*!< Transmit Data Inversion */ +#define LPUARTx_CTRL_ORIE ((uint32_t)0x08000000) /*!< Overrun Interrupt Enable */ +#define LPUARTx_CTRL_NEIE ((uint32_t)0x04000000) /*!< Noise Error Interrupt Enable */ +#define LPUARTx_CTRL_FEIE ((uint32_t)0x02000000) /*!< Framing Error Interrupt Enable */ +#define LPUARTx_CTRL_PEIE ((uint32_t)0x01000000) /*!< Parity Error Interrupt Enable */ +#define LPUARTx_CTRL_TIE ((uint32_t)0x00800000) /*!< Transmit Interrupt Enable */ +#define LPUARTx_CTRL_TCIE ((uint32_t)0x00400000) /*!< Transmission Complete Interrupt Enable */ +#define LPUARTx_CTRL_RIE ((uint32_t)0x00200000) /*!< Receiver Interrupt Enable */ +#define LPUARTx_CTRL_ILIE ((uint32_t)0x00100000) /*!< Idle Line Interrupt Enable */ +#define LPUARTx_CTRL_TE ((uint32_t)0x00080000) /*!< Transmitter Enable */ +#define LPUARTx_CTRL_RE ((uint32_t)0x00040000) /*!< Receiver Enable */ +#define LPUARTx_CTRL_RWU ((uint32_t)0x00020000) /*!< Receiver Wakeup Control */ +#define LPUARTx_CTRL_SBK ((uint32_t)0x00010000) /*!< Send Break */ +#define LPUARTx_CTRL_MA1IE ((uint32_t)0x00008000) /*!< Match 1 Interrupt Enable */ +#define LPUARTx_CTRL_MA2IE ((uint32_t)0x00004000) /*!< Match 2 Interrupt Enable */ +#define LPUARTx_CTRL_IDLECFG_SHIFT 8 /*!< Idle Configuration (shift) */ +#define LPUARTx_CTRL_IDLECFG_MASK ((uint32_t)((uint32_t)0x7 << LPUARTx_CTRL_IDLECFG_SHIFT)) /*!< Idle Configuration (mask) */ +#define LPUARTx_CTRL_IDLECFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_CTRL_IDLECFG_SHIFT) & LPUARTx_CTRL_IDLECFG_MASK)) /*!< Idle Configuration */ +#define LPUARTx_CTRL_LOOPS ((uint32_t)0x00000080) /*!< Loop Mode Select */ +#define LPUARTx_CTRL_DOZEEN ((uint32_t)0x00000040) /*!< Doze Enable */ +#define LPUARTx_CTRL_RSRC ((uint32_t)0x00000020) /*!< Receiver Source Select */ +#define LPUARTx_CTRL_M ((uint32_t)0x00000010) /*!< 9-Bit or 8-Bit Mode Select */ +#define LPUARTx_CTRL_WAKE ((uint32_t)0x00000008) /*!< Receiver Wakeup Method Select */ +#define LPUARTx_CTRL_ILT ((uint32_t)0x00000004) /*!< Idle Line Type Select */ +#define LPUARTx_CTRL_PE ((uint32_t)0x00000002) /*!< Parity Enable */ +#define LPUARTx_CTRL_PT ((uint32_t)0x00000001) /*!< Parity Type */ + +/********* Bits definition for LPUARTx_DATA register **********/ +#define LPUARTx_DATA_NOISY ((uint32_t)0x00008000) /*!< The current received dataword contained in DATA[R9:R0] was received with noise */ +#define LPUARTx_DATA_PARITYE ((uint32_t)0x00004000) /*!< The current received dataword contained in DATA[R9:R0] was received with a parity error */ +#define LPUARTx_DATA_FRETSC ((uint32_t)0x00002000) /*!< Frame Error / Transmit Special Character */ +#define LPUARTx_DATA_RXEMPT ((uint32_t)0x00001000) /*!< Receive Buffer Empty */ +#define LPUARTx_DATA_IDLINE ((uint32_t)0x00000800) /*!< Idle Line */ +#define LPUARTx_DATA_R9T9 ((uint32_t)0x00000200) /*!< Read receive data buffer 9 or write transmit data buffer 9 */ +#define LPUARTx_DATA_R8T8 ((uint32_t)0x00000100) /*!< Read receive data buffer 8 or write transmit data buffer 8 */ +#define LPUARTx_DATA_R7T7 ((uint32_t)0x00000080) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define LPUARTx_DATA_R6T6 ((uint32_t)0x00000040) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define LPUARTx_DATA_R5T5 ((uint32_t)0x00000020) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define LPUARTx_DATA_R4T4 ((uint32_t)0x00000010) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define LPUARTx_DATA_R3T3 ((uint32_t)0x00000008) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define LPUARTx_DATA_R2T2 ((uint32_t)0x00000004) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define LPUARTx_DATA_R1T1 ((uint32_t)0x00000002) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define LPUARTx_DATA_R0T0 ((uint32_t)0x00000001) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define LPUARTx_DATA_DATA_SHIFT 0 /*!< Data (shift) */ +#define LPUARTx_DATA_DATA_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_DATA_DATA_SHIFT)) /*!< Data (mask) */ +#define LPUARTx_DATA_DATA(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_DATA_DATA_SHIFT) & LPUARTx_DATA_DATA_MASK)) /*!< Data */ + +/********* Bits definition for LPUARTx_MATCH register *********/ +#define LPUARTx_MATCH_MA2_SHIFT 16 /*!< Match Address 2 (shift) */ +#define LPUARTx_MATCH_MA2_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA2_SHIFT)) /*!< Match Address 2 (mask) */ +#define LPUARTx_MATCH_MA2(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA2_SHIFT) & LPUARTx_MATCH_MA2_MASK)) /*!< Match Address 2 */ +#define LPUARTx_MATCH_MA1_SHIFT 0 /*!< Match Address 1 (shift) */ +#define LPUARTx_MATCH_MA1_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA1_SHIFT)) /*!< Match Address 1 (mask) */ +#define LPUARTx_MATCH_MA1(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA1_SHIFT) & LPUARTx_MATCH_MA1_MASK)) /*!< Match Address 1 */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_POL register **************/ +#define TPMx_POL_POL5 ((uint32_t)0x20) /*!< Channel 5 Polarity */ +#define TPMx_POL_POL4 ((uint32_t)0x10) /*!< Channel 4 Polarity */ +#define TPMx_POL_POL3 ((uint32_t)0x08) /*!< Channel 3 Polarity */ +#define TPMx_POL_POL2 ((uint32_t)0x04) /*!< Channel 2 Polarity */ +#define TPMx_POL_POL1 ((uint32_t)0x02) /*!< Channel 1 Polarity */ +#define TPMx_POL_POL0 ((uint32_t)0x01) /*!< Channel 0 Polarity */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_TRGSRC ((uint32_t)0x800000) /*!< Trigger Source */ +#define TPMx_CONF_TRGPOL ((uint32_t)0x400000) /*!< Trigger Polarity */ +#define TPMx_CONF_CPOT ((uint32_t)0x80000) /*!< Counter Pause On Trigger */ +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_GTBSYNC ((uint32_t)0x100) /*!< Global Time Base Synchronization */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USBFS: Device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USB_CLK_RECOVERY_INT ((uint8_t)0x04) /* Combined USB Clock Recovery interrupt status */ + +/****** Bits definition for USBx_CLK_RECOVER_CTRL register ******/ +#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN ((uint8_t)0x80) /*!< Crystal-less USB enable */ +#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN ((uint8_t)0x40) /*!< Reset/resume to rough phase enable */ +#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN ((uint8_t)0x20) /*!< Restart from IFR trim value */ + +/****** Bits definition for USBx_CLK_RECOVER_IRC_EN register ****/ +#define USBx_CLK_RECOVER_IRC_EN_IRC_EN ((uint8_t)0x02) /*!< IRC48M enable */ + +/****** Bits definition for USBx_CLK_RECOVER_INT_EN register ****/ +#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN ((uint8_t)0x10) /*!< Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. */ + +/*** Bits definition for USBx_CLK_RECOVER_INT_STATUS register ***/ +#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR ((uint8_t)0x10) /*!< frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ +/* Device independent parts, plus: */ +/*********** Bits definition for RCM_FM register ****************/ +#define RCM_FM_FORCEROM_SHIFT 1 /*!< Force ROM Boot */ +#define RCM_FM_FORCEROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_FM_FORCEROM_SHIFT)) +#define RCM_FM_FORCEROM(x) ((uint8_t)(((uint8_t)(x) << RCM_FM_FORCEROM_SHIFT) & RCM_FM_FORCEROM_MASK)) + +/*********** Bits definition for RCM_MR register ****************/ +#define RCM_MR_BOOTROM_SHIFT 1 /*!< Boot ROM Configuration */ +#define RCM_MR_BOOTROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_MR_BOOTROM_SHIFT)) +#define RCM_MR_BOOTROM(x) ((uint8_t)(((uint8_t)(x) << RCM_MR_BOOTROM_SHIFT) & RCM_MR_BOOTROM_MASK)) +#define RCM_MR_BOOTROM_FROM_FLASH RCM_MR_BOOTROM(0) +#define RCM_MR_BOOTROM_FROM_ROM_BOOTCFG0 RCM_MR_BOOTROM(1) +#define RCM_MR_BOOTROM_FROM_ROM_FOPT RCM_MR_BOOTROM(2) +#define RCM_MR_BOOTROM_FROM_ROM_BOTH RCM_MR_BOOTROM(3) + +/********** Bits definition for RCM_SSRS0 register ************/ +#define RCM_SSRS0_SPOR ((uint8_t)0x80) /*!< Sticky Power-On Reset */ +#define RCM_SSRS0_SPIN ((uint8_t)0x40) /*!< Sticky External Reset Pin */ +#define RCM_SSRS0_SWDOG ((uint8_t)0x20) /*!< Sticky Watchdog */ +#define RCM_SSRS0_SLVD ((uint8_t)0x02) /*!< Sticky Low-Voltage Detect Reset */ +#define RCM_SSRS0_SWAKEUP ((uint8_t)0x01) /*!< Sticky Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SSRS1 register *************/ +#define RCM_SSRS1_SSACKERR ((uint8_t)0x20) /*!< Sticky Stop Mode Acknowledge Error Reset */ +#define RCM_SSRS1_SMDM_AP ((uint8_t)0x08) /*!< Sticky MDM-AP System Reset Request */ +#define RCM_SSRS1_SSW ((uint8_t)0x04) /*!< Sticky Software */ +#define RCM_SSRS1_SLOCKUP ((uint8_t)0x02) /*!< Sticky Core Lockup */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 1 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x03 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0x0 +#define DACx_C1_DACBFMD_MODE_OTS 0x2 +#define DACx_C1_DACBFMD_MODE_FIFO 0x3 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Voltage Reference (VREFV1) */ +/* */ +/****************************************************************/ +/********** Bits definition for VREF_TRM register ***************/ +#define VREF_TRM_CHOPEN ((uint8_t)0x40) /*!< Chop oscillator enable. */ +#define VREF_TRM_TRIM_SHIFT 0 /*!< Trim bits */ +#define VREF_TRM_TRIM_MASK ((uint8_t)((uint8_t)0x3F << VREF_TRM_TRIM_SHIFT)) +#define VREF_TRM_TRIM(x) ((uint8_t)(((uint8_t)(x) << VREF_TRM_TRIM_SHIFT) & VREF_TRM_TRIM_MASK)) + +/********** Bits definition for VREF_SC register ****************/ +#define VREF_SC_VREFEN ((uint8_t)0x80) /*!< Internal Voltage Reference enable */ +#define VREF_SC_REGEN ((uint8_t)0x40) /*!< Regulator enable */ +#define VREF_SC_ICOMPEN ((uint8_t)0x20) /*!< Second order curvature compensation enable */ +#define VREF_SC_VREFST ((uint8_t)0x04) /*!< Internal Voltage Reference stable */ +#define VREF_SC_MODE_LV_SHIFT 0 /*!< Buffer Mode selection */ +#define VREF_SC_MODE_LV_MASK ((uint8_t)((uint8_t)0x3 << VREF_SC_MODE_LV_SHIFT)) +#define VREF_SC_MODE_LV(x) ((uint8_t)(((uint8_t)(x) << VREF_SC_MODE_LV_SHIFT) & VREF_SC_MODE_LV_MASK)) + +#define VREF_SC_MODE_LV_BANDGAP_ONLY VREF_SC_MODE_LV(0) +#define VREF_SC_MODE_LV_HIGH_POWER VREF_SC_MODE_LV(1) +#define VREF_SC_MODE_LV_LOW_POWER VREF_SC_MODE_LV(2) + +#endif /* _KL27ZXXX_H_ */ diff --git a/os/common/ext/CMSIS/KINETIS/kl2xz.h b/os/common/ext/CMSIS/KINETIS/kl2xz.h new file mode 100644 index 0000000..1ff29b1 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/kl2xz.h @@ -0,0 +1,1142 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL2xZ_H_ +#define _KL2xZ_H_ + +/* + * Include the correct MCU specific header + */ +#if defined(KL25) /* MKL25Z* MCUs */ +#include "kl25z.h" +#elif defined(KL26) /* MKL26Z* MCUs */ +#include "kl26z.h" +#elif defined(KL27Zxxx) /* MKL25Z128* and MKL27Z256* MCUs */ +#include "kl27zxxx.h" +#elif defined(KL27Zxx) /* MKL25Z32* and MKL27Z64* MCUs */ +#include "kl27zxx.h" +#else +#error Please select a supported target MCU in your board.h +#endif + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ + +/* Device dependent */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + __I uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __IO uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + uint32_t RESERVED5[1]; + __IO uint32_t FCFG1; + __IO uint32_t FCFG2; + uint32_t RESERVED6[1]; + __IO uint32_t UIDMH; + __IO uint32_t UIDML; + __IO uint32_t UIDL; + uint32_t RESERVED7[39]; + __IO uint32_t COPC; + __IO uint32_t SRVCOP; +} SIM_TypeDef; + +typedef struct +{ + __IO uint8_t PE1; + __IO uint8_t PE2; + __IO uint8_t PE3; + __IO uint8_t PE4; + __IO uint8_t ME; + __IO uint8_t F1; + __IO uint8_t F2; + __I uint8_t F3; + __IO uint8_t FILT1; + __IO uint8_t FILT2; +} LLWU_TypeDef; + +typedef struct +{ + __IO uint32_t PCR[32]; + __IO uint32_t GPCLR; + __IO uint32_t GPCHR; + uint32_t RESERVED0[6]; + __IO uint32_t ISFR; +} PORT_TypeDef; + +/* Device dependent + MCG_TypeDef; +*/ + +typedef struct +{ + __IO uint8_t CR; +} OSC_TypeDef; + +typedef struct +{ + __IO uint32_t SAR; + __IO uint32_t DAR; + __IO uint32_t DSR_BCR; + __IO uint32_t DCR; +} DMAChannel_TypeDef; + +typedef struct +{ + DMAChannel_TypeDef ch[4]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint8_t CHCFG[4]; +} DMAMUX_TypeDef; + +typedef struct { + __IO uint32_t MCR; /* PIT Module Control Register */ + __I uint32_t LTMR64H; /* PIT Module Control Register */ + __I uint32_t LTMR64L; /* PIT Lower Lifetime Timer Register */ + uint8_t RESERVED0[244]; + struct PIT_CHANNEL { + __IO uint32_t LDVAL; /* Timer Load Value Register */ + __I uint32_t CVAL; /* Current Timer Value Register */ + __IO uint32_t TCTRL; /* Timer Control Register */ + __IO uint32_t TFLG; /* Timer Flag Register */ + } CHANNEL[2]; +} PIT_TypeDef; + +/* Device dependent + TPM_TypeDef; +*/ + +typedef struct +{ + __IO uint32_t SC1A; // ADC Status and Control Registers 1 + __IO uint32_t SC1B; // ADC Status and Control Registers 1 + __IO uint32_t CFG1; // ADC Configuration Register 1 + __IO uint32_t CFG2; // ADC Configuration Register 2 + __I uint32_t RA; // ADC Data Result Register + __I uint32_t RB; // ADC Data Result Register + __IO uint32_t CV1; // Compare Value Registers + __IO uint32_t CV2; // Compare Value Registers + __IO uint32_t SC2; // Status and Control Register 2 + __IO uint32_t SC3; // Status and Control Register 3 + __IO uint32_t OFS; // ADC Offset Correction Register + __IO uint32_t PG; // ADC Plus-Side Gain Register + __IO uint32_t MG; // ADC Minus-Side Gain Register + __IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register + uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t PSR; + __IO uint32_t CMR; + __I uint32_t CNR; +} LPTMR_TypeDef; + +/* Device dependent (TSI or FlexIO) + TSI_TypeDef; +*/ + +typedef struct +{ + __IO uint32_t PDOR; + __IO uint32_t PSOR; + __IO uint32_t PCOR; + __IO uint32_t PTOR; + __IO uint32_t PDIR; + __IO uint32_t PDDR; +} GPIO_TypeDef; + +/* Device dependent + SPI_TypeDef; +*/ + +/* Device dependent + I2C_TypeDef; +*/ + +/* Device dependent + UART_TypeDef; +*/ + +/* Device dependent + LPUART_Typedef; +*/ + +typedef struct +{ + __IO uint8_t LVDSC1; + __IO uint8_t LVDSC2; + __IO uint8_t REGSC; +} PMC_TypeDef; + +/* Device dependent + USBOTG_TypeDef; +*/ + +/* Device dependent + RCM_TypeDef; +*/ + +typedef struct +{ + __IO uint8_t PMPROT; + __IO uint8_t PMCTRL; + __IO uint8_t STOPCTRL; + __I uint8_t PMSTAT; +} SMC_TypeDef; + +typedef struct +{ + struct { + __IO uint8_t DATL; + __IO uint8_t DATH; + } DAT[2]; + uint8_t RESERVED0[28]; + __IO uint8_t SR; + __IO uint8_t C0; + __IO uint8_t C1; + __IO uint8_t C2; +} DAC_TypeDef; + +typedef struct +{ + __IO uint32_t TSR; + __IO uint32_t TPR; + __IO uint32_t TAR; + __IO uint32_t TCR; + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t LR; + __IO uint32_t IER; +} RTC_TypeDef; + +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t FPR; + __IO uint8_t SCR; + __IO uint8_t DACCR; + __IO uint8_t MUXCR; +} CMP_TypeDef; + +typedef struct +{ + __IO uint8_t FSTAT; + __IO uint8_t FCNFG; + __I uint8_t FSEC; + __I uint8_t FOPT; + __IO uint8_t FCCOB3; + __IO uint8_t FCCOB2; + __IO uint8_t FCCOB1; + __IO uint8_t FCCOB0; + __IO uint8_t FCCOB7; + __IO uint8_t FCCOB6; + __IO uint8_t FCCOB5; + __IO uint8_t FCCOB4; + __IO uint8_t FCCOBB; + __IO uint8_t FCCOBA; + __IO uint8_t FCCOB9; + __IO uint8_t FCCOB8; + __IO uint8_t FPROT3; + __IO uint8_t FPROT2; + __IO uint8_t FPROT1; + __IO uint8_t FPROT0; +} FTFA_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[2]; + __I uint16_t PLASC; // 0x08 + __I uint16_t PLAMC; // 0x0A + __IO uint32_t PLACR; // 0x0C + uint32_t RESERVED1[12]; + __IO uint32_t CPO; // 0x40 +} MCM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ +/********** Bits definition for LLWU_PE1 register *************/ +#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ +#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ +#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ +#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ +#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ +#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ +#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ +#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ +#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ +#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ +#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ +#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ + +/********** Bits definition for LLWU_PE2 register *************/ +#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ +#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ +#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ +#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ +#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ +#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ +#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ +#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ +#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ +#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ +#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ +#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ + +/********** Bits definition for LLWU_PE3 register *************/ +#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ +#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ +#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ +#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ +#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ +#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ +#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ +#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ +#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ +#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ +#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ +#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ + +/********** Bits definition for LLWU_PE4 register *************/ +#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ +#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ +#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ +#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ +#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ +#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ +#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ +#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ +#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ +#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ +#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ +#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ + +/********** Bits definition for LLWU_ME register *************/ +#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ +#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ +#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ +#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ +#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ +#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ +#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ +#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ + +/********** Bits definition for LLWU_F1 register *************/ +#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ +#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ +#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ +#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ +#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ +#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ +#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ +#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ + +/********** Bits definition for LLWU_F2 register *************/ +#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ +#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ +#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ +#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ +#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ +#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ +#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ +#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ + +/********** Bits definition for LLWU_F3 register *************/ +#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ +#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ +#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ +#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ +#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ +#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ +#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ +#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ + +/********** Bits definition for LLWU_FILT1 register *************/ +#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/********** Bits definition for LLWU_FILT2 register *************/ +#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ +/******** Bits definition for PORTx_PCRn register *************/ +#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ +#define PORTx_PCRn_IRQC_SHIFT 16 +#define PORTx_PCRn_IRQC_MASK ((uint32_t)0x000F0000) /*!< Interrupt Configuration */ +#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) +#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ +#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */ +#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ +#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ +#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ +#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ +#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ +#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for OSC_CR register **************/ +#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ +#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ +#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ +#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ +#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ +#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ +/*********** Bits definition for DMA_BCRn register ************/ +#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */ +#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */ +#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */ +#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */ +#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */ +#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */ +#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */ +#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */ +#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */ + +/*********** Bits definition for DMA_DCRn register ************/ +#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */ +#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */ +#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */ +#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */ +#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */ +#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */ +#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */ +#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */ +#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */ +#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */ +#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */ +#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */ +#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */ +#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */ +#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */ +#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */ +#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */ +#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */ +#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */ +#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */ +#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */ +#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */ +#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */ +#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */ +#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */ +#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */ +#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */ +#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */ +#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */ +#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ +/******** Bits definition for DMAMUX_CHCFGn register **********/ +#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ +#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ +#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ +#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ +#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ +/*********** Bits definition for PIT_MCR register *************/ +#define PIT_MCR_MDIS ((uint32_t)((uint32_t)1 << 1)) /*!< Module Disable */ +#define PIT_MCR_FRZ ((uint32_t)((uint32_t)1 << 0)) /*!< Freeze */ +/********** Bits definition for PIT_LDVALn register ***********/ +#define PIT_LDVALn_TSV_SHIFT 0 /*!< Timer Start Value */ +#define PIT_LDVALn_TSV_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << PIT_LDVALn_TSV_SHIFT)) +#define PIT_LDVALn_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVALn_TSV_SHIFT))&PIT_LDVALn_TSV_MASK) +/********** Bits definition for PIT_CVALn register ************/ +#define PIT_CVALn_TVL_SHIFT 0 /*!< Current Timer Value */ +#define PIT_CVALn_TVL_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << PIT_CVALn_TVL_SHIFT)) +#define PIT_CVALn_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVALn_TVL_SHIFT))&PIT_CVALn_TVL_MASK) +/********** Bits definition for PIT_TCTRLn register ***********/ +#define PIT_TCTRLn_CHN ((uint32_t)((uint32_t)1 << 2)) /*!< Chain Mode */ +#define PIT_TCTRLn_TIE ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Interrupt Enable */ +#define PIT_TCTRLn_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ +/********** Bits definition for PIT_TFLGn register ************/ +#define PIT_TFLGn_TIF ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Interrupt Flag */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for ADCx_SC1n register ***********/ +#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ +#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ +#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ +#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ +#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ +#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ + +/*********** Bits definition for ADCx_CFG1 register ***********/ +#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ +#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ +#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ +#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ +#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ +#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ +#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ +#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ +#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ +#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ +#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ + +/*********** Bits definition for ADCx_CFG2 register ***********/ +#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ +#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ +#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ +#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ +#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ +#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ + +/*********** Bits definition for ADCx_SC2 register ***********/ +#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ +#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ +#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ +#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ +#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ +#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ +#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ +#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ +#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ + +/*********** Bits definition for ADCx_SC3 register ***********/ +#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ +#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ +#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ +#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ +#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ +#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ +#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ +/********** Bits definition for LPTMRx_CSR register ***********/ +#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ +#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ +#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ +#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ +#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ +#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ +#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ +#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ +#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ + +/********** Bits definition for LPTMRx_PSR register ***********/ +#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ +#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ +#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ +#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ +#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ +#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ +#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ + +/********** Bits definition for LPTMRx_CMR register ***********/ +#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ +#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ +#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ + +/********** Bits definition for LPTMRx_CNR register ***********/ +#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ +#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ +#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ +#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ +#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ +#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ +#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ +#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ +#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ +#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +/********* Bits definition for PMC_REGSC register *************/ +#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ +#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ +#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ +#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* USB/OTG or FS: Device independent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IEHOST ((uint8_t)0x01) /*!< Host mode operation? */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPHIGH ((uint8_t)0x80) /*!< D+ Data Line pullup resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ +#define USBx_ISTAT_RESUME ((uint8_t)0x20) /*!< Signal remote wakeup on the bus */ +#define USBx_ISTAT_SLEEP ((uint8_t)0x10) /*!< Detected bus idle for 3ms */ +#define USBx_ISTAT_TOKDNE ((uint8_t)0x08) /*!< Completed processing of current token */ +#define USBx_ISTAT_SOFTOK ((uint8_t)0x04) /*!< Received start of frame */ +#define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ +#define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ +#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ +#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ +#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ +#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ +#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ +#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ + +/******** Bits definition for USBx_ERRSTAT register ***********/ +#define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ +#define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ +#define USBx_ERRSTAT_BTOERR ((uint8_t)0x10) /*!< BUS turnaround timeout error */ +#define USBx_ERRSTAT_DFN8 ((uint8_t)0x08) /*!< Received data not 8-bit sized */ +#define USBx_ERRSTAT_CRC16 ((uint8_t)0x04) /*!< Packet with CRC16 error */ +#define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ +#define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ + +/******** Bits definition for USBx_ERREN register ************/ +#define USBx_ERREN_BTSERREN ((uint8_t)0x80) /*!< BTSERR Interrupt Enable */ +#define USBx_ERREN_DMAERREN ((uint8_t)0x20) /*!< DMAERR Interrupt Enable */ +#define USBx_ERREN_BTOERREN ((uint8_t)0x10) /*!< BTOERR Interrupt Enable */ +#define USBx_ERREN_DFN8EN ((uint8_t)0x08) /*!< DFN8 Interrupt Enable */ +#define USBx_ERREN_CRC16EN ((uint8_t)0x04) /*!< CRC16 Interrupt Enable */ +#define USBx_ERREN_CRC5EOFEN ((uint8_t)0x02) /*!< CRC5/EOF Interrupt Enable */ +#define USBx_ERREN_PIDERREN ((uint8_t)0x01) /*!< PIDERR Interrupt Enable */ + +/******** Bits definition for USBx_STAT register *************/ +#define USBx_STAT_ENDP_MASK ((uint8_t)0xF0) /*!< Endpoint address mask*/ +#define USBx_STAT_ENDP_SHIFT ((uint8_t)0x04) /*!< Endpoint address shift*/ +#define USBx_STAT_TX_MASK ((uint8_t)0x08) /*!< Transmit indicator mask*/ +#define USBx_STAT_TX_SHIFT ((uint8_t)0x03) /*!< Transmit indicator shift*/ +#define USBx_STAT_ODD_MASK ((uint8_t)0x04) /*!< EVEN/ODD bank indicator mask*/ +#define USBx_STAT_ODD_SHIFT ((uint8_t)0x02) /*!< EVEN/ODD bank indicator shift */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ +#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ +#define USBx_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) /*!< */ +#define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ +#define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_ADDR_SHIFT 0 /*!< USB Address */ +#define USBx_ADDR_ADDR_MASK ((uint8_t)0x7F) /*!< USB Address */ + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_EPCTLDIS ((uint8_t)0x10) /*!< Disables control transfers */ +#define USBx_ENDPTn_EPRXEN ((uint8_t)0x08) /*!< Enable RX transfers */ +#define USBx_ENDPTn_EPTXEN ((uint8_t)0x04) /*!< Enable TX transfers */ +#define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ +#define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ + +/******** Bits definition for USBx_USBCTRL register *************/ +#define USBx_USBCTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ +#define USBx_USBCTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ + +/******** Bits definition for USBx_OBSERVE register *************/ +#define USBx_OBSERVE_DPPU ((uint8_t)0x80) /*!< Provides observability of the D+ Pullup . signal output from the USB OTG module */ +#define USBx_OBSERVE_DPPD ((uint8_t)0x40) /*!< Provides observability of the D+ Pulldown . signal output from the USB OTG module */ +#define USBx_OBSERVE_DMPD ((uint8_t)0x10) /*!< Provides observability of the D- Pulldown signal output from the USB OTG module */ + +/******** Bits definition for USBx_CONTROL register *************/ +#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ + +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ +#define USBx_USBTRC0_USBRESMEN ((uint8_t)0x20) /*!< Asynchronous resume interrupt enable */ +#define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ +#define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM): Device independent parts */ +/* */ +/****************************************************************/ +/********** Bits definition for RCM_SRS0 register *************/ +#define RCM_SRS0_POR ((uint8_t)0x80) /*!< Power-On Reset */ +#define RCM_SRS0_PIN ((uint8_t)0x40) /*!< External Reset Pin */ +#define RCM_SRS0_WDOG ((uint8_t)0x20) /*!< Watchdog */ +#define RCM_SRS0_LOL ((uint8_t)0x08) /*!< Loss-of-Lock Reset */ +#define RCM_SRS0_LOC ((uint8_t)0x04) /*!< Loss-of-Clock Reset */ +#define RCM_SRS0_LVD ((uint8_t)0x02) /*!< Low-Voltage Detect Reset */ +#define RCM_SRS0_WAKEUP ((uint8_t)0x01) /*!< Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SRS1 register *************/ +#define RCM_SRS1_SACKERR ((uint8_t)0x20) /*!< Stop Mode Acknowledge Error Reset */ +#define RCM_SRS1_MDM_AP ((uint8_t)0x08) /*!< MDM-AP System Reset Request */ +#define RCM_SRS1_SW ((uint8_t)0x04) /*!< Software */ +#define RCM_SRS1_LOCKUP ((uint8_t)0x02) /*!< Core Lockup */ + +/********** Bits definition for RCM_RPFC register *************/ +#define RCM_RPFC_RSTFLTSS ((uint8_t)0x04) /*!< Reset Pin Filter Select in Stop Mode */ +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 /*!< Reset Pin Filter Select in Run and Wait Modes (shift) */ +#define RCM_RPFC_RSTFLTSRW_MASK ((uint8_t)((uint8_t)0x03 << RCM_RPFC_RSTFLTSRW_SHIFT)) /*!< Reset Pin Filter Select in Run and Wait Modes (mask) */ +#define RCM_RPFC_RSTFLTSRW(x) ((uint8_t)(((uint8_t)(x) << RCM_RPFC_RSTFLTSRW_SHIFT) & RCM_RPFC_RSTFLTSRW_MASK)) /*!< Reset Pin Filter Select in Run and Wait Modes */ + +/********** Bits definition for RCM_RPFW register *************/ +#define RCM_RPFW_RSTFLTSEL_SHIFT 0 /*!< Reset Pin Filter Bus Clock Select (shift) */ +#define RCM_RPFW_RSTFLTSEL_MASK ((uint8_t)((uint8_t)0x1F << RCM_RPFW_RSTFLTSEL_SHIFT)) /*!< Reset Pin Filter Bus Clock Select (mask) */ +#define RCM_RPFW_RSTFLTSEL(x) ((uint8_t)(((uint8_t)(x) << RCM_RPFW_RSTFLTSEL_SHIFT) & RCM_RPFW_RSTFLTSEL_MASK)) /*!< Reset Pin Filter Bus Clock Select */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for SMC_PMPROT register ************/ +#define SMC_PMPROT_AVLP ((uint8_t)0x20) /*!< Allow Very-Low-Power Modes */ +#define SMC_PMPROT_ALLS ((uint8_t)0x08) /*!< Allow Low-Leakage Stop Mode */ +#define SMC_PMPROT_AVLLS ((uint8_t)0x02) /*!< Allow Very-Low-Leakage Stop Mode */ + +/********* Bits definition for SMC_PMCTRL register ************/ +#define SMC_PMCTRL_RUNM_SHIFT 5 /*!< Run Mode Control (shift) */ +#define SMC_PMCTRL_RUNM_MASK ((uint8_t)((uint8_t)0x03 << SMC_PMCTRL_RUNM_SHIFT)) /*!< Run Mode Control (mask) */ +#define SMC_PMCTRL_RUNM(x) ((uint8_t)(((uint8_t)(x) << SMC_PMCTRL_RUNM_SHIFT) & SMC_PMCTRL_RUNM_MASK)) /*!< Run Mode Control */ +#define SMC_PMCTRL_STOPA ((uint8_t)0x08) /*!< Stop Aborted */ +#define SMC_PMCTRL_STOPM_SHIFT 0 /*!< Stop Mode Control (shift) */ +#define SMC_PMCTRL_STOPM_MASK ((uint8_t)((uint8_t)0x07 << SMC_PMCTRL_STOPM_SHIFT)) /*!< Stop Mode Control (mask) */ +#define SMC_PMCTRL_STOPM(x) ((uint8_t)(((uint8_t)(x) << SMC_PMCTRL_STOPM_SHIFT) & SMC_PMCTRL_STOPM_MASK)) /*!< Stop Mode Control */ + +#define SMC_PMCTRL_RUNM_RUN ((uint8_t)0x00) +#define SMC_PMCTRL_RUNM_VLPR ((uint8_t)0x02) +#define SMC_PMCTRL_STOPM_STOP ((uint8_t)0x00) +#define SMC_PMCTRL_STOPM_VLPS ((uint8_t)0x02) +#define SMC_PMCTRL_STOPM_LLS ((uint8_t)0x03) +#define SMC_PMCTRL_STOPM_VLLSx ((uint8_t)0x04) + +/******** Bits definition for SMC_STOPCTRL register ***********/ +#define SMC_STOPCTRL_PSTOPO_SHIFT 6 /*!< Partial Stop Option (shift) */ +#define SMC_STOPCTRL_PSTOPO_MASK ((uint8_t)((uint8_t)0x03 << SMC_STOPCTRL_PSTOPO_SHIFT)) /*!< Partial Stop Option (mask) */ +#define SMC_STOPCTRL_PSTOPO(x) ((uint8_t)(((uint8_t)(x) << SMC_STOPCTRL_PSTOPO_SHIFT) & SMC_STOPCTRL_PSTOPO_MASK)) /*!< Partial Stop Option */ +#define SMC_STOPCTRL_PORP0 ((uint8_t)0x20) /*!< POR Power Option */ +#define SMC_STOPCTRL_VLLSM_SHIFT 0 /*!< VLLS Mode Control (shift) */ +#define SMC_STOPCTRL_VLLSM_MASK ((uint8_t)((uint8_t)0x07 << SMC_STOPCTRL_VLLSM_SHIFT)) /*!< VLLS Mode Control (mask) */ +#define SMC_STOPCTRL_VLLSM(x) ((uint8_t)(((uint8_t)(x) << SMC_STOPCTRL_VLLSM_SHIFT) & SMC_STOPCTRL_VLLSM_MASK)) /*!< VLLS Mode Control */ + +#define SMC_STOPCTRL_PSTOPO_STOP ((uint8_t)0x00) +#define SMC_STOPCTRL_PSTOPO_PSTOP1 ((uint8_t)0x01) +#define SMC_STOPCTRL_PSTOPO_PSTOP2 ((uint8_t)0x02) +#define SMC_STOPCTRL_VLLSM_VLLS0 ((uint8_t)0x00) +#define SMC_STOPCTRL_VLLSM_VLLS1 ((uint8_t)0x01) +#define SMC_STOPCTRL_VLLSM_VLLS2 ((uint8_t)0x03) + +/********* Bits definition for SMC_PMSTAT register ************/ +#define SMC_PMSTAT_PMSTAT_SHIFT 0 /*!< Power Mode Status (shift) */ +#define SMC_PMSTAT_PMSTAT_MASK ((uint8_t)((uint8_t)0x7F << SMC_PMSTAT_PMSTAT_SHIFT)) /*!< Power Mode Status (mask) */ +#define SMC_PMSTAT_PMSTAT(x) ((uint8_t)(((uint8_t)(x) << SMC_PMSTAT_PMSTAT_SHIFT) & SMC_PMSTAT_PMSTAT_MASK)) /*!< Power Mode Status */ + +#define SMC_PMSTAT_RUN ((uint8_t)0x01) +#define SMC_PMSTAT_STOP ((uint8_t)0x02) +#define SMC_PMSTAT_VLPR ((uint8_t)0x04) +#define SMC_PMSTAT_VLPW ((uint8_t)0x08) +#define SMC_PMSTAT_VLPS ((uint8_t)0x10) +#define SMC_PMSTAT_LLS ((uint8_t)0x20) +#define SMC_PMSTAT_VLLS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ +/********* Bits definition for DACx_DATnL register ************/ +#define DACx_DATnL_DATA_SHIFT 0 /*!< DAC Data Low Register (shift) */ +#define DACx_DATnL_DATA_MASK ((uint8_t)((uint8_t)0xFF << DACx_DATnL_DATA_SHIFT)) /*!< DAC Data Low Register (mask) */ +#define DACx_DATnL_DATA(x) ((uint8_t)(((uint8_t)(x) << DACx_DATnL_DATA_SHIFT) & DACx_DATnL_DATA_MASK)) /*!< DAC Data Low Register */ + +/********* Bits definition for DACx_DATnH register ************/ +#define DACx_DATnH_DATA_SHIFT 0 /*!< DAC Data High Register (shift) */ +#define DACx_DATnH_DATA_MASK ((uint8_t)((uint8_t)0x0F << DACx_DATnH_DATA_SHIFT)) /*!< DAC Data High Register (mask) */ +#define DACx_DATnH_DATA(x) ((uint8_t)(((uint8_t)(x) << DACx_DATnH_DATA_SHIFT) & DACx_DATnH_DATA_MASK)) /*!< DAC Data High Register */ + +/********** Bits definition for DACx_SR register **************/ +#define DACx_SR_DACBFRPTF ((uint8_t)0x02) /*!< DAC Buffer Read Pointer Top Position Flag */ +#define DACx_SR_DACBFRPBF ((uint8_t)0x01) /*!< DAC Buffer Read Pointer Bottom Position Flag */ + +/********** Bits definition for DACx_C0 register **************/ +#define DACx_C0_DACEN ((uint8_t)0x80) /*!< DAC Enable */ +#define DACx_C0_DACRFS ((uint8_t)0x40) /*!< DAC Reference Select */ +#define DACx_C0_DACTRGSEL ((uint8_t)0x20) /*!< DAC Trigger Select */ +#define DACx_C0_DACSWTRG ((uint8_t)0x10) /*!< DAC Software Trigger */ +#define DACx_C0_LPEN ((uint8_t)0x08) /*!< DAC Low Power Control */ +#define DACx_C0_DACBTIEN ((uint8_t)0x02) /*!< DAC Buffer Read Pointer Top Flag Interrupt Enable */ +#define DACx_C0_DACBBIEN ((uint8_t)0x01) /*!< DAC Buffer Read Pointer Bottom Flag Interrupt Enable */ + +/********** Bits definition for DACx_C1 register **************/ +#define DACx_C1_DMAEN ((uint8_t)0x80) /*!< DMA Enable Select */ +/* Device dependent bits */ +/* #define DACx_C1_DACBFMD ((uint8_t)0x04)*//*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFEN ((uint8_t)0x01) /*!< DAC Buffer Enable */ + +/********** Bits definition for DACx_C2 register **************/ +#define DACx_C2_DACBFRP ((uint8_t)0x10) /*!< DAC Buffer Read Pointer */ +#define DACx_C2_DACBFUP ((uint8_t)0x01) /*!< DAC Buffer Upper Limit */ + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ +/********** Bits definition for RTC_TSR register **************/ +#define RTC_TSR_TSR_SHIFT 0 /*!< RTC Time Seconds Register (shift) */ +#define RTC_TSR_TSR_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << RTC_TSR_TSR_SHIFT)) /*!< RTC Time Seconds Register (mask) */ +#define RTC_TSR_TSR(x) ((uint32_t)(((uint32_t)(x) << RTC_TSR_TSR_SHIFT) & RTC_TSR_TSR_MASK)) /*!< RTC Time Seconds Register */ + +/********** Bits definition for RTC_TPR register **************/ +#define RTC_TPR_TPR_SHIFT 0 /*!< RTC Time Prescaler Register (shift) */ +#define RTC_TPR_TPR_MASK ((uint32_t)((uint32_t)0xFFFF << RTC_TPR_TPR_SHIFT)) /*!< RTC Time Prescaler Register (mask) */ +#define RTC_TPR_TPR(x) ((uint32_t)(((uint32_t)(x) << RTC_TPR_TPR_SHIFT) & RTC_TPR_TPR_MASK)) /*!< RTC Time Prescaler Register */ + +/********** Bits definition for RTC_TAR register **************/ +#define RTC_TAR_TAR_SHIFT 0 /*!< RTC Time Alarm Register (shift) */ +#define RTC_TAR_TAR_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << RTC_TAR_TAR_SHIFT)) /*!< RTC Time Alarm Register (mask) */ +#define RTC_TAR_TAR(x) ((uint32_t)(((uint32_t)(x) << RTC_TAR_TAR_SHIFT) & RTC_TAR_TAR_MASK)) /*!< RTC Time Alarm Register */ + +/********** Bits definition for RTC_TCR register **************/ +#define RTC_TCR_CIC_SHIFT 24 /*!< Compensation Interval Counter (shift) */ +#define RTC_TCR_CIC_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_CIC_SHIFT)) /*!< Compensation Interval Counter (mask) */ +#define RTC_TCR_CIC(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_CIC_SHIFT) & RTC_TCR_CIC_MASK)) /*!< Compensation Interval Counter */ +#define RTC_TCR_TCV_SHIFT 16 /*!< Time Compensation Value (shift) */ +#define RTC_TCR_TCV_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_TCV_SHIFT)) /*!< Time Compensation Value (mask) */ +#define RTC_TCR_TCV(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_TCV_SHIFT) & RTC_TCR_TCV_MASK)) /*!< Time Compensation Value */ +#define RTC_TCR_CIR_SHIFT 8 /*!< Compensation Interval Register (shift) */ +#define RTC_TCR_CIR_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_CIR_SHIFT)) /*!< Compensation Interval Register (mask) */ +#define RTC_TCR_CIR(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_CIR_SHIFT) & RTC_TCR_CIR_MASK)) /*!< Compensation Interval Register */ +#define RTC_TCR_TCR_SHIFT 0 /*!< Time Compensation Register (shift) */ +#define RTC_TCR_TCR_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_TCR_SHIFT)) /*!< Time Compensation Register (mask) */ +#define RTC_TCR_TCR(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_TCR_SHIFT) & RTC_TCR_TCR_MASK)) /*!< Time Compensation Register */ + +/*********** Bits definition for RTC_CR register **************/ +#define RTC_CR_SC2P ((uint32_t)0x2000) /*!< Oscillator 2pF Load Configure */ +#define RTC_CR_SC4P ((uint32_t)0x1000) /*!< Oscillator 4pF Load Configure */ +#define RTC_CR_SC8P ((uint32_t)0x0800) /*!< Oscillator 8pF Load Configure */ +#define RTC_CR_SC16P ((uint32_t)0x0400) /*!< Oscillator 16pF Load Configure */ +#define RTC_CR_CLKO ((uint32_t)0x0200) /*!< Clock Output */ +#define RTC_CR_OSCE ((uint32_t)0x0100) /*!< Oscillator Enable */ +#define RTC_CR_WPS ((uint32_t)0x0010) /*!< Wakeup Pin Select */ +#define RTC_CR_UM ((uint32_t)0x0008) /*!< Update Mode */ +#define RTC_CR_SUP ((uint32_t)0x0004) /*!< Supervisor Access */ +#define RTC_CR_WPE ((uint32_t)0x0002) /*!< Wakeup Pin Enable */ +#define RTC_CR_SWR ((uint32_t)0x0001) /*!< Software Reset */ + +/*********** Bits definition for RTC_SR register **************/ +#define RTC_SR_TCE ((uint32_t)0x10) /*!< Time Counter Enable */ +#define RTC_SR_TAF ((uint32_t)0x04) /*!< Time Alarm Flag */ +#define RTC_SR_TOF ((uint32_t)0x02) /*!< Time Overflow Flag */ +#define RTC_SR_TIF ((uint32_t)0x01) /*!< Time Invalid Flag */ + +/*********** Bits definition for RTC_LR register **************/ +#define RTC_LR_LRL ((uint32_t)0x40) /*!< Lock Register Lock */ +#define RTC_LR_SRL ((uint32_t)0x20) /*!< Status Register Lock */ +#define RTC_LR_CRL ((uint32_t)0x10) /*!< Control Register Lock */ +#define RTC_LR_TCL ((uint32_t)0x08) /*!< Time Compensation Lock */ + +/********** Bits definition for RTC_IER register **************/ +#define RTC_IER_WPON ((uint32_t)0x80) /*!< Wakeup Pin On */ +#define RTC_IER_TSIE ((uint32_t)0x10) /*!< Time Seconds Interrupt Enable */ +#define RTC_IER_TAIE ((uint32_t)0x04) /*!< Time Alarm Interrupt Enable */ +#define RTC_IER_TOIE ((uint32_t)0x02) /*!< Time Overflow Interrupt Enable */ +#define RTC_IER_TIIE ((uint32_t)0x01) /*!< Time Invalid Interrupt Enable */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ +/********** Bits definition for CMP_CR0 register **************/ +#define CMP_CR0_FILTER_CNT_SHIFT 4 /*!< Filter Sample Count (shift) */ +#define CMP_CR0_FILTER_CNT_MASK ((uint8_t)((uint8_t)0x07 << CMP_CR0_FILTER_CNT_SHIFT)) /*!< Filter Sample Count (mask) */ +#define CMP_CR0_FILTER_CNT(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_FILTER_CNT_SHIFT) & CMP_CR0_FILTER_CNT_MASK)) /*!< Filter Sample Count */ +#define CMP_CR0_HYSTCTR_SHIFT 0 /*!< Comparator hard block hysteresis control (shift) */ +#define CMP_CR0_HYSTCTR_MASK ((uint8_t)((uint8_t)0x03 << CMP_CR0_HYSTCTR_SHIFT)) /*!< Comparator hard block hysteresis control (mask) */ +#define CMP_CR0_HYSTCTR(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_HYSTCTR_SHIFT) & CMP_CR0_HYSTCTR_MASK)) /*!< Comparator hard block hysteresis control */ + +/********** Bits definition for CMP_CR1 register **************/ +#define CMP_CR1_SE ((uint8_t)0x80) /*!< Sample Enable */ +#define CMP_CR1_WE ((uint8_t)0x40) /*!< Windowing Enable */ +#define CMP_CR1_TRIGM ((uint8_t)0x20) /*!< Trigger Mode Enable */ +#define CMP_CR1_PMODE ((uint8_t)0x10) /*!< Power Mode Select */ +#define CMP_CR1_INV ((uint8_t)0x08) /*!< Comparator INVERT */ +#define CMP_CR1_COS ((uint8_t)0x04) /*!< Comparator Output Select */ +#define CMP_CR1_OPE ((uint8_t)0x02) /*!< Comparator Output Pin Enable */ +#define CMP_CR1_EN ((uint8_t)0x01) /*!< Comparator Module Enable */ + +/********** Bits definition for CMP_FPR register **************/ +#define CMP_CR0_FILT_PER_SHIFT 0 /*!< Filter Sample Period (shift) */ +#define CMP_CR0_FILT_PER_MASK ((uint8_t)((uint8_t)0xFF << CMP_CR0_FILT_PER_SHIFT)) /*!< Filter Sample Period (mask) */ +#define CMP_CR0_FILT_PER(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_FILT_PER_SHIFT) & CMP_CR0_FILT_PER_MASK)) /*!< Filter Sample Period */ + +/********** Bits definition for CMP_SCR register **************/ +#define CMP_SCR_DMAEN ((uint8_t)0x40) /*!< DMA Enable Control */ +#define CMP_SCR_IER ((uint8_t)0x10) /*!< Comparator Interrupt Enable Rising */ +#define CMP_SCR_IEF ((uint8_t)0x08) /*!< Comparator Interrupt Enable Falling */ +#define CMP_SCR_CFR ((uint8_t)0x04) /*!< Analog Comparator Flag Rising */ +#define CMP_SCR_CFF ((uint8_t)0x02) /*!< Analog Comparator Flag Falling */ +#define CMP_SCR_COUT ((uint8_t)0x01) /*!< Analog Comparator Output */ + +/********** Bits definition for CMP_DACCR register ************/ +#define CMP_DACCR_DACEN ((uint8_t)0x80) /*!< DAC Enable */ +#define CMP_DACCR_VRSEL ((uint8_t)0x40) /*!< Supply Voltage Reference Source Select */ +#define CMP_DACCR_VOSEL_SHIFT 0 /*!< DAC Output Voltage Select (shift) */ +#define CMP_DACCR_VOSEL_MASK ((uint8_t)((uint8_t)0x3F << CMP_DACCR_VOSEL_SHIFT)) /*!< DAC Output Voltage Select (mask) */ +#define CMP_DACCR_VOSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_DACCR_VOSEL_SHIFT) & CMP_DACCR_VOSEL_MASK)) /*!< DAC Output Voltage Select */ + +/********** Bits definition for CMP_MUXCR register ************/ +#define CMP_MUXCR_PSTM ((uint8_t)0x80) /*!< Pass Through Mode Enable */ +#define CMP_MUXCR_PSEL_SHIFT 3 /*!< Plus Input Mux Control (shift) */ +#define CMP_MUXCR_PSEL_MASK ((uint8_t)((uint8_t)0x07 << CMP_MUXCR_PSEL_SHIFT)) /*!< Plus Input Mux Control (mask) */ +#define CMP_MUXCR_PSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_MUXCR_PSEL_SHIFT) & CMP_MUXCR_PSEL_MASK)) /*!< Plus Input Mux Control */ +#define CMP_MUXCR_MSEL_SHIFT 0 /*!< Minus Input Mux Control (shift) */ +#define CMP_MUXCR_MSEL_MASK ((uint8_t)((uint8_t)0x07 << CMP_MUXCR_MSEL_SHIFT)) /*!< Minus Input Mux Control (mask) */ +#define CMP_MUXCR_MSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_MUXCR_MSEL_SHIFT) & CMP_MUXCR_MSEL_MASK)) /*!< Minus Input Mux Control */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ +/********** Bits definition for FTFA_FSTAT register ***********/ +#define FTFA_FSTAT_CCIF ((uint8_t)0x80) /*!< Command Complete Interrupt Flag */ +#define FTFA_FSTAT_RDCOLERR ((uint8_t)0x40) /*!< Flash Read Collision Error Flag */ +#define FTFA_FSTAT_ACCERR ((uint8_t)0x20) /*!< Flash Access Error Flag */ +#define FTFA_FSTAT_FPVIOL ((uint8_t)0x10) /*!< Flash Protection Violation Flag */ +#define FTFA_FSTAT_MGSTAT0 ((uint8_t)0x01) /*!< Memory Controller Command Completion Status Flag */ + +/********** Bits definition for FTFA_FCNFG register ***********/ +#define FTFA_FCNFG_CCIE ((uint8_t)0x80) /*!< Command Complete Interrupt Enable */ +#define FTFA_FCNFG_RDCOLLIE ((uint8_t)0x40) /*!< Read Collision Error Interrupt Enable */ +#define FTFA_FCNFG_ERSAREQ ((uint8_t)0x20) /*!< Erase All Request */ +#define FTFA_FCNFG_ERSSUSP ((uint8_t)0x10) /*!< Erase Suspend */ + +/********** Bits definition for FTFA_FSEC register ************/ +#define FTFA_FSEC_KEYEN_MASK ((uint8_t)0xC0) /*!< Backdoor Key Security Enable */ +#define FTFA_FSEC_MEEN_MASK ((uint8_t)0x30) /*!< Mass Erase Enable Bits */ +#define FTFA_FSEC_FSLACC_MASK ((uint8_t)0x0C) /*!< Freescale Failure Analysis Access Code */ +#define FTFA_FSEC_SEC_MASK ((uint8_t)0x03) /*!< Flash Security */ +#define FTFA_FSEC_KEYEN_ENABLED ((uint8_t)0x80) +#define FTFA_FSEC_MEEN_DISABLED ((uint8_t)0x20) +#define FTFA_FSEC_SEC_UNSECURE ((uint8_t)0x02) + +/********** Bits definition for FTFA_FOPT register ************/ +#define FTFA_FOPT_BOOTSRC_SEL_MASK ((uint8_t)0xC0) /*!< Boot Source Selection */ +#define FTFA_FOPT_FAST_INIT ((uint8_t)0x20) /*!< Initialization Speed */ +#define FTFA_FOPT_RESET_PIN_CFG ((uint8_t)0x08) /*!< Enables/disables control for the RESET pin */ +#define FTFA_FOPT_NMI_DIS ((uint8_t)0x04) /*!< Enables/disables control for the NMI function */ +#define FTFA_FOPT_BOOTPIN_OPT ((uint8_t)0x02) /*!< External pin selects boot options */ +#define FTFA_FOPT_LPBOOT_MASK ((uint8_t)0x11) /*!< Reset value of OUTDIV1 in SIM_CLKDIV1 and RUNM in SMC_PMCTRL */ +#define FTFA_FOPT_LPBOOT_DIV8 ((uint8_t)0x00) +#define FTFA_FOPT_LPBOOT_DIV4 ((uint8_t)0x01) +#define FTFA_FOPT_LPBOOT_DIV2 ((uint8_t)0x10) +#define FTFA_FOPT_LPBOOT_DIV1 ((uint8_t)0x11) + +/****************************************************************/ +/* */ +/* Miscellaneous Control Module (MCM) */ +/* */ +/****************************************************************/ +/********** Bits definition for MCM_PLASC register ************/ +#define MCM_PLASC_ASC_MASK ((uint16_t)0xFF) /*!< Crossbar Switch (AXBS) Slave Configuration */ + +/********** Bits definition for MCM_PLAMC register ************/ +#define MCM_PLASC_AMC_MASK ((uint16_t)0xFF) /*!< Crossbar Switch (AXBS) Master Configuration */ + +/********** Bits definition for MCM_PLACR register ************/ +#define MCM_PLACR_ESFC ((uint32_t)0x00010000) /*!< Enable Stalling Flash Controller */ +#define MCM_PLACR_DFCS ((uint32_t)0x00008000) /*!< Disable Flash Controller Speculation */ +#define MCM_PLACR_EFDS ((uint32_t)0x00004000) /*!< Enable Flash Data Speculation */ +#define MCM_PLACR_DFCC ((uint32_t)0x00002000) /*!< Disable Flash Controller Cache */ +#define MCM_PLACR_DFCIC ((uint32_t)0x00001000) /*!< Disable Flash Controller Instruction Caching */ +#define MCM_PLACR_DFCDA ((uint32_t)0x00000800) /*!< Disable Flash Controller Data Caching */ +#define MCM_PLACR_CFCC ((uint32_t)0x00000400) /*!< Clear Flash Controller Cache */ +#define MCM_PLACR_ARB ((uint32_t)0x00000200) /*!< Arbitration select */ + +/********** Bits definition for MCM_CPO register **************/ +#define MCM_CPO_CPOWOI ((uint32_t)0x00000004) /*!< Compute Operation wakeup on interrupt */ +#define MCM_CPO_CPOACK ((uint32_t)0x00000002) /*!< Compute Operation acknowledge */ +#define MCM_CPO_CPOREQ ((uint32_t)0x00000001) /*!< Compute Operation request */ + +#endif /* _KL2xZ_H_ */ diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk deleted file mode 100644 index b3d6e37..0000000 --- a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_k20x.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS generic K20x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
-
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.s
-
-STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/devices/K20x \
- $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x \
- $(CHIBIOS)/os/common/ext/CMSIS/include
-
-STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk deleted file mode 100644 index 363cafe..0000000 --- a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of the ChibiOS generic KL2x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
-
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.s
-
-STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/devices/KL2x \
- $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x \
- $(CHIBIOS)/os/common/ext/CMSIS/include
-
-STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld new file mode 100644 index 0000000..57678ef --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld @@ -0,0 +1,59 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 128k - 0x410
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld new file mode 100644 index 0000000..af47ac5 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld @@ -0,0 +1,57 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup (3k bootloader section).
+ */
+MEMORY
+{
+ flash : org = 0x00000c00, len = 128k - 0xc00
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis_bldr.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld new file mode 100644 index 0000000..28c1033 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld @@ -0,0 +1,57 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup (4k bootloader section).
+ */
+MEMORY
+{
+ flash : org = 0x00001000, len = 128k - 0x1000
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis_bldr.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld new file mode 100644 index 0000000..35a63f6 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org> + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * MK20DX256 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 0x400 + flashcfg : org = 0x00000400, len = 0x10 + flash : org = 0x00000410, len = 256k - 0x410 + ram0 : org = 0x1FFF8000, len = 64k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules_kinetis.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld new file mode 100644 index 0000000..d079e2d --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld @@ -0,0 +1,59 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL26Z64 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 64k - 0x410
+ ram0 : org = 0x1FFFF800, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld new file mode 100644 index 0000000..fc405a8 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld @@ -0,0 +1,59 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL27Z256 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 256k - 0x410
+ ram0 : org = 0x1FFFE000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld new file mode 100644 index 0000000..2e04ab3 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld @@ -0,0 +1,59 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL26Z128 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 128k - 0x410
+ ram0 : org = 0x1FFFF000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+INCLUDE rules_kinetis.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/rules_kinetis.ld index 9e90549..1e95c5f 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/MK20DX128.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/rules_kinetis.ld @@ -1,42 +1,25 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * MK20DX128 memory setup.
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
-MEMORY
-{
- flash0 : org = 0x00000000, len = 0x100
- flashcfg : org = 0x00000400, len = 0x10
- flash : org = 0x00000410, len = 128k - 0x410
- ram0 : org = 0x1fffe000, len = 16k
- ram1 : org = 0x00000000, len = 0
- ram2 : org = 0x00000000, len = 0
- ram3 : org = 0x00000000, len = 0
- ram4 : org = 0x00000000, len = 0
- ram5 : org = 0x00000000, len = 0
- ram6 : org = 0x00000000, len = 0
- ram7 : org = 0x00000000, len = 0
-}
-
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("BSS_RAM", ram0);
-REGION_ALIAS("HEAP_RAM", ram0);
__ram0_start__ = ORIGIN(ram0);
__ram0_size__ = LENGTH(ram0);
@@ -69,7 +52,7 @@ SECTIONS {
. = 0;
- startup : ALIGN(16) SUBALIGN(16)
+ .isr : ALIGN(4) SUBALIGN(4)
{
KEEP(*(.vectors))
} > flash0
@@ -184,7 +167,7 @@ SECTIONS . = ALIGN(4);
_bss_end = .;
PROVIDE(end = .);
- } > BSS_RAM
+ } > BSS_RAM
.ram0_init : ALIGN(4)
{
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/rules_kinetis_bldr.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/rules_kinetis_bldr.ld new file mode 100644 index 0000000..4ae8dc1 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/rules_kinetis_bldr.ld @@ -0,0 +1,367 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+__ram0_start__ = ORIGIN(ram0);
+__ram0_size__ = LENGTH(ram0);
+__ram0_end__ = __ram0_start__ + __ram0_size__;
+__ram1_start__ = ORIGIN(ram1);
+__ram1_size__ = LENGTH(ram1);
+__ram1_end__ = __ram1_start__ + __ram1_size__;
+__ram2_start__ = ORIGIN(ram2);
+__ram2_size__ = LENGTH(ram2);
+__ram2_end__ = __ram2_start__ + __ram2_size__;
+__ram3_start__ = ORIGIN(ram3);
+__ram3_size__ = LENGTH(ram3);
+__ram3_end__ = __ram3_start__ + __ram3_size__;
+__ram4_start__ = ORIGIN(ram4);
+__ram4_size__ = LENGTH(ram4);
+__ram4_end__ = __ram4_start__ + __ram4_size__;
+__ram5_start__ = ORIGIN(ram5);
+__ram5_size__ = LENGTH(ram5);
+__ram5_end__ = __ram5_start__ + __ram5_size__;
+__ram6_start__ = ORIGIN(ram6);
+__ram6_size__ = LENGTH(ram6);
+__ram6_end__ = __ram6_start__ + __ram6_size__;
+__ram7_start__ = ORIGIN(ram7);
+__ram7_size__ = LENGTH(ram7);
+__ram7_end__ = __ram7_start__ + __ram7_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ . = 0;
+
+ .isr : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.vectors))
+ } > flash
+
+ _text = .;
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ __init_array_start = .;
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ __init_array_end = .;
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ __fini_array_start = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .textalign : ONLY_IF_RO
+ {
+ . = ALIGN(8);
+ } > flash
+
+ /* Legacy symbol, not used anywhere.*/
+ . = ALIGN(4);
+ PROVIDE(_etext = .);
+
+ /* Special section for exceptions stack.*/
+ .mstack :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ } > MAIN_STACK_RAM
+
+ /* Special section for process stack.*/
+ .pstack :
+ {
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > PROCESS_STACK_RAM
+
+ .data : ALIGN(4)
+ {
+ . = ALIGN(4);
+ PROVIDE(_textdata = LOADADDR(.data));
+ PROVIDE(_data = .);
+ _textdata_start = LOADADDR(.data);
+ _data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ _data_end = .;
+ } > DATA_RAM AT > flash
+
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ _bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _bss_end = .;
+ PROVIDE(end = .);
+ } > BSS_RAM
+
+ .ram0_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram0_init_text__ = LOADADDR(.ram0_init);
+ __ram0_init__ = .;
+ *(.ram0_init)
+ *(.ram0_init.*)
+ . = ALIGN(4);
+ } > ram0 AT > flash
+
+ .ram0 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram0_clear__ = .;
+ *(.ram0_clear)
+ *(.ram0_clear.*)
+ . = ALIGN(4);
+ __ram0_noinit__ = .;
+ *(.ram0)
+ *(.ram0.*)
+ . = ALIGN(4);
+ __ram0_free__ = .;
+ } > ram0
+
+ .ram1_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram1_init_text__ = LOADADDR(.ram1_init);
+ __ram1_init__ = .;
+ *(.ram1_init)
+ *(.ram1_init.*)
+ . = ALIGN(4);
+ } > ram1 AT > flash
+
+ .ram1 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram1_clear__ = .;
+ *(.ram1_clear)
+ *(.ram1_clear.*)
+ . = ALIGN(4);
+ __ram1_noinit__ = .;
+ *(.ram1)
+ *(.ram1.*)
+ . = ALIGN(4);
+ __ram1_free__ = .;
+ } > ram1
+
+ .ram2_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram2_init_text__ = LOADADDR(.ram2_init);
+ __ram2_init__ = .;
+ *(.ram2_init)
+ *(.ram2_init.*)
+ . = ALIGN(4);
+ } > ram2 AT > flash
+
+ .ram2 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram2_clear__ = .;
+ *(.ram2_clear)
+ *(.ram2_clear.*)
+ . = ALIGN(4);
+ __ram2_noinit__ = .;
+ *(.ram2)
+ *(.ram2.*)
+ . = ALIGN(4);
+ __ram2_free__ = .;
+ } > ram2
+
+ .ram3_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram3_init_text__ = LOADADDR(.ram3_init);
+ __ram3_init__ = .;
+ *(.ram3_init)
+ *(.ram3_init.*)
+ . = ALIGN(4);
+ } > ram3 AT > flash
+
+ .ram3 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram3_clear__ = .;
+ *(.ram3_clear)
+ *(.ram3_clear.*)
+ . = ALIGN(4);
+ __ram3_noinit__ = .;
+ *(.ram3)
+ *(.ram3.*)
+ . = ALIGN(4);
+ __ram3_free__ = .;
+ } > ram3
+
+ .ram4_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram4_init_text__ = LOADADDR(.ram4_init);
+ __ram4_init__ = .;
+ *(.ram4_init)
+ *(.ram4_init.*)
+ . = ALIGN(4);
+ } > ram4 AT > flash
+
+ .ram4 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram4_clear__ = .;
+ *(.ram4_clear)
+ *(.ram4_clear.*)
+ . = ALIGN(4);
+ __ram4_noinit__ = .;
+ *(.ram4)
+ *(.ram4.*)
+ . = ALIGN(4);
+ __ram4_free__ = .;
+ } > ram4
+
+ .ram5_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram5_init_text__ = LOADADDR(.ram5_init);
+ __ram5_init__ = .;
+ *(.ram5_init)
+ *(.ram5_init.*)
+ . = ALIGN(4);
+ } > ram5 AT > flash
+
+ .ram5 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram5_clear__ = .;
+ *(.ram5_clear)
+ *(.ram5_clear.*)
+ . = ALIGN(4);
+ __ram5_noinit__ = .;
+ *(.ram5)
+ *(.ram5.*)
+ . = ALIGN(4);
+ __ram5_free__ = .;
+ } > ram5
+
+ .ram6_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram6_init_text__ = LOADADDR(.ram6_init);
+ __ram6_init__ = .;
+ *(.ram6_init)
+ *(.ram6_init.*)
+ . = ALIGN(4);
+ } > ram6 AT > flash
+
+ .ram6 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram6_clear__ = .;
+ *(.ram6_clear)
+ *(.ram6_clear.*)
+ . = ALIGN(4);
+ __ram6_noinit__ = .;
+ *(.ram6)
+ *(.ram6.*)
+ . = ALIGN(4);
+ __ram6_free__ = .;
+ } > ram6
+
+ .ram7_init : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram7_init_text__ = LOADADDR(.ram7_init);
+ __ram7_init__ = .;
+ *(.ram7_init)
+ *(.ram7_init.*)
+ . = ALIGN(4);
+ } > ram7 AT > flash
+
+ .ram7 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __ram7_clear__ = .;
+ *(.ram7_clear)
+ *(.ram7_clear.*)
+ . = ALIGN(4);
+ __ram7_noinit__ = .;
+ *(.ram7)
+ *(.ram7.*)
+ . = ALIGN(4);
+ __ram7_free__ = .;
+ } > ram7
+
+ /* The default heap uses the (statically) unused part of a RAM section.*/
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __heap_base__ = .;
+ . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
+ __heap_end__ = .;
+ } > HEAP_RAM
+}
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk new file mode 100644 index 0000000..410e607 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk @@ -0,0 +1,12 @@ +# List of the ChibiOS generic K20x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.s
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk new file mode 100644 index 0000000..7ab25de --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk @@ -0,0 +1,3 @@ +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+
+STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x5
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk new file mode 100644 index 0000000..3c8ea09 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk @@ -0,0 +1,3 @@ +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+
+STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x7
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk new file mode 100644 index 0000000..ada23f6 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk @@ -0,0 +1,12 @@ +# List of the ChibiOS generic KL2x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.s
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/KL2x \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/ports/ARMCMx/devices/K20x/cmparams.h b/os/common/startup/ARMCMx/devices/K20x5/cmparams.h index 8ee9abd..8aebbc0 100644 --- a/os/common/ports/ARMCMx/devices/K20x/cmparams.h +++ b/os/common/startup/ARMCMx/devices/K20x5/cmparams.h @@ -1,27 +1,32 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
+ This file is part of ChibiOS/RT.
- http://www.apache.org/licenses/LICENSE-2.0
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
- * @file GCC/ARMCMx/MK20Dx/cmparams.h
- * @brief ARM Cortex-M4 parameters for the Kinetis MK20Dx.
+ * @file GCC/ARMCMx/K20x5/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the Kinetis K20x5.
*
- * @defgroup ARMCMx_MK20Dx Kinetis MK20Dx Specific Parameters
+ * @defgroup ARMCMx_K20x5 Kinetis K20x5 Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M4 specific parameters for the
- * Kinetis MK20Dx platform.
+ * Kinetis K20x5 platform.
* @{
*/
@@ -62,7 +67,7 @@ /* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
-#include "mk20d5.h"
+#include "k20x5.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
diff --git a/os/common/startup/ARMCMx/devices/K20x7/cmparams.h b/os/common/startup/ARMCMx/devices/K20x7/cmparams.h new file mode 100644 index 0000000..afb3053 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/K20x7/cmparams.h @@ -0,0 +1,80 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file GCC/ARMCMx/K20x7/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the Kinetis K20x7.
+ *
+ * @defgroup ARMCMx_K20x7 Kinetis K20x7 Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * Kinetis K20x7 platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 96
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "k20x7.h"
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/KL2x/cmparams.h b/os/common/startup/ARMCMx/devices/KL2x/cmparams.h index dd89c75..93a7055 100644 --- a/os/common/ports/ARMCMx/devices/KL2x/cmparams.h +++ b/os/common/startup/ARMCMx/devices/KL2x/cmparams.h @@ -1,17 +1,22 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
+ This file is part of ChibiOS.
- http://www.apache.org/licenses/LICENSE-2.0
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
@@ -59,10 +64,18 @@ asm module.*/
#if !defined(_FROM_ASM_)
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (KL25) && !defined (KL26) && \
+ !defined (KL27Zxxx) && !defined (KL27Zxx)
+#include "board.h"
+#endif
+
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
-#include "kl25z.h"
+#include "kl2xz.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c index b803d1f..ee86d96 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c @@ -116,7 +116,7 @@ const PALConfig pal_default_config = */
void __early_init(void) {
- mk20d50_clock_init();
+ k20x_clock_init();
}
/**
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h index 41ce877..cf41495 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h @@ -27,6 +27,24 @@ #define BOARD_FREESCALE_FREEDOM_K20D50M
#define BOARD_NAME "Freescale Freedom K20D50M"
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY 8000000UL
+
+/*
+ * MCU type
+ */
+#define K20x5
+
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED IOPORT3
+#define PIN_LED_RED 3
+#define GPIO_LED_GREEN IOPORT4
+#define PIN_LED_GREEN 4
+#define GPIO_LED_BLUE IOPORT1
+#define PIN_LED_BLUE 2
+
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk index e09d821..f74d306 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk @@ -1,5 +1,5 @@ # List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h index beeeef1..35d8e06 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h @@ -27,9 +27,30 @@ #define BOARD_FREESCALE_FREEDOM_KL25Z
#define BOARD_NAME "Freescale Freedom KL25Z"
-/* External 8 MHz crystal with PLL for 48 MHz core/system clock. */
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
-#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY 8000000UL
+
+/*
+ * MCU type
+ */
+#define KL25
+
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED IOPORT2
+#define PIN_LED_RED 18
+#define GPIO_LED_GREEN IOPORT2
+#define PIN_LED_GREEN 19
+#define GPIO_LED_BLUE IOPORT4
+#define PIN_LED_BLUE 1
+
+#define I2C_INERIAL_SENSOR I2C0
+
+/*
+ * Not configured:
+ * - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
+ */
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk index 9ae0f5e..3097a90 100644 --- a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk @@ -1,5 +1,5 @@ # List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c new file mode 100644 index 0000000..7c68f66 --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c @@ -0,0 +1,127 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ .port = IOPORT1, // PORTA
+ .pads = {
+ /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_ALTERNATIVE_2, /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
+ /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_INPUT_ANALOG, /* PTA5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
+ /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
+ /*PTA12*/ PAL_MODE_INPUT_ANALOG, /*PTA13*/ PAL_MODE_INPUT_ANALOG, /*PTA14*/ PAL_MODE_UNCONNECTED,
+ /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
+ /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
+ /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
+ /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
+ /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
+ /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT2, // PORTB
+ .pads = {
+ /* PTB0*/ PAL_MODE_INPUT_ANALOG, /* PTB1*/ PAL_MODE_INPUT_ANALOG, /* PTB2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB3*/ PAL_MODE_INPUT_ANALOG, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
+ /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
+ /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
+ /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_INPUT_ANALOG, /*PTB17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTB18*/ PAL_MODE_INPUT_ANALOG, /*PTB19*/ PAL_MODE_INPUT_ANALOG, /*PTB20*/ PAL_MODE_UNCONNECTED,
+ /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
+ /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
+ /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
+ /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT3, // PORTC
+ .pads = {
+ /* PTC0*/ PAL_MODE_INPUT_ANALOG, /* PTC1*/ PAL_MODE_INPUT_ANALOG, /* PTC2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC3*/ PAL_MODE_INPUT, /* PTC4*/ PAL_MODE_INPUT_ANALOG, /* PTC5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC6*/ PAL_MODE_INPUT_ANALOG, /* PTC7*/ PAL_MODE_INPUT_ANALOG, /* PTC8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC9*/ PAL_MODE_INPUT_ANALOG, /*PTC10*/ PAL_MODE_INPUT_ANALOG, /*PTC11*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
+ /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
+ /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
+ /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
+ /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
+ /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
+ /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT4, // PORTD
+ .pads = {
+ /* PTD0*/ PAL_MODE_INPUT_PULLUP, /* PTD1*/ PAL_MODE_INPUT_ANALOG, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD3*/ PAL_MODE_INPUT_ANALOG, /* PTD4*/ PAL_MODE_INPUT_ANALOG, /* PTD5*/ PAL_MODE_OUTPUT_PUSHPULL,
+ /* PTD6*/ PAL_MODE_INPUT_ANALOG, /* PTD7*/ PAL_MODE_INPUT_ANALOG, /* PTD8*/ PAL_MODE_UNCONNECTED,
+ /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
+ /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
+ /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
+ /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
+ /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
+ /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
+ /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
+ /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT5, // PORTE
+ .pads = {
+ /* PTE0*/ PAL_MODE_INPUT_ANALOG, /* PTE1*/ PAL_MODE_INPUT_ANALOG, /* PTE2*/ PAL_MODE_UNCONNECTED,
+ /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
+ /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
+ /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
+ /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
+ /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
+ /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE21*/ PAL_MODE_INPUT_ANALOG, /*PTE22*/ PAL_MODE_INPUT, /*PTE23*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE24*/ PAL_MODE_ALTERNATIVE_5, /*PTE25*/ PAL_MODE_ALTERNATIVE_5, /*PTE26*/ PAL_MODE_UNCONNECTED,
+ /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_OUTPUT_PUSHPULL,
+ /*PTE30*/ PAL_MODE_INPUT_ANALOG, /*PTE31*/ PAL_MODE_OUTPUT_PUSHPULL,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ kl2x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h new file mode 100644 index 0000000..e13debb --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h @@ -0,0 +1,69 @@ +/*
+ ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Freescale Freedom KL26Z board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_KL26Z
+#define BOARD_NAME "Freescale Freedom KL26Z"
+
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY 8000000UL
+
+/*
+ * MCU type
+ */
+#define KL26
+
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED IOPORT5
+#define PIN_LED_RED 29
+#define GPIO_LED_GREEN IOPORT5
+#define PIN_LED_GREEN 31
+#define GPIO_LED_BLUE IOPORT4
+#define PIN_LED_BLUE 5
+#define GPIO_BUTTON IOPORT4
+#define PIN_BUTTON 0
+#define GPIO_LIGHTSNS IOPORT5
+#define PIN_LIGHTSNS 22
+
+#define I2C_INERIAL_SENSOR I2C0
+
+/*
+ * Not configured:
+ * - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
+ */
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk new file mode 100644 index 0000000..c352346 --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z
diff --git a/os/hal/boards/MCHCK_K20/board.c b/os/hal/boards/MCHCK_K20/board.c index 9d2b698..d67e6ce 100644 --- a/os/hal/boards/MCHCK_K20/board.c +++ b/os/hal/boards/MCHCK_K20/board.c @@ -115,7 +115,8 @@ const PALConfig pal_default_config = * and before any other initialization.
*/
void __early_init(void) {
- mk20d50_clock_init();
+
+ k20x_clock_init();
}
/**
diff --git a/os/hal/boards/MCHCK_K20/board.h b/os/hal/boards/MCHCK_K20/board.h index ed22891..504ab0e 100644 --- a/os/hal/boards/MCHCK_K20/board.h +++ b/os/hal/boards/MCHCK_K20/board.h @@ -27,6 +27,11 @@ #define BOARD_MCHCK_K20_MX20DX128
#define BOARD_NAME "MCHCK K20 MX20DX128"
+/*
+ * MCU type
+ */
+#define K20x5
+
#define GPIOB_LED 16
#if !defined(_FROM_ASM_)
diff --git a/os/hal/boards/MCHCK_K20/board.mk b/os/hal/boards/MCHCK_K20/board.mk index dbf42c3..22406ac 100644 --- a/os/hal/boards/MCHCK_K20/board.mk +++ b/os/hal/boards/MCHCK_K20/board.mk @@ -1,5 +1,5 @@ # List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/MCHCK_K20/board.c
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/MCHCK_K20
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.c b/os/hal/boards/PJRC_TEENSY_3/board.c index 68b13d0..f89c7e5 100644 --- a/os/hal/boards/PJRC_TEENSY_3/board.c +++ b/os/hal/boards/PJRC_TEENSY_3/board.c @@ -13,8 +13,6 @@ See the License for the specific language governing permissions and
limitations under the License.
*/
-
-#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
@@ -34,16 +32,19 @@ const PALConfig pal_default_config = * PTA5 - PIN24
* PTA12 - PIN3
* PTA13 - PIN4
+ *
+ * PTA18/19 crystal
+ * PTA0/3 SWD
*/
.port = IOPORT1,
.pads = {
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
@@ -171,7 +172,7 @@ const PALConfig pal_default_config = */
void __early_init(void) {
- mk20d50_clock_init();
+ k20x_clock_init();
}
/**
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.h b/os/hal/boards/PJRC_TEENSY_3/board.h index 4f7ecdb..ee9f514 100644 --- a/os/hal/boards/PJRC_TEENSY_3/board.h +++ b/os/hal/boards/PJRC_TEENSY_3/board.h @@ -27,11 +27,17 @@ #define BOARD_PJRC_TEENSY_3
#define BOARD_NAME "PJRC Teensy 3.0"
-/* External 16 MHz crystal with PLL for 48 MHz core/system clock. */
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
-#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+/* External 16 MHz crystal */
#define KINETIS_XTAL_FREQUENCY 16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define K20x5
+
/*
* IO pins assignments.
*/
@@ -39,16 +45,16 @@ #define PORTA_PIN1 1
#define PORTA_PIN2 2
#define PORTA_PIN3 3
-#define PORTA_TEENSY_PIN33 4
-#define PORTA_TEENSY_PIN24 5
+#define TEENSY_PIN33 4
+#define TEENSY_PIN24 5
#define PORTA_PIN6 6
#define PORTA_PIN7 7
#define PORTA_PIN8 8
#define PORTA_PIN9 9
#define PORTA_PIN10 10
#define PORTA_PIN11 11
-#define PORTA_TEENSY_PIN3 12
-#define PORTA_TEENSY_PIN4 13
+#define TEENSY_PIN3 12
+#define TEENSY_PIN4 13
#define PORTA_PIN14 14
#define PORTA_PIN15 15
#define PORTA_PIN16 16
@@ -68,10 +74,15 @@ #define PORTA_PIN30 30
#define PORTA_PIN31 31
-#define PORTB_TEENSY_PIN16 0
-#define PORTB_TEENSY_PIN17 1
-#define PORTB_TEENSY_PIN19 2
-#define PORTB_TEENSY_PIN18 3
+#define TEENSY_PIN3_IOPORT IOPORT1
+#define TEENSY_PIN4_IOPORT IOPORT1
+#define TEENSY_PIN24_IOPORT IOPORT1
+#define TEENSY_PIN33_IOPORT IOPORT1
+
+#define TEENSY_PIN16 0
+#define TEENSY_PIN17 1
+#define TEENSY_PIN19 2
+#define TEENSY_PIN18 3
#define PORTB_PIN4 4
#define PORTB_PIN5 5
#define PORTB_PIN6 6
@@ -84,10 +95,10 @@ #define PORTB_PIN13 13
#define PORTB_PIN14 14
#define PORTB_PIN15 15
-#define PORTB_TEENSY_PIN0 16
-#define PORTB_TEENSY_PIN1 17
-#define PORTB_TEENSY_PIN32 18
-#define PORTB_TEENSY_PIN25 19
+#define TEENSY_PIN0 16
+#define TEENSY_PIN1 17
+#define TEENSY_PIN32 18
+#define TEENSY_PIN25 19
#define PORTB_PIN20 20
#define PORTB_PIN21 21
#define PORTB_PIN22 22
@@ -101,18 +112,27 @@ #define PORTB_PIN30 30
#define PORTB_PIN31 31
-#define PORTC_TEENSY_PIN15 0
-#define PORTC_TEENSY_PIN22 1
-#define PORTC_TEENSY_PIN23 2
-#define PORTC_TEENSY_PIN9 3
-#define PORTC_TEENSY_PIN10 4
-#define PORTC_TEENSY_PIN13 5
-#define PORTC_TEENSY_PIN11 6
-#define PORTC_TEENSY_PIN12 7
-#define PORTC_TEENSY_PIN28 8
-#define PORTC_TEENSY_PIN27 9
-#define PORTC_TEENSY_PIN29 10
-#define PORTC_TEENSY_PIN30 11
+#define TEENSY_PIN0_IOPORT IOPORT2
+#define TEENSY_PIN1_IOPORT IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN25_IOPORT IOPORT2
+#define TEENSY_PIN32_IOPORT IOPORT2
+
+#define TEENSY_PIN15 0
+#define TEENSY_PIN22 1
+#define TEENSY_PIN23 2
+#define TEENSY_PIN9 3
+#define TEENSY_PIN10 4
+#define TEENSY_PIN13 5
+#define TEENSY_PIN11 6
+#define TEENSY_PIN12 7
+#define TEENSY_PIN28 8
+#define TEENSY_PIN27 9
+#define TEENSY_PIN29 10
+#define TEENSY_PIN30 11
#define PORTC_PIN12 12
#define PORTC_PIN13 13
#define PORTC_PIN14 14
@@ -134,14 +154,27 @@ #define PORTC_PIN30 30
#define PORTC_PIN31 31
-#define PORTD_TEENSY_PIN2 0
-#define PORTD_TEENSY_PIN14 1
-#define PORTD_TEENSY_PIN7 2
-#define PORTD_TEENSY_PIN8 3
-#define PORTD_TEENSY_PIN6 4
-#define PORTD_TEENSY_PIN20 5
-#define PORTD_TEENSY_PIN21 6
-#define PORTD_TEENSY_PIN5 7
+#define TEENSY_PIN9_IOPORT IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN27_IOPORT IOPORT3
+#define TEENSY_PIN28_IOPORT IOPORT3
+#define TEENSY_PIN29_IOPORT IOPORT3
+#define TEENSY_PIN30_IOPORT IOPORT3
+
+#define TEENSY_PIN2 0
+#define TEENSY_PIN14 1
+#define TEENSY_PIN7 2
+#define TEENSY_PIN8 3
+#define TEENSY_PIN6 4
+#define TEENSY_PIN20 5
+#define TEENSY_PIN21 6
+#define TEENSY_PIN5 7
#define PORTD_PIN8 8
#define PORTD_PIN9 9
#define PORTD_PIN10 10
@@ -167,8 +200,17 @@ #define PORTD_PIN30 30
#define PORTD_PIN31 31
-#define PORTE_TEENSY_PIN31 0
-#define PORTE_TEENSY_PIN26 1
+#define TEENSY_PIN2_IOPORT IOPORT4
+#define TEENSY_PIN5_IOPORT IOPORT4
+#define TEENSY_PIN6_IOPORT IOPORT4
+#define TEENSY_PIN7_IOPORT IOPORT4
+#define TEENSY_PIN8_IOPORT IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+
+#define TEENSY_PIN31 0
+#define TEENSY_PIN26 1
#define PORTE_PIN2 2
#define PORTE_PIN3 3
#define PORTE_PIN4 4
@@ -200,6 +242,9 @@ #define PORTE_PIN30 30
#define PORTE_PIN31 31
+#define TEENSY_PIN26_IOPORT IOPORT5
+#define TEENSY_PIN31_IOPORT IOPORT5
+
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.mk b/os/hal/boards/PJRC_TEENSY_3/board.mk index d19a654..b9dcdc8 100644 --- a/os/hal/boards/PJRC_TEENSY_3/board.mk +++ b/os/hal/boards/PJRC_TEENSY_3/board.mk @@ -1,5 +1,5 @@ # List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/PJRC_TEENSY_3/board.c
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/PJRC_TEENSY_3
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3
diff --git a/os/hal/boards/PJRC_TEENSY_3_1/board.c b/os/hal/boards/PJRC_TEENSY_3_1/board.c new file mode 100644 index 0000000..d60a89c --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_1/board.c @@ -0,0 +1,183 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ /*
+ * PORTA setup.
+ *
+ * PTA4 - PIN33
+ * PTA5 - PIN24
+ * PTA12 - PIN3
+ * PTA13 - PIN4
+ *
+ * PTA18/19 crystal
+ * PTA0/3 SWD
+ */
+ .port = IOPORT1,
+ .pads = {
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTB setup.
+ *
+ * PTB0 - PIN16
+ * PTB1 - PIN17
+ * PTB2 - PIN19
+ * PTB3 - PIN18
+ * PTB16 - PIN0 - UART0_TX
+ * PTB17 - PIN1 - UART0_RX
+ * PTB18 - PIN32
+ * PTB19 - PIN25
+ */
+ .port = IOPORT2,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTC setup.
+ *
+ * PTC0 - PIN15
+ * PTC1 - PIN22
+ * PTC2 - PIN23
+ * PTC3 - PIN9
+ * PTC4 - PIN10
+ * PTC5 - PIN13
+ * PTC6 - PIN11
+ * PTC7 - PIN12
+ * PTC8 - PIN28
+ * PTC9 - PIN27
+ * PTC10 - PIN29
+ * PTC11 - PIN30
+ */
+ .port = IOPORT3,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTD setup.
+ *
+ * PTD0 - PIN2
+ * PTD1 - PIN14
+ * PTD2 - PIN7
+ * PTD3 - PIN8
+ * PTD4 - PIN6
+ * PTD5 - PIN20
+ * PTD6 - PIN21
+ * PTD7 - PIN5
+ */
+ .port = IOPORT4,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTE setup.
+ *
+ * PTE0 - PIN31
+ * PTE1 - PIN26
+ */
+ .port = IOPORT5,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ k20x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3_1/board.h b/os/hal/boards/PJRC_TEENSY_3_1/board.h new file mode 100644 index 0000000..6e89c07 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_1/board.h @@ -0,0 +1,258 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.1 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3_1
+#define BOARD_NAME "PJRC Teensy 3.1"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY 16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define K20x7
+
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0 0
+#define PORTA_PIN1 1
+#define PORTA_PIN2 2
+#define PORTA_PIN3 3
+#define TEENSY_PIN33 4
+#define TEENSY_PIN24 5
+#define PORTA_PIN6 6
+#define PORTA_PIN7 7
+#define PORTA_PIN8 8
+#define PORTA_PIN9 9
+#define PORTA_PIN10 10
+#define PORTA_PIN11 11
+#define TEENSY_PIN3 12
+#define TEENSY_PIN4 13
+#define PORTA_PIN14 14
+#define PORTA_PIN15 15
+#define PORTA_PIN16 16
+#define PORTA_PIN17 17
+#define PORTA_PIN18 18
+#define PORTA_PIN19 19
+#define PORTA_PIN20 20
+#define PORTA_PIN21 21
+#define PORTA_PIN22 22
+#define PORTA_PIN23 23
+#define PORTA_PIN24 24
+#define PORTA_PIN25 25
+#define PORTA_PIN26 26
+#define PORTA_PIN27 27
+#define PORTA_PIN28 28
+#define PORTA_PIN29 29
+#define PORTA_PIN30 30
+#define PORTA_PIN31 31
+
+#define TEENSY_PIN3_IOPORT IOPORT1
+#define TEENSY_PIN4_IOPORT IOPORT1
+#define TEENSY_PIN24_IOPORT IOPORT1
+#define TEENSY_PIN33_IOPORT IOPORT1
+
+#define TEENSY_PIN16 0
+#define TEENSY_PIN17 1
+#define TEENSY_PIN19 2
+#define TEENSY_PIN18 3
+#define PORTB_PIN4 4
+#define PORTB_PIN5 5
+#define PORTB_PIN6 6
+#define PORTB_PIN7 7
+#define PORTB_PIN8 8
+#define PORTB_PIN9 9
+#define PORTB_PIN10 10
+#define PORTB_PIN11 11
+#define PORTB_PIN12 12
+#define PORTB_PIN13 13
+#define PORTB_PIN14 14
+#define PORTB_PIN15 15
+#define TEENSY_PIN0 16
+#define TEENSY_PIN1 17
+#define TEENSY_PIN32 18
+#define TEENSY_PIN25 19
+#define PORTB_PIN20 20
+#define PORTB_PIN21 21
+#define PORTB_PIN22 22
+#define PORTB_PIN23 23
+#define PORTB_PIN24 24
+#define PORTB_PIN25 25
+#define PORTB_PIN26 26
+#define PORTB_PIN27 27
+#define PORTB_PIN28 28
+#define PORTB_PIN29 29
+#define PORTB_PIN30 30
+#define PORTB_PIN31 31
+
+#define TEENSY_PIN0_IOPORT IOPORT2
+#define TEENSY_PIN1_IOPORT IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN25_IOPORT IOPORT2
+#define TEENSY_PIN32_IOPORT IOPORT2
+
+#define TEENSY_PIN15 0
+#define TEENSY_PIN22 1
+#define TEENSY_PIN23 2
+#define TEENSY_PIN9 3
+#define TEENSY_PIN10 4
+#define TEENSY_PIN13 5
+#define TEENSY_PIN11 6
+#define TEENSY_PIN12 7
+#define TEENSY_PIN28 8
+#define TEENSY_PIN27 9
+#define TEENSY_PIN29 10
+#define TEENSY_PIN30 11
+#define PORTC_PIN12 12
+#define PORTC_PIN13 13
+#define PORTC_PIN14 14
+#define PORTC_PIN15 15
+#define PORTC_PIN16 16
+#define PORTC_PIN17 17
+#define PORTC_PIN18 18
+#define PORTC_PIN19 19
+#define PORTC_PIN20 20
+#define PORTC_PIN21 21
+#define PORTC_PIN22 22
+#define PORTC_PIN23 23
+#define PORTC_PIN24 24
+#define PORTC_PIN25 25
+#define PORTC_PIN26 26
+#define PORTC_PIN27 27
+#define PORTC_PIN28 28
+#define PORTC_PIN29 29
+#define PORTC_PIN30 30
+#define PORTC_PIN31 31
+
+#define TEENSY_PIN9_IOPORT IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN27_IOPORT IOPORT3
+#define TEENSY_PIN28_IOPORT IOPORT3
+#define TEENSY_PIN29_IOPORT IOPORT3
+#define TEENSY_PIN30_IOPORT IOPORT3
+
+#define TEENSY_PIN2 0
+#define TEENSY_PIN14 1
+#define TEENSY_PIN7 2
+#define TEENSY_PIN8 3
+#define TEENSY_PIN6 4
+#define TEENSY_PIN20 5
+#define TEENSY_PIN21 6
+#define TEENSY_PIN5 7
+#define PORTD_PIN8 8
+#define PORTD_PIN9 9
+#define PORTD_PIN10 10
+#define PORTD_PIN11 11
+#define PORTD_PIN12 12
+#define PORTD_PIN13 13
+#define PORTD_PIN14 14
+#define PORTD_PIN15 15
+#define PORTD_PIN16 16
+#define PORTD_PIN17 17
+#define PORTD_PIN18 18
+#define PORTD_PIN19 19
+#define PORTD_PIN20 20
+#define PORTD_PIN21 21
+#define PORTD_PIN22 22
+#define PORTD_PIN23 23
+#define PORTD_PIN24 24
+#define PORTD_PIN25 25
+#define PORTD_PIN26 26
+#define PORTD_PIN27 27
+#define PORTD_PIN28 28
+#define PORTD_PIN29 29
+#define PORTD_PIN30 30
+#define PORTD_PIN31 31
+
+#define TEENSY_PIN2_IOPORT IOPORT4
+#define TEENSY_PIN5_IOPORT IOPORT4
+#define TEENSY_PIN6_IOPORT IOPORT4
+#define TEENSY_PIN7_IOPORT IOPORT4
+#define TEENSY_PIN8_IOPORT IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+
+#define TEENSY_PIN31 0
+#define TEENSY_PIN26 1
+#define PORTE_PIN2 2
+#define PORTE_PIN3 3
+#define PORTE_PIN4 4
+#define PORTE_PIN5 5
+#define PORTE_PIN6 6
+#define PORTE_PIN7 7
+#define PORTE_PIN8 8
+#define PORTE_PIN9 9
+#define PORTE_PIN10 10
+#define PORTE_PIN11 11
+#define PORTE_PIN12 12
+#define PORTE_PIN13 13
+#define PORTE_PIN14 14
+#define PORTE_PIN15 15
+#define PORTE_PIN16 16
+#define PORTE_PIN17 17
+#define PORTE_PIN18 18
+#define PORTE_PIN19 19
+#define PORTE_PIN20 20
+#define PORTE_PIN21 21
+#define PORTE_PIN22 22
+#define PORTE_PIN23 23
+#define PORTE_PIN24 24
+#define PORTE_PIN25 25
+#define PORTE_PIN26 26
+#define PORTE_PIN27 27
+#define PORTE_PIN28 28
+#define PORTE_PIN29 29
+#define PORTE_PIN30 30
+#define PORTE_PIN31 31
+
+#define TEENSY_PIN26_IOPORT IOPORT5
+#define TEENSY_PIN31_IOPORT IOPORT5
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/PJRC_TEENSY_3_1/board.mk b/os/hal/boards/PJRC_TEENSY_3_1/board.mk new file mode 100644 index 0000000..572a524 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_1/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1
diff --git a/os/hal/boards/PJRC_TEENSY_LC/board.c b/os/hal/boards/PJRC_TEENSY_LC/board.c new file mode 100644 index 0000000..31c3ca4 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_LC/board.c @@ -0,0 +1,178 @@ +/*
+ ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ /*
+ * PORTA setup.
+ *
+ * PTA1 - PIN3
+ * PTA2 - PIN4
+ *
+ * PTA18/19 crystal
+ * PTA0/3 SWD
+ */
+ .port = IOPORT1,
+ .pads = {
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTB setup.
+ *
+ * PTB0 - PIN16
+ * PTB1 - PIN17
+ * PTB2 - PIN19
+ * PTB3 - PIN18
+ * PTB16 - PIN0 - UART0_TX
+ * PTB17 - PIN1 - UART0_RX
+ */
+ .port = IOPORT2,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTC setup.
+ *
+ * PTC0 - PIN15
+ * PTC1 - PIN22
+ * PTC2 - PIN23
+ * PTC3 - PIN9
+ * PTC4 - PIN10
+ * PTC5 - PIN13
+ * PTC6 - PIN11
+ * PTC7 - PIN12
+ */
+ .port = IOPORT3,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTD setup.
+ *
+ * PTD0 - PIN2
+ * PTD1 - PIN14
+ * PTD2 - PIN7
+ * PTD3 - PIN8
+ * PTD4 - PIN6
+ * PTD5 - PIN20
+ * PTD6 - PIN21
+ * PTD7 - PIN5
+ */
+ .port = IOPORT4,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTE setup.
+ *
+ * PTE20 - PIN24
+ * PTE21 - PIN25
+ * PTE30 - PIN26
+ */
+ .port = IOPORT5,
+ .pads = {
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ kl2x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_LC/board.h b/os/hal/boards/PJRC_TEENSY_LC/board.h new file mode 100644 index 0000000..3f181f8 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_LC/board.h @@ -0,0 +1,251 @@ +/*
+ ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy LC board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_LC
+#define BOARD_NAME "PJRC Teensy LC"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY 16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P|OSC_CR_ERCLKEN
+
+/*
+ * MCU type
+ */
+#define KL26
+
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0 0
+#define TEENSY_PIN3 1
+#define TEENSY_PIN4 2
+#define PORTA_PIN3 3
+#define PORTA_PIN4 4
+#define PORTA_PIN5 5
+#define PORTA_PIN6 6
+#define PORTA_PIN7 7
+#define PORTA_PIN8 8
+#define PORTA_PIN9 9
+#define PORTA_PIN10 10
+#define PORTA_PIN11 11
+#define PORTA_PIN12 12
+#define PORTA_PIN13 13
+#define PORTA_PIN14 14
+#define PORTA_PIN15 15
+#define PORTA_PIN16 16
+#define PORTA_PIN17 17
+#define PORTA_PIN18 18
+#define PORTA_PIN19 19
+#define PORTA_PIN20 20
+#define PORTA_PIN21 21
+#define PORTA_PIN22 22
+#define PORTA_PIN23 23
+#define PORTA_PIN24 24
+#define PORTA_PIN25 25
+#define PORTA_PIN26 26
+#define PORTA_PIN27 27
+#define PORTA_PIN28 28
+#define PORTA_PIN29 29
+#define PORTA_PIN30 30
+#define PORTA_PIN31 31
+
+#define TEENSY_PIN3_IOPORT IOPORT1
+#define TEENSY_PIN4_IOPORT IOPORT1
+
+#define TEENSY_PIN16 0
+#define TEENSY_PIN17 1
+#define TEENSY_PIN19 2
+#define TEENSY_PIN18 3
+#define PORTB_PIN4 4
+#define PORTB_PIN5 5
+#define PORTB_PIN6 6
+#define PORTB_PIN7 7
+#define PORTB_PIN8 8
+#define PORTB_PIN9 9
+#define PORTB_PIN10 10
+#define PORTB_PIN11 11
+#define PORTB_PIN12 12
+#define PORTB_PIN13 13
+#define PORTB_PIN14 14
+#define PORTB_PIN15 15
+#define TEENSY_PIN0 16
+#define TEENSY_PIN1 17
+#define PORTB_PIN18 18
+#define PORTB_PIN19 19
+#define PORTB_PIN20 20
+#define PORTB_PIN21 21
+#define PORTB_PIN22 22
+#define PORTB_PIN23 23
+#define PORTB_PIN24 24
+#define PORTB_PIN25 25
+#define PORTB_PIN26 26
+#define PORTB_PIN27 27
+#define PORTB_PIN28 28
+#define PORTB_PIN29 29
+#define PORTB_PIN30 30
+#define PORTB_PIN31 31
+
+#define TEENSY_PIN0_IOPORT IOPORT2
+#define TEENSY_PIN1_IOPORT IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+
+#define TEENSY_PIN15 0
+#define TEENSY_PIN22 1
+#define TEENSY_PIN23 2
+#define TEENSY_PIN9 3
+#define TEENSY_PIN10 4
+#define TEENSY_PIN13 5
+#define TEENSY_PIN11 6
+#define TEENSY_PIN12 7
+#define PORTC_PIN8 8
+#define PORTC_PIN9 9
+#define PORTC_PIN10 10
+#define PORTC_PIN11 11
+#define PORTC_PIN12 12
+#define PORTC_PIN13 13
+#define PORTC_PIN14 14
+#define PORTC_PIN15 15
+#define PORTC_PIN16 16
+#define PORTC_PIN17 17
+#define PORTC_PIN18 18
+#define PORTC_PIN19 19
+#define PORTC_PIN20 20
+#define PORTC_PIN21 21
+#define PORTC_PIN22 22
+#define PORTC_PIN23 23
+#define PORTC_PIN24 24
+#define PORTC_PIN25 25
+#define PORTC_PIN26 26
+#define PORTC_PIN27 27
+#define PORTC_PIN28 28
+#define PORTC_PIN29 29
+#define PORTC_PIN30 30
+#define PORTC_PIN31 31
+
+#define TEENSY_PIN9_IOPORT IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+
+#define TEENSY_PIN2 0
+#define TEENSY_PIN14 1
+#define TEENSY_PIN7 2
+#define TEENSY_PIN8 3
+#define TEENSY_PIN6 4
+#define TEENSY_PIN20 5
+#define TEENSY_PIN21 6
+#define TEENSY_PIN5 7
+#define PORTD_PIN8 8
+#define PORTD_PIN9 9
+#define PORTD_PIN10 10
+#define PORTD_PIN11 11
+#define PORTD_PIN12 12
+#define PORTD_PIN13 13
+#define PORTD_PIN14 14
+#define PORTD_PIN15 15
+#define PORTD_PIN16 16
+#define PORTD_PIN17 17
+#define PORTD_PIN18 18
+#define PORTD_PIN19 19
+#define PORTD_PIN20 20
+#define PORTD_PIN21 21
+#define PORTD_PIN22 22
+#define PORTD_PIN23 23
+#define PORTD_PIN24 24
+#define PORTD_PIN25 25
+#define PORTD_PIN26 26
+#define PORTD_PIN27 27
+#define PORTD_PIN28 28
+#define PORTD_PIN29 29
+#define PORTD_PIN30 30
+#define PORTD_PIN31 31
+
+#define TEENSY_PIN2_IOPORT IOPORT4
+#define TEENSY_PIN5_IOPORT IOPORT4
+#define TEENSY_PIN6_IOPORT IOPORT4
+#define TEENSY_PIN7_IOPORT IOPORT4
+#define TEENSY_PIN8_IOPORT IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+
+#define PORTE_PIN0 0
+#define PORTE_PIN1 1
+#define PORTE_PIN2 2
+#define PORTE_PIN3 3
+#define PORTE_PIN4 4
+#define PORTE_PIN5 5
+#define PORTE_PIN6 6
+#define PORTE_PIN7 7
+#define PORTE_PIN8 8
+#define PORTE_PIN9 9
+#define PORTE_PIN10 10
+#define PORTE_PIN11 11
+#define PORTE_PIN12 12
+#define PORTE_PIN13 13
+#define PORTE_PIN14 14
+#define PORTE_PIN15 15
+#define PORTE_PIN16 16
+#define PORTE_PIN17 17
+#define PORTE_PIN18 18
+#define PORTE_PIN19 19
+#define TEENSY_PIN24 20
+#define TEENSY_PIN25 21
+#define PORTE_PIN22 22
+#define PORTE_PIN23 23
+#define PORTE_PIN24 24
+#define PORTE_PIN25 25
+#define PORTE_PIN26 26
+#define PORTE_PIN27 27
+#define PORTE_PIN28 28
+#define PORTE_PIN29 29
+#define TEENSY_PIN26 30
+#define PORTE_PIN31 31
+
+#define TEENSY_PIN24_IOPORT IOPORT5
+#define TEENSY_PIN25_IOPORT IOPORT5
+#define TEENSY_PIN26_IOPORT IOPORT5
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/PJRC_TEENSY_LC/board.mk b/os/hal/boards/PJRC_TEENSY_LC/board.mk new file mode 100644 index 0000000..85c643a --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_LC/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c index 1e10241..e6eeed8 100644 --- a/os/hal/ports/KINETIS/K20x/hal_lld.c +++ b/os/hal/ports/KINETIS/K20x/hal_lld.c @@ -39,7 +39,7 @@ #ifdef __CC_ARM
__attribute__ ((section(".ARM.__at_0x400")))
#else
-__attribute__ ((used, section(".cfmconfig")))
+__attribute__ ((used,section(".cfmconfig")))
#endif
const uint8_t _cfm[0x10] = {
0xFF, /* NV_BACKKEY3: KEY=0xFF */
@@ -84,7 +84,7 @@ void hal_lld_init(void) { }
/**
- * @brief MK20D5 clock initialization.
+ * @brief K20x clock initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function is meant to be invoked early during the system
* initialization, it is usually invoked from the file
@@ -93,16 +93,9 @@ void hal_lld_init(void) { *
* @special
*/
-void mk20d50_clock_init(void) {
+void k20x_clock_init(void) {
#if !KINETIS_NO_INIT
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
- uint32_t ratio, frdiv;
- uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
- int ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
- int i;
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
-
/* Disable the watchdog */
WDOG->UNLOCK = 0xC520;
WDOG->UNLOCK = 0xD928;
@@ -115,14 +108,24 @@ void mk20d50_clock_init(void) { SIM_SCGC5_PORTE;
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
/* Configure FEI mode */
MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
(KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI */
+ /* Set clock dividers */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] = 0;
@@ -132,8 +135,13 @@ void mk20d50_clock_init(void) { * Start in FEI mode
*/
- /* Disable capacitors for crystal */
- OSC->CR = 0;
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* TODO: need to add more flexible calculation, specially regarding
* divisors which may not be available depending on the XTAL
@@ -141,13 +149,13 @@ void mk20d50_clock_init(void) { */
/* Enable OSC, low power mode */
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
- if (KINETIS_XTAL_FREQUENCY > 8000000)
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
MCG->C2 |= MCG_C2_RANGE0(2);
else
MCG->C2 |= MCG_C2_RANGE0(1);
frdiv = 7;
- ratio = KINETIS_XTAL_FREQUENCY / 31250;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
for (i = 0; i < ratio_quantity; ++i) {
if (ratio == ratios[i]) {
frdiv = i;
@@ -170,22 +178,42 @@ void mk20d50_clock_init(void) { /*
* Now in FBE mode
*/
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /*
+ * Config PLL input for 2 MHz
+ * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+ */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
- /* Config PLL input for 2 MHz */
- MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY / 2000000) - 1);
-
- /* Config PLL for 96 MHz output */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /*
+ * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+ */
+ for(i = 24; i < 56; i++)
+ {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+ {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
- /* Wait for PLL to start using crystal as its input */
- while (!(MCG->S & MCG_S_PLLST));
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
- /* Wait for PLL to lock */
- while (!(MCG->S & MCG_S_LOCK0));
+ /* Wait for PLL to start using crystal as its input, and to lock */
+ while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
/*
* Now in PBE mode
*/
+ /* Set the PLL dividers for the different clocks */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
@@ -196,7 +224,9 @@ void mk20d50_clock_init(void) { /*
* Now in PEE mode
*/
-#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
#endif /* !KINETIS_NO_INIT */
}
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.h b/os/hal/ports/KINETIS/K20x/hal_lld.h index 3544797..31364cf 100644 --- a/os/hal/ports/KINETIS/K20x/hal_lld.h +++ b/os/hal/ports/KINETIS/K20x/hal_lld.h @@ -15,8 +15,8 @@ */
/**
- * @file KL2x/hal_lld.h
- * @brief Kinetis KL2x HAL subsystem low level driver header.
+ * @file K20x/hal_lld.h
+ * @brief Kinetis K20x HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
@@ -25,7 +25,6 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-#include "mk20d5.h"
#include "kinetis_registry.h"
/*===========================================================================*/
@@ -45,16 +44,6 @@ /** @} */
/**
- * @brief Maximum system and core clock (f_SYS) frequency.
- */
-#define KINETIS_SYSCLK_MAX 48000000
-
-/**
- * @brief Maximum bus clock (f_BUS) frequency.
- */
-#define KINETIS_BUSCLK_MAX 24000000
-
-/**
* @name Internal clock sources
* @{
*/
@@ -94,24 +83,56 @@ #endif
/**
- * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
- * @note The allowed range is 1...16.
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system clocks (OUTDIV1).
+ * @note The allowed range is 1..16
* @note The default value is calculated for a 48 MHz system clock
* from a 96 MHz PLL output.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV1 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for bus clock (OUTDIV2).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz bus clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV2 2
+ #endif
#endif
/**
- * @brief Additional clock divider bus/flash clocks (OUTDIV4).
- * @note The allowed range is 1...8.
- * @note This divider is on top of the OUTDIV1 divider.
- * @note The default value is calculated for 24 MHz bus/flash clocks
- * from a 96 MHz PLL output and 48 MHz core/system clock.
+ * @brief Clock divider for flash clock (OUTDIV4).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 24 MHz flash clock
+ * from a 96 MHz PLL output
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV4 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 4
+ #endif
#endif
/**
@@ -140,32 +161,21 @@ * @brief MCU system/core clock frequency.
*/
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
#endif
/**
- * @brief MCU bus/flash clock frequency.
+ * @brief MCU bus clock frequency.
*/
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
#endif
/**
- * @brief UART0 clock frequency.
- * @note The default value is based on 96 MHz PLL/2 source.
- * If you use a different source, such as the FLL,
- * you must set this properly.
+ * @brief MCU flash clock frequency.
*/
-#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
-#endif
-
-/**
- * @brief UART0 clock source.
- * @note The default value is to use PLL/2 or FLL source.
- */
-#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_SRC 1
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif
/** @} */
@@ -175,29 +185,52 @@ /*===========================================================================*/
#if !defined(KINETIS_SYSCLK_FREQUENCY)
-#error KINETIS_SYSCLK_FREQUENCY must be defined
+ #error KINETIS_SYSCLK_FREQUENCY must be defined
#endif
#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
-#error KINETIS_SYSCLK_FREQUENCY out of range
+ #error KINETIS_SYSCLK_FREQUENCY out of range
#endif
#if !defined(KINETIS_BUSCLK_FREQUENCY)
-#error KINETIS_BUSCLK_FREQUENCY must be defined
+ #error KINETIS_BUSCLK_FREQUENCY must be defined
#endif
#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
-#error KINETIS_BUSCLK_FREQUENCY out of range
+ #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+ #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+ #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
- KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
-#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+ KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
- KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
-#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
#endif
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
@@ -259,7 +292,7 @@ typedef uint32_t halrtcnt_t; extern "C" {
#endif
void hal_lld_init(void);
- void mk20d50_clock_init(void);
+ void k20x_clock_init(void);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/KINETIS/K20x/kinetis_registry.h b/os/hal/ports/KINETIS/K20x/kinetis_registry.h index 024a424..4c70e84 100644 --- a/os/hal/ports/KINETIS/K20x/kinetis_registry.h +++ b/os/hal/ports/KINETIS/K20x/kinetis_registry.h @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -15,8 +16,8 @@ */
/**
- * @file KL2x/kinetis_registry.h
- * @brief KL2x capabilities registry.
+ * @file K20x/kinetis_registry.h
+ * @brief K20x capabilities registry.
*
* @addtogroup HAL
* @{
@@ -25,31 +26,230 @@ #ifndef _KINETIS_REGISTRY_H_
#define _KINETIS_REGISTRY_H_
+#if !defined(K20x) || defined(__DOXYGEN__)
+#define K20x
+#endif
+
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
- * @name KL2x capabilities
+ * @name K20x capabilities
* @{
*/
-/* EXT attributes.*/
+/*===========================================================================*/
+/* K20x5 */
+/*===========================================================================*/
+#if defined(K20x5) || defined(__DOXYGEN__)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector98
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+/* EXT attributes.*/
#define KINETIS_PORTA_IRQ_VECTOR VectorE0
#define KINETIS_PORTB_IRQ_VECTOR VectorE4
#define KINETIS_PORTC_IRQ_VECTOR VectorE8
#define KINETIS_PORTD_IRQ_VECTOR VectorEC
#define KINETIS_PORTE_IRQ_VECTOR VectorF0
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+#define KINETIS_HAS_I2C1 FALSE
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector80
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector90
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR Vector84
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector8C
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector94
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SPI1 FALSE
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR VectorA4
+#define KINETIS_FTM1_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_FTM2 FALSE
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR VectorB8
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR VectorBC
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR VectorC0
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR VectorC4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorCC
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorDC
+
+/*===========================================================================*/
+/* K20x7 */
+/*===========================================================================*/
+#elif defined(K20x7)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 72000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/**
+ * @name K20x7 attributes
+ * @{
+ */
/* ADC attributes.*/
#define KINETIS_HAS_ADC0 TRUE
-#define KINETIS_ADC0_IRQ_VECTOR Vector98
+#define KINETIS_ADC0_IRQ_VECTOR Vector124
+#define KINETIS_HAS_ADC1 TRUE
+#define KINETIS_ADC1_IRQ_VECTOR Vector128
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR Vector184
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR Vector19C
+#define KINETIS_PORTB_IRQ_VECTOR Vector1A0
+#define KINETIS_PORTC_IRQ_VECTOR Vector1A4
+#define KINETIS_PORTD_IRQ_VECTOR Vector1A8
+#define KINETIS_PORTE_IRQ_VECTOR Vector1AC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
/* I2C attributes.*/
-#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR VectorA0
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR VectorA4
-/* USB attributes */
-#define KINETIS_USB_IRQ_VECTOR VectorCC
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR VectorF4
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR VectorFC
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector104
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorF8
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector100
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector108
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR VectorAC
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR Vector138
+#define KINETIS_FTM1_IRQ_VECTOR Vector13C
+#define KINETIS_HAS_FTM2 TRUE
+#define KINETIS_FTM2_IRQ_VECTOR Vector140
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR Vector150
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR Vector154
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR Vector158
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR Vector15C
+#define KINETIS_HAS_PIT FALSE
+#define KINETIS_PIT_CHANNELS 4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR Vector164
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR Vector194
+
+#endif /* K20xY */
/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/platform.mk b/os/hal/ports/KINETIS/K20x/platform.mk index 20502c2..baa90a2 100644 --- a/os/hal/ports/KINETIS/K20x/platform.mk +++ b/os/hal/ports/KINETIS/K20x/platform.mk @@ -1,14 +1,16 @@ # List of all platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/st_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/pwm_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/KINETIS/K20x/pwm_lld.c b/os/hal/ports/KINETIS/K20x/pwm_lld.c new file mode 100644 index 0000000..f5a8d96 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pwm_lld.c @@ -0,0 +1,390 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer FTM0 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer FTM1 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer FTM2 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->ftm->SC;
+ pwmp->ftm->SC = sr&(~FTM_SC_TOF);
+
+ if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
+ ((sr & FTM_SC_TOIE) != 0) &&
+ (pwmp->config->callback != NULL)) {
+ pwmp->config->callback(pwmp);
+ }
+
+ uint8_t n=0;
+ for(n=0;n<pwmp->channels;n++) {
+ sr = pwmp->ftm->CHANNEL[n].CnSC;
+ pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
+ if (((sr & FTM_CnSC_CHF) != 0) &&
+ ((sr & FTM_CnSC_CHIE) != 0) &&
+ (pwmp->config->channels[n].callback != NULL)) {
+ pwmp->config->channels[n].callback(pwmp);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0
+/**
+ * @brief FTM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM0 */
+
+#if KINETIS_PWM_USE_FTM1
+/**
+ * @brief FTM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM1 */
+
+#if KINETIS_PWM_USE_FTM2
+/**
+ * @brief FTM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_FTM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_FTM0_CHANNELS;
+ PWMD1.ftm = FTM0;
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_FTM1_CHANNELS;
+ PWMD2.ftm = FTM1;
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_FTM2_CHANNELS;
+ PWMD3.ftm = FTM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint16_t psc;
+ uint8_t i=0;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM0;
+ nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM1;
+ nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 |= SIM_SCGC3_FTM2;
+ nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
+ }
+#endif
+ }
+ pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
+ pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
+ |FTM_SYNC_SWSYNC_MASK;
+ pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
+ | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
+ pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
+
+ pwmp->ftm->CNTIN = 0x0000;
+ //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
+ pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ //~ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ //~ /* Prescaler register value determination.
+ //~ Prescaler register value conveniently corresponds to bit position,
+ //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (unsigned)(1 << i)) {
+ break;
+ }
+ }
+
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWMS up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
+ /* Configure period */
+ pwmp->ftm->MOD = pwmp->period-1;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
+ nvicDisableVector(FTM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
+ nvicDisableVector(FTM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
+ nvicDisableVector(FTM2_IRQn);
+ }
+#endif
+ /* Disable FTM counter.*/
+ pwmp->ftm->SC = 0;
+ pwmp->ftm->MOD = 0;
+ }
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= FTM_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= FTM_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
+ mode |= FTM_CnSC_CHIE;
+
+ pwmp->ftm->CHANNEL[channel].CnSC = mode;
+ pwmp->ftm->CHANNEL[channel].CnV = width;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->ftm->CHANNEL[channel].CnSC = 0;
+ pwmp->ftm->CHANNEL[channel].CnV = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC |= FTM_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC &= ~FTM_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/pwm_lld.h b/os/hal/ports/KINETIS/K20x/pwm_lld.h new file mode 100644 index 0000000..176e8a8 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pwm_lld.h @@ -0,0 +1,270 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x7/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_FTM0)
+ #define KINETIS_PWM_USE_FTM0 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM1)
+ #define KINETIS_PWM_USE_FTM1 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM2)
+ #define KINETIS_PWM_USE_FTM2 FALSE
+#endif
+
+/**
+ * @brief FTM0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM0_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM1_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM2_PRIORITY 12
+#endif
+
+/** @} */
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
+#error "PWM driver activated but no FTM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the FTM registers block.
+ */
+ FTM_TypeDef *ftm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ do { \
+ (pwmp)->ftm->MOD = ((period) - 1); \
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+ } while(0)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.c b/os/hal/ports/KINETIS/K20x/serial_lld.c deleted file mode 100644 index 0092747..0000000 --- a/os/hal/ports/KINETIS/K20x/serial_lld.c +++ /dev/null @@ -1,327 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/serial_lld.c
- * @brief Kinetis K20x Serial Driver subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "mk20d5.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SD1 driver identifier.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- 38400
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] u pointer to an UART I/O block
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- UART_TypeDef *u = sdp->uart;
- uint8_t s1 = u->S1;
-
- if (s1 & UARTx_S1_RDRF) {
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if (s1 & UARTx_S1_TDRE) {
- msg_t b;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- u->C2 &= ~UARTx_C2_TIE;
- } else {
- u->D = b;
- }
- }
-}
-
-/**
- * @brief Attempts a TX preload
- */
-static void preload(SerialDriver *sdp) {
- UART_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b = oqGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- return;
- }
- u->D = b;
- u->C2 |= UARTx_C2_TIE;
- }
-}
-
-/**
- * @brief Driver output notification.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD1);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
-}
-#endif
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(UART_TypeDef *uart, const SerialConfig *config)
-{
- uint32_t divisor = (KINETIS_SYSCLK_FREQUENCY * 2 + 1) / config->sc_speed;
-
- /* Disable UART while configuring */
- uart->C2 &= ~(UARTx_C2_RE | UARTx_C2_TE);
- uart->C1 = 0;
-
- uart->BDH = UARTx_BDH_SBR(divisor >> 13) | (uart->BDH & ~UARTx_BDH_SBR_MASK);
- uart->BDL = divisor >> 5;
- uart->C4 = UARTx_C4_BRFA(divisor) | (uart->C4 & ~UARTx_C4_BRFA_MASK);
-
- uart->C2 |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
- uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/* TODO:
- * UART0_Error is Vector84
- * UART1_Error is Vector8C
- * UART2_Error is Vector94
- */
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector80) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector88) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector90) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if KINETIS_SERIAL_USE_UART0
- /* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
- SD1.uart = UART0;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- /* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
- SD2.uart = UART1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart = UART2;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- SIM->SCGC4 |= SIM_SCGC4_UART0;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- SIM->SCGC4 |= SIM_SCGC4_UART1;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- SIM->SCGC4 |= SIM_SCGC4_UART2;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART2 */
-
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- /* TODO: Resets the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- nvicDisableVector(UART0Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART0;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- nvicDisableVector(UART1Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART1;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- nvicDisableVector(UART2Status_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART2;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.h b/os/hal/ports/KINETIS/K20x/serial_lld.h deleted file mode 100644 index 736cfe3..0000000 --- a/os/hal/ports/KINETIS/K20x/serial_lld.h +++ /dev/null @@ -1,163 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/serial_lld.h
- * @brief Kinetis K20x Serial Driver subsystem low level driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART0 FALSE
-#endif
-/**
- * @brief SD2 driver enable switch.
- * @details If set to @p TRUE the support for SD2 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART1 FALSE
-#endif
-/**
- * @brief SD3 driver enable switch.
- * @details If set to @p TRUE the support for SD3 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART2 FALSE
-#endif
-
-/**
- * @brief UART0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART0_PRIORITY 12
-#endif
-
-/**
- * @brief UART1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART1_PRIORITY 12
-#endif
-
-/**
- * @brief UART2 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART2_PRIORITY 12
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t sc_speed;
- /* End of the mandatory fields.*/
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- input_queue_t iqueue; \
- /* Output queue.*/ \
- output_queue_t oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the UART registers block.*/ \
- UART_TypeDef *uart;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.c b/os/hal/ports/KINETIS/K20x/spi_lld.c index 132580f..29ab4e8 100644 --- a/os/hal/ports/KINETIS/K20x/spi_lld.c +++ b/os/hal/ports/KINETIS/K20x/spi_lld.c @@ -30,10 +30,6 @@ /* Driver local definitions. */
/*===========================================================================*/
-#if !defined(KINETIS_SPI_USE_SPI0)
-#define KINETIS_SPI_USE_SPI0 TRUE
-#endif
-
#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
#endif
@@ -54,8 +50,35 @@ #define KINETIS_SPI0_TX_DMA_CHANNEL 1
#endif
+#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
+#define KINETIS_SPI1_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
+#define KINETIS_SPI1_TX_DMA_CHANNEL 1
+#endif
+
+#if KINETIS_SPI_USE_SPI0
#define DMAMUX_SPI_RX_SOURCE 16
#define DMAMUX_SPI_TX_SOURCE 17
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+#define DMAMUX_SPI_RX_SOURCE 18
+#define DMAMUX_SPI_TX_SOURCE 19
+#endif
/*===========================================================================*/
/* Driver exported variables. */
@@ -66,6 +89,11 @@ SPIDriver SPID1;
#endif
+/** @brief SPI1 driver identifier.*/
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -137,7 +165,9 @@ static void spi_stop_xfer(SPIDriver *spip) /* Driver interrupt handlers. */
/*===========================================================================*/
-OSAL_IRQ_HANDLER(Vector40) {
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
/* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
@@ -150,6 +180,25 @@ OSAL_IRQ_HANDLER(Vector40) { OSAL_IRQ_EPILOGUE();
}
+#endif
+
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID2);
+
+ _spi_isr_code(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -163,6 +212,9 @@ void spi_lld_init(void) { #if KINETIS_SPI_USE_SPI0
spiObjectInit(&SPID1);
#endif
+#if KINETIS_SPI_USE_SPI1
+ spiObjectInit(&SPID2);
+#endif
}
/**
@@ -193,6 +245,22 @@ void spi_lld_start(SPIDriver *spip) { }
#endif
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI1;
+
+ SPID2.spi = SPI1;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
@@ -201,6 +269,7 @@ void spi_lld_start(SPIDriver *spip) { /* Clear DMA error flags */
DMA->ERR = 0x0F;
+#if KINETIS_SPI_USE_SPI0
/* Rx, select SPI Rx FIFO */
DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
@@ -239,6 +308,48 @@ void spi_lld_start(SPIDriver *spip) { DMA_ATTR_DSIZE(dma_size);
DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
}
}
@@ -264,10 +375,20 @@ void spi_lld_stop(SPIDriver *spip) { /* SPI halt.*/
spip->spi->MCR |= SPIx_MCR_HALT;
}
-#endif
/* Disable the clock for SPI0 */
SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI1 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
+#endif
}
}
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.h b/os/hal/ports/KINETIS/K20x/spi_lld.h index 23c6812..a1f2a99 100644 --- a/os/hal/ports/KINETIS/K20x/spi_lld.h +++ b/os/hal/ports/KINETIS/K20x/spi_lld.h @@ -55,17 +55,39 @@ #define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
#endif
+/**
+ * @brief SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief SPI1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
-#define KINETIS_HAS_SPI0 TRUE
-
#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
#error "SPI0 not present in the selected device"
#endif
-#if !KINETIS_SPI_USE_SPI0
+#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
+#error "Only one SPI peripheral can be enabled"
+#endif
+
+#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
#error "SPI driver activated but no SPI peripheral assigned"
#endif
@@ -74,6 +96,11 @@ #error "Invalid IRQ priority assigned to SPI0"
#endif
+#if KINETIS_SPI_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -205,6 +232,10 @@ struct SPIDriver { extern SPIDriver SPID1;
#endif
+#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.c b/os/hal/ports/KINETIS/K20x/st_lld.c deleted file mode 100644 index 1f8cb63..0000000 --- a/os/hal/ports/KINETIS/K20x/st_lld.c +++ /dev/null @@ -1,98 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/KL2x/st_lld.c
- * @brief ST Driver subsystem low level driver code.
- *
- * @addtogroup ST
- * @{
- */
-
-#include "hal.h"
-
-#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
-/**
- * @brief System Timer vector.
- * @details This interrupt is used for system tick in periodic mode.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(SysTick_Handler) {
-
- OSAL_IRQ_PROLOGUE();
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ST driver initialization.
- *
- * @notapi
- */
-void st_lld_init(void) {
-#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
- /* Periodic systick mode, the Cortex-Mx internal systick timer is used
- in this mode.*/
- SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* IRQ enabled.*/
- nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-}
-
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.h b/os/hal/ports/KINETIS/K20x/st_lld.h deleted file mode 100644 index 24044e5..0000000 --- a/os/hal/ports/KINETIS/K20x/st_lld.h +++ /dev/null @@ -1,156 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/st_lld.h
- * @brief ST Driver subsystem low level driver header.
- * @details This header is designed to be include-able without having to
- * include other files from the HAL.
- *
- * @addtogroup ST
- * @{
- */
-
-#ifndef _ST_LLD_H_
-#define _ST_LLD_H_
-
-#include "mcuconf.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SysTick timer IRQ priority.
- */
-#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_ST_IRQ_PRIORITY 8
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void st_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Driver inline functions. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the time counter value.
- *
- * @return The counter value.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_counter(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Starts the alarm.
- * @note Makes sure that no spurious alarms are triggered after
- * this call.
- *
- * @param[in] time the time to be set for the first alarm
- *
- * @notapi
- */
-static inline void st_lld_start_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-
-}
-
-/**
- * @brief Sets the alarm time.
- *
- * @param[in] time the time to be set for the next alarm
- *
- * @notapi
- */
-static inline void st_lld_set_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Returns the current alarm time.
- *
- * @return The currently set alarm time.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_alarm(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Determines if the alarm is active.
- *
- * @return The alarm status.
- * @retval false if the alarm is not active.
- * @retval true is the alarm is active
- *
- * @notapi
- */
-static inline bool st_lld_is_alarm_active(void) {
-
- return false;
-}
-
-#endif /* _ST_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.c b/os/hal/ports/KINETIS/KL2x/hal_lld.c index dce1588..77addf0 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_lld.c +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.c @@ -40,7 +40,7 @@ #ifdef __CC_ARM
__attribute__ ((section(".ARM.__at_0x400")))
#else
-__attribute__ ((used, section(".cfmconfig")))
+__attribute__ ((used,section(".cfmconfig")))
#endif
const uint8_t _cfm[0x10] = {
0xFF, /* NV_BACKKEY3: KEY=0xFF */
@@ -55,9 +55,20 @@ const uint8_t _cfm[0x10] = { 0xFF, /* NV_FPROT2: PROT=0xFF */
0xFF, /* NV_FPROT1: PROT=0xFF */
0xFF, /* NV_FPROT0: PROT=0xFF */
+#if defined(KINETIS_NV_FSEC_BYTE)
+ #warning Please triple check your FSEC setting: KEYEN!=b10, MEEN==b10, SEC!=b10 leads to an unmodifiable chip.
+ KINETIS_NV_FSEC_BYTE,
+#else /* KINETIS_NV_FSEC_BYTE */
0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+#endif /* KINETIS_NV_FSEC_BYTE */
+#if defined(KINETIS_NV_FOPT_BYTE)
+ KINETIS_NV_FOPT_BYTE,
+#else /* KINETIS_NV_FOPT_BYTE */
0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ /* on KL27: bit7-6:BOOTSRC_SEL=0b11 (11=from ROM; 00=from FLASH)
+ bit1:BOOTPIN_OPT=1 (NMI pin not sampled at boot) */
+#endif /* KINETIS_NV_FOPT_BYTE */
0xFF,
0xFF
};
@@ -91,6 +102,7 @@ void hal_lld_init(void) { */
void kl2x_clock_init(void) {
#if !KINETIS_NO_INIT
+
/* Disable COP watchdog */
SIM->COPC = 0;
@@ -107,16 +119,118 @@ void kl2x_clock_init(void) { /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
+#if KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_LIRC8M
+ /* Out of reset, the MCU is in LIRC8M mode. */
+ /* Except when coming out of the ROM bootloader, then
+ * the MCU is in HIRC mode; so better set it explicitly here. */
+
+ /* Switching to LIRC8M mode, page 414 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_C2[IRCS] to select LIRC 8M. */
+ MCG->C2 |= MCG_C2_IRCS;
+
+ /* (2) Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional). */
+ MCG->C1 |= MCG_C1_IRCLKEN;
+
+ /* (2) Write 01b to MCG_C1[CLKS] to select LIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_LIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm LIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_LIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_HIRC
+ /* Switching to HIRC mode, page 413 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_MC[HIRCEN] to enable HIRC (optional). */
+ MCG->MC |= MCG_MC_HIRCEN;
+
+ /* (2) Write 00b to MCG_C1[CLKS] to select HIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_HIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm HIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_EXT
+ /* Assuming we have an external crystal, frequency
+ * specified with KINETIS_XTAL_FREQUENCY.
+ *
+ * Note: Except with 32768 kHz crystal (low-freq mode),
+ * external load capacitors and a feedback resistor
+ * are *required*. Additionally, a series resistor is
+ * required in the high-gain mode, and forbidden in
+ * the low-power mode.
+ * In this case, the internal caps can be configured
+ * via KINETIS_BOARD_OSCILLATOR_SETTING.
+ * (Page 420 of the KL27 manual.) */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* Switching to EXT mode, page 413 of the KL27 manual. */
+
+ /* (1) Configure MCG_C2[EREFS0] for external clock source selection. */
+ #if KINETIS_XTAL_FREQUENCY == 32768 /* low range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(0);
+ #elif (KINETIS_XTAL_FREQUENCY >= 1000000 && \
+ KINETIS_XTAL_FREQUENCY <= 8000000) /* high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(1);
+ #elif (KINETIS_XTAL_FREQUENCY > 8000000 && \
+ KINETIS_XTAL_FREQUENCY <= 32000000) /* very high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(2);
+ #else /* KINETIS_XTAL_FREQUENCY == */
+ #error KINETIS_XTAL_FREQUENCY not in allowed range
+ #endif /* KINETIS_XTAL_FREQUENCY == */
+
+ #if defined(KINETIS_XTAL_HIGH_GAIN) && KINETIS_XTAL_HIGH_GAIN
+ MCG->C2 |= MCG_C2_HGO0;
+ #endif /* KINETIS_XTAL_HIGH_GAIN */
+
+ /* Oscillator requested. */
+ MCG->C2 |= MCG_C2_EREFS0;
+
+ /* (2) Write 10b to MCG_C1[CLKS] to select external clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_EXT;
+
+ /* (3) Check MCG_S[CLKST] to confirm external clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT )
+ ;
+
+#else /* KINETIS_MCGLITE_MODE */
+#error Unimplemented KINETIS_MCGLITE_MODE
+#endif /* KINETIS_MCGLITE_MODE */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
+
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
/* This is the default mode at reset. */
/* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
* OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 24 MHz */
- SIM_CLKDIV1_OUTDIV4(0); /* OUTDIV4 = divide-by-1 => 24 MHz */
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
+ /* TODO: check this, for generality */
/*
* FLL Enabled External (FEE) MCG Mode
* 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
@@ -138,14 +252,20 @@ void kl2x_clock_init(void) { * OUTDIV1 (divider for core/system and bus/flash clock)
* OUTDIV4 (additional divider for bus/flash clock) */
SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(KINETIS_MCG_FLL_OUTDIV1 - 1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_MCG_FLL_OUTDIV4 - 1);
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FEE mode: */
@@ -183,35 +303,40 @@ void kl2x_clock_init(void) { seems to omit it. */
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
/*
* PLL Enabled External (PEE) MCG Mode
- * 48 MHz core, 24 MHz bus - using 8 MHz crystal with PLL.
+ * Uses external crystal (KINETIS_XTAL_FREQUENCY) with PLL.
* f_MCGOUTCLK = (OSCCLK / PLL_R) * M
- * = 8 MHz / 2 * 24 = 96 MHz
+ * OSCCLK = KINETIS_XTAL_FREQUENCY
* PLL_R is the reference divider selected by C5[PRDIV0]
+ * (OSCCLK/PLL_R must be between 2 and 4 MHz)
* M is the multiplier selected by C6[VDIV0]
*
+ * Running from PLL, so assuming PLLCLK = MCGOUTCLK.
+ *
* Then the core/system and bus/flash clocks are divided:
* f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
* f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
*/
- /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
- * OUTDIV1 (divider for core/system and bus/flash clock)
- * OUTDIV4 (additional divider for bus/flash clock) */
- SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 48 MHz */
- SIM_CLKDIV1_OUTDIV4(1); /* OUTDIV4 = divide-by-2 => 24 MHz */
-
- SIM->SOPT2 =
- SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
- SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
-
/* EXTAL0 and XTAL0 */
PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+ /* Start in FEI mode */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
/* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
/* To change from FEI mode to FBE mode: */
@@ -220,15 +345,27 @@ void kl2x_clock_init(void) { resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
Use high-gain mode by setting C2[HGO0] instead if external
feedback resistor Rf is installed. */
- MCG->C2 =
- MCG_C2_RANGE0(2) | /* very high frequency range */
- MCG_C2_EREFS0; /* external reference (using a crystal) */
+ MCG->C2 = MCG_C2_EREFS0; /* external reference (using a crystal) */
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 |= MCG_C2_RANGE0(2);
+ else
+ MCG->C2 |= MCG_C2_RANGE0(1);
/* (2) Write to C1 to select the clock mode. */
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
- MCG_C1_CLKS_ERCLK | /* Use ERCLK for system clock, MCGCLKOUT. */
- MCG_C1_FRDIV(3); /* Divide ERCLK / 256 for FLL reference. */
- /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz.
- 8 MHz / 256 = 31.25 kHz. */
+ MCG_C1_CLKS_ERCLK | /* Use Ext Ref Clock for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(frdiv); /* Divide ERCLK / 256 for FLL reference. */
+ /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz. */
+
MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
@@ -254,11 +391,25 @@ void kl2x_clock_init(void) { /* (2) Then configure C5[PRDIV0] to generate the
correct PLL reference frequency. */
- MCG->C5 = MCG_C5_PRDIV0(1); /* PLL External Reference Divide by 2 */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */
+ /* PLL External Reference Divide by ... */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
/* (3) Then from FBE transition to PBE mode. */
/* (3)(b) C6[PLLS]=1 to select PLL. */
- /* (3)(b) C6[VDIV0]=5'b0000 (x24) 2 MHz * 24 = 48 MHz. */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /* (3)(b) C6[VDIV0]= PLLIN MHz * i = PLLCLK MHz. */
+ /* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match */
+ for(i = 24; i < 56; i++) {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY)) {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
/* (3)(d) Loop until S[PLLST], indicating PLL
is the PLLS clock source. */
while ((MCG->S & MCG_S_PLLST) == 0)
@@ -270,14 +421,26 @@ void kl2x_clock_init(void) { /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
+ /* Set the PLL dividers for the different clocks */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock)
+ * - these are computed in .h */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
+
/* (4) Transition from PBE mode to PEE mode. */
/* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
// Switch to PEE mode
// Select PLL output (CLKS=0)
- // FLL external reference divider (FRDIV=3)
+ // FLL external reference divider (FRDIV) already set
// External reference clock for FLL (IREFS=0)
- MCG->C1 = MCG_C1_CLKS(0) |
- MCG_C1_FRDIV(3);
+ MCG->C1 = MCG_C1_CLKS(0);
/* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
; /* wait until clock switched to PLL output */
@@ -288,6 +451,8 @@ void kl2x_clock_init(void) { #error Unimplemented KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+#endif /* KINETIS_HAS_MCG_LITE */
+
#endif /* !KINETIS_NO_INIT */
}
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.h b/os/hal/ports/KINETIS/KL2x/hal_lld.h index f93d920..a10c21c 100644 --- a/os/hal/ports/KINETIS/KL2x/hal_lld.h +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.h @@ -25,7 +25,7 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-#include "kl25z.h"
+#include "kl2xz.h"
#include "kinetis_registry.h"
/*===========================================================================*/
@@ -44,15 +44,30 @@ #define PLATFORM_NAME "Kinetis"
/** @} */
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
/**
- * @brief Maximum system and core clock (f_SYS) frequency.
+ * @name Internal clock sources
+ * @{
*/
-#define KINETIS_SYSCLK_MAX 48000000
+#define KINETIS_HIRC 48000000 /**< High-frequency internal reference clock (USB recovery). */
+#define KINETIS_LIRC_8 8000000 /**< Low-frequency internal reference clock (faster). */
+#define KINETIS_LIRC_2 2000000 /**< Low-frequency internal reference clock (slower). */
+/** @} */
/**
- * @brief Maximum bus clock (f_BUS) frequency.
+ * @name MCG modes of operation
+ * @{
*/
-#define KINETIS_BUSCLK_MAX 24000000
+#define KINETIS_MCGLITE_MODE_LIRC8M 1 /**< Low frequency internal reference mode (8MHz). */
+#define KINETIS_MCGLITE_MODE_LIRC2M 2 /**< Low frequency internal reference mode (2MHz). */
+#define KINETIS_MCGLITE_MODE_HIRC 3 /**< High frequency internal reference mode (with optional USB recovery). */
+#define KINETIS_MCGLITE_MODE_EXT 4 /**< External reference mode. */
+/** @} */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
/**
* @name Internal clock sources
@@ -62,6 +77,10 @@ #define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
/** @} */
+/**
+ * @name MCG modes of operation
+ * @{
+ */
#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
@@ -70,6 +89,9 @@ #define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+/** @} */
+
+#endif /* KINETIS_HAS_MCG_LITE */
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -93,14 +115,29 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#endif
+#if !defined(KINETIS_MCGLITE_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
/**
* @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
* @note The allowed range is 1...16.
* @note The default value is calculated for a 48 MHz system clock
* from a 96 MHz PLL output.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV1 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
#endif
/**
@@ -110,8 +147,12 @@ * @note The default value is calculated for 24 MHz bus/flash clocks
* from a 96 MHz PLL output and 48 MHz core/system clock.
*/
-#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_OUTDIV4 2
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 ((KINETIS_PLLCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV1)/KINETIS_BUSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 2
+ #endif
#endif
/**
@@ -140,14 +181,14 @@ * @brief MCU system/core clock frequency.
*/
#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
#endif
/**
* @brief MCU bus/flash clock frequency.
*/
#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif
/**
@@ -190,14 +231,20 @@ #error KINETIS_BUSCLK_FREQUENCY out of range
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
- KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
-#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
#endif
-#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
- KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
-#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
#endif
#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_registry.h b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h index dcf3576..92ea0cc 100644 --- a/os/hal/ports/KINETIS/KL2x/kinetis_registry.h +++ b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,6 +26,10 @@ #ifndef _KINETIS_REGISTRY_H_
#define _KINETIS_REGISTRY_H_
+#if !defined(KL2x) || defined(__DOXYGEN__)
+#define KL2x
+#endif
+
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
@@ -34,16 +39,217 @@ * @{
*/
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+/*===========================================================================*/
+/* Common features */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
/* ADC attributes.*/
#define KINETIS_HAS_ADC0 TRUE
#define KINETIS_ADC0_IRQ_VECTOR Vector7C
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ FALSE
+
+/* GPT attributes.*/
+#define KINETIS_PIT_IRQ_VECTOR Vector98
+#define KINETIS_HAS_PIT_COMMON_IRQ TRUE
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_HAS_PIT2 FALSE
+#define KINETIS_HAS_PIT3 FALSE
/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
#define KINETIS_I2C0_IRQ_VECTOR Vector60
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR Vector64
+
+/* Serial attributes */
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector74
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector78
+#define KINETIS_HAS_SERIAL_ERROR_IRQ FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector68
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR Vector6C
+
+/* TPM attributes.*/
+#define KINETIS_HAS_TPM0 TRUE
+#define KINETIS_TPM0_CHANNELS 6
+#define KINETIS_TPM0_IRQ_VECTOR Vector84
+#define KINETIS_HAS_TPM1 TRUE
+#define KINETIS_TPM1_CHANNELS 2
+#define KINETIS_TPM1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_TPM2 TRUE
+#define KINETIS_TPM2_CHANNELS 2
+#define KINETIS_TPM2_IRQ_VECTOR Vector8C
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorA0
+
+/* FTFA attributes.*/
+#define KINETIS_FTFA_IRQ_VECTOR Vector54
+
+/* LPTMR attributes */
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorB0
+
+/*===========================================================================*/
+/* KL25 */
+/*===========================================================================*/
+#if defined(KL25) || defined(__DOXYGEN__)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL26 */
+/*===========================================================================*/
+#elif defined(KL26) /* defined(KL25) */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL27 */
+/*===========================================================================*/
+#elif defined(KL27Zxxx) || defined(KL27Zxx) /* defined(KL26) */
+
+#if !defined(KL27)
+#define KL27
+#endif
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE TRUE
+
+/* Note: on this device, SERIAL2 IRQ is alternatively FlexIO IRQ. */
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL0_IS_LPUART TRUE
+#define KINETIS_SERIAL1_IS_LPUART TRUE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG FALSE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/*===========================================================================*/
+/* KL27Zxxx (MKL27Z128* and MKL27Z256*) specific */
+/*===========================================================================*/
+#if defined(KL27Zxxx)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/*===========================================================================*/
+/* KL27Zxx (MKL27Z32* and MKL27Z264*) specific */
+/*===========================================================================*/
+#elif defined(KL27Zxx) /* defined(KL27Zxxx) */
+
+/* Has CRC module */
+/* Does not have USB voltage regulator */
+/* Does have KEEP_ALIVE USB feature */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTB to PORTE */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ TRUE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+#endif /* defined(KL27Zxx) */
+
+#else /* ! (KL25 || KL26 || KL27) */
+#error MCU type not described in kinetis_registry
+#endif /* KL2Y */
/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h b/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h deleted file mode 100644 index 99ffc9c..0000000 --- a/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h +++ /dev/null @@ -1,120 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/kinetis_tpm.h
- * @brief Kinetis TPM registers layout header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _KINETIS_TPM_H_
-#define _KINETIS_TPM_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name TPM_SC register
- * @{
- */
-#define TPM_SC_CMOD_DISABLE (0 << 3)
-#define TPM_SC_CMOD_LPTPM_CLK (1 << 3)
-#define TPM_SC_CMOD_LPTPM_EXTCLK (2 << 3)
-#define TPM_SC_CPWMS (1 << 5)
-#define TPM_SC_TOIE (1 << 6)
-#define TPM_SC_TOF (1 << 7)
-#define TPM_SC_DMA (1 << 8)
-/** @} */
-
-/**
- * @name TPM_MOD register
- * @{
- */
-#define TPM_MOD_MASK (0xFFFF)
-/** @} */
-
-/**
- * @name TPM_CnSC register
- * @{
- */
-#define TPM_CnSC_DMA (1 << 0)
-#define TPM_CnSC_ELSA (1 << 2)
-#define TPM_CnSC_ELSB (1 << 3)
-#define TPM_CnSC_MSA (1 << 4)
-#define TPM_CnSC_MSB (1 << 5)
-#define TPM_CnSC_CHIE (1 << 6)
-#define TPM_CnSC_CHF (1 << 7)
-/** @} */
-
-/**
- * @name TPM_CnV register
- * @{
- */
-#define TPM_CnV_VAL_MASK (0xFFFF)
-/** @} */
-
-/**
- * @name TPM_STATUS register
- * @{
- */
-#define TPM_STATUS_CH0F (1 << 0)
-#define TPM_STATUS_CH1F (1 << 1)
-#define TPM_STATUS_CH2F (1 << 2)
-#define TPM_STATUS_CH3F (1 << 3)
-#define TPM_STATUS_CH4F (1 << 4)
-#define TPM_STATUS_CH5F (1 << 5)
-#define TPM_STATUS_TOF (1 << 8)
-/** @} */
-
-/**
- * @name TPM_CONF register
- * @{
- */
-#define TPM_CONF_DOZEEN (1 << 5)
-#define TPM_CONF_DBGMODE_CONT (3 << 6)
-#define TPM_CONF_DBGMODE_PAUSE (0 << 6)
-#define TPM_CONF_GTBEEN (1 << 9)
-#define TPM_CONF_CSOT (1 << 16)
-#define TPM_CONF_CSOO (1 << 17)
-#define TPM_CONF_CROT (1 << 18)
-#define TPM_CONF_TRGSEL(n) ((n) << 24)
-/** @{ */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-#endif /* _KINETIS_TPM_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.c b/os/hal/ports/KINETIS/KL2x/pal_lld.c deleted file mode 100644 index a894c6a..0000000 --- a/os/hal/ports/KINETIS/KL2x/pal_lld.c +++ /dev/null @@ -1,225 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013..2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pal_lld.c
- * @brief Kinetis KL2x PAL subsystem low level driver.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 I/O ports configuration.
- * @details Ports A-D(E, F, G, H) clocks enabled.
- *
- * @param[in] config the STM32 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
- int i, j;
-
- /* Enable clocking of all Ports */
- SIM->SCGC5 |= SIM_SCGC5_PORTA |
- SIM_SCGC5_PORTB |
- SIM_SCGC5_PORTC |
- SIM_SCGC5_PORTD |
- SIM_SCGC5_PORTE;
-
- for (i = 0; i < TOTAL_PORTS; i++) {
- for (j = 0; j < PADS_PER_PORT; j++) {
- pal_lld_setpadmode(config->ports[i].port,
- j,
- config->ports[i].pads[j]);
- }
- }
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
-
- (void)port;
- (void)mask;
- (void)mode;
-
-}
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-uint8_t pal_lld_readpad(ioportid_t port, uint8_t pad)
-{
- return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
-}
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-void pal_lld_writepad(ioportid_t port, uint8_t pad, uint8_t bit)
-{
- if (bit == PAL_HIGH)
- port->PDOR |= ((uint32_t) 1 << pad);
- else
- port->PDOR &= ~((uint32_t) 1 << pad);
-}
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
-{
- PORT_TypeDef *portcfg = NULL;
-
- osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
-
- if (mode == PAL_MODE_OUTPUT_PUSHPULL)
- port->PDDR |= ((uint32_t) 1 << pad);
- else
- port->PDDR &= ~((uint32_t) 1 << pad);
-
- if (port == IOPORT1)
- portcfg = PORTA;
- else if (port == IOPORT2)
- portcfg = PORTB;
- else if (port == IOPORT3)
- portcfg = PORTC;
- else if (port == IOPORT4)
- portcfg = PORTD;
- else if (port == IOPORT5)
- portcfg = PORTE;
-
- osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() - invalid port");
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_INPUT:
- case PAL_MODE_OUTPUT_PUSHPULL:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
- break;
- case PAL_MODE_INPUT_PULLUP:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE | PORTx_PCRn_PS;
- break;
- case PAL_MODE_INPUT_PULLDOWN:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE;
- break;
- case PAL_MODE_UNCONNECTED:
- case PAL_MODE_INPUT_ANALOG:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(0);
- break;
- case PAL_MODE_ALTERNATIVE_1:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
- break;
- case PAL_MODE_ALTERNATIVE_2:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(2);
- break;
- case PAL_MODE_ALTERNATIVE_3:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(3);
- break;
- case PAL_MODE_ALTERNATIVE_4:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(4);
- break;
- case PAL_MODE_ALTERNATIVE_5:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(5);
- break;
- case PAL_MODE_ALTERNATIVE_6:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(6);
- break;
- case PAL_MODE_ALTERNATIVE_7:
- portcfg->PCR[pad] = PORTx_PCRn_MUX(7);
- break;
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.h b/os/hal/ports/KINETIS/KL2x/pal_lld.h deleted file mode 100644 index 8b38709..0000000 --- a/os/hal/ports/KINETIS/KL2x/pal_lld.h +++ /dev/null @@ -1,331 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pal_lld.h
- * @brief Kinetis KL2x PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-#define PAL_MODE_ALTERNATIVE_1 0x10
-#define PAL_MODE_ALTERNATIVE_2 0x11
-#define PAL_MODE_ALTERNATIVE_3 0x12
-#define PAL_MODE_ALTERNATIVE_4 0x13
-#define PAL_MODE_ALTERNATIVE_5 0x14
-#define PAL_MODE_ALTERNATIVE_6 0x15
-#define PAL_MODE_ALTERNATIVE_7 0x16
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-#define TOTAL_PORTS 5
-#define PADS_PER_PORT 32
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef GPIO_TypeDef * ioportid_t;
-
-typedef struct {
- ioportid_t port;
- iomode_t pads[PADS_PER_PORT];
-} PortConfig;
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct
-{
- PortConfig ports[TOTAL_PORTS];
-} PALConfig;
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief First I/O port identifier.
- * @details Low level drivers can define multiple ports, it is suggested to
- * use this naming convention.
- */
-#define IOPORT1 GPIOA
-#define IOPORT2 GPIOB
-#define IOPORT3 GPIOC
-#define IOPORT4 GPIOD
-#define IOPORT5 GPIOE
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) \
- (port)->PDIR
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) \
- (port)->PDOR
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) \
- (port)->PDOR = (bits)
-
-/**
- * @brief Sets a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) \
- (port)->PSOR = (bits)
-
-/**
- * @brief Clears a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) \
- (port)->PCOR = (bits)
-
-/**
- * @brief Toggles a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be XORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits) \
- (port)->PTOR = (bits)
-
-/**
- * @brief Reads a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) 0
-
-/**
- * @brief Writes a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode) \
- _pal_lld_setpadmode(port, pad, mode)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
- void pal_lld_setpadmode(ioportid_t port,
- uint8_t pad,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/platform.mk b/os/hal/ports/KINETIS/KL2x/platform.mk index f9d3c67..8ababc3 100644 --- a/os/hal/ports/KINETIS/KL2x/platform.mk +++ b/os/hal/ports/KINETIS/KL2x/platform.mk @@ -1,13 +1,15 @@ # List of all platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/adc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/st_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/usb_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.c b/os/hal/ports/KINETIS/KL2x/pwm_lld.c index 4ba7d6e..2f56216 100644 --- a/os/hal/ports/KINETIS/KL2x/pwm_lld.c +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.c @@ -27,18 +27,6 @@ #if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define KINETIS_TPM0_CHANNELS 6
-#define KINETIS_TPM1_CHANNELS 2
-#define KINETIS_TPM2_CHANNELS 2
-
-#define KINETIS_TPM0_HANDLER Vector84
-#define KINETIS_TPM1_HANDLER Vector88
-#define KINETIS_TPM2_HANDLER Vector8C
-
-/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -80,25 +68,25 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { sr = pwmp->tpm->STATUS;
pwmp->tpm->STATUS = 0xFFFFFFFF;
- if (((sr & TPM_SC_TOF) != 0) &&
+ if (((sr & TPMx_STATUS_TOF) != 0) &&
(pwmp->config->callback != NULL))
pwmp->config->callback(pwmp);
- if (((sr & TPM_STATUS_CH0F) != 0) &&
+ if (((sr & TPMx_STATUS_CH0F) != 0) &&
(pwmp->config->channels[0].callback != NULL))
pwmp->config->channels[0].callback(pwmp);
- if (((sr & TPM_STATUS_CH1F) != 0) &&
+ if (((sr & TPMx_STATUS_CH1F) != 0) &&
(pwmp->config->channels[1].callback != NULL))
pwmp->config->channels[1].callback(pwmp);
- if (((sr & TPM_STATUS_CH2F) != 0) &&
+ if (((sr & TPMx_STATUS_CH2F) != 0) &&
(pwmp->config->channels[2].callback != NULL))
pwmp->config->channels[2].callback(pwmp);
- if (((sr & TPM_STATUS_CH3F) != 0) &&
+ if (((sr & TPMx_STATUS_CH3F) != 0) &&
(pwmp->config->channels[3].callback != NULL))
pwmp->config->channels[3].callback(pwmp);
- if (((sr & TPM_STATUS_CH4F) != 0) &&
+ if (((sr & TPMx_STATUS_CH4F) != 0) &&
(pwmp->config->channels[4].callback != NULL))
pwmp->config->channels[4].callback(pwmp);
- if (((sr & TPM_STATUS_CH5F) != 0) &&
+ if (((sr & TPMx_STATUS_CH5F) != 0) &&
(pwmp->config->channels[5].callback != NULL))
pwmp->config->channels[5].callback(pwmp);
}
@@ -113,7 +101,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM0_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD1);
@@ -127,7 +115,7 @@ OSAL_IRQ_HANDLER(KINETIS_TPM0_HANDLER) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM1_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD2);
@@ -141,7 +129,7 @@ OSAL_IRQ_HANDLER(KINETIS_TPM1_HANDLER) { *
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_TPM2_HANDLER) {
+OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD3);
@@ -238,7 +226,7 @@ void pwm_lld_start(PWMDriver *pwmp) { CPWM up-counting mode
Timer overflow interrupt disabled
DMA disabled.*/
- pwmp->tpm->SC = TPM_SC_CMOD_LPTPM_CLK | i;
+ pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i;
/* Configure period.*/
pwmp->tpm->MOD = pwmp->period - 1;
}
@@ -297,19 +285,19 @@ void pwm_lld_stop(PWMDriver *pwmp) { void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
- uint32_t mode = TPM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+ uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/
switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= TPM_CnSC_ELSB;
+ mode |= TPMx_CnSC_ELSB;
break;
case PWM_OUTPUT_ACTIVE_LOW:
- mode |= TPM_CnSC_ELSA;
+ mode |= TPMx_CnSC_ELSA;
break;
}
- if (pwmp->tpm->C[channel].SC & TPM_CnSC_CHIE)
- mode |= TPM_CnSC_CHIE;
+ if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE)
+ mode |= TPMx_CnSC_CHIE;
pwmp->tpm->C[channel].SC = mode;
pwmp->tpm->C[channel].V = width;
@@ -344,7 +332,7 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { */
void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->tpm->SC |= TPM_SC_TOIE;
+ pwmp->tpm->SC |= TPMx_SC_TOIE;
}
/**
@@ -358,7 +346,7 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { */
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->tpm->SC &= ~TPM_SC_TOIE;
+ pwmp->tpm->SC &= ~TPMx_SC_TOIE;
}
/**
@@ -375,7 +363,7 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel) {
- pwmp->tpm->C[channel].SC |= TPM_CnSC_CHIE;
+ pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE;
}
/**
@@ -392,7 +380,7 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
pwmchannel_t channel) {
- pwmp->tpm->C[channel].SC &= ~TPM_CnSC_CHIE;
+ pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE;
}
#endif /* HAL_USE_PWM */
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.h b/os/hal/ports/KINETIS/KL2x/pwm_lld.h index fe255bd..5a3d7c2 100644 --- a/os/hal/ports/KINETIS/KL2x/pwm_lld.h +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.h @@ -25,8 +25,6 @@ #ifndef _PWM_LLD_H_
#define _PWM_LLD_H_
-#include "kinetis_tpm.h"
-
#if HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/
@@ -65,16 +63,80 @@ #if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
#define KINETIS_PWM_USE_ADVANCED FALSE
#endif
+
+/**
+ * @brief TPM0 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM1 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM2 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2
+#endif
+
/** @} */
/*===========================================================================*/
/* Configuration checks. */
/*===========================================================================*/
+#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0
+#error "TPM0 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1
+#error "TPM1 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2
+#error "TPM2 not present in the selected device"
+#endif
+
#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
#error "PWM driver activated but no TPM peripheral assigned"
#endif
+#if KINETIS_PWM_USE_TPM0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_TPM0_IRQ_VECTOR)
+#error "KINETIS_TPM0_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM1_IRQ_VECTOR)
+#error "KINETIS_TPM1_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM2_IRQ_VECTOR)
+#error "KINETIS_TPM2_IRQ_VECTOR not defined"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.c b/os/hal/ports/KINETIS/KL2x/serial_lld.c deleted file mode 100644 index f0cbc46..0000000 --- a/os/hal/ports/KINETIS/KL2x/serial_lld.c +++ /dev/null @@ -1,353 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/serial_lld.c
- * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#include "kl25z.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SD1 driver identifier.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- 38400
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] u pointer to an UART I/O block
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- UARTLP_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_RDRF) {
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- u->C2 &= ~UARTx_C2_TIE;
- } else {
- u->D = b;
- }
- }
-
- if (u->S1 & UARTx_S1_IDLE)
- u->S1 = UARTx_S1_IDLE; // Clear IDLE (S1 bits are write-1-to-clear).
-
- if (u->S1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- // FIXME: need to add set_error()
- // Clear flags (S1 bits are write-1-to-clear).
- u->S1 = UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
-}
-
-/**
- * @brief Attempts a TX preload
- */
-static void preload(SerialDriver *sdp) {
- UARTLP_TypeDef *u = sdp->uart;
-
- if (u->S1 & UARTx_S1_TDRE) {
- msg_t b = oqGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- return;
- }
- u->D = b;
- u->C2 |= UARTx_C2_TIE;
- }
-}
-
-/**
- * @brief Driver output notification.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD1);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
-}
-#endif
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(UARTLP_TypeDef *uart, const SerialConfig *config)
-{
- uint32_t uart_clock;
-
- uart->C1 = 0;
- uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
- uart->S1 = UARTx_S1_IDLE | UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- while (uart->S1 & UARTx_S1_RDRF) {
- (void)uart->D;
- }
-
-#if KINETIS_SERIAL_USE_UART0
- if (uart == UART0) {
- /* UART0 can be clocked from several sources. */
- uart_clock = KINETIS_UART0_CLOCK_FREQ;
- }
-#endif
-#if KINETIS_SERIAL_USE_UART1
- if (uart == UART1) {
- uart_clock = KINETIS_BUSCLK_FREQUENCY;
- }
-#endif
-#if KINETIS_SERIAL_USE_UART2
- if (uart == UART2) {
- uart_clock = KINETIS_BUSCLK_FREQUENCY;
- }
-#endif
-
- /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
- uint16_t divisor = (uart_clock / 16) / config->sc_speed;
- uart->C4 = UARTx_C4_OSR & (16 - 1);
- uart->BDH = (divisor >> 8) & UARTx_BDH_SBR;
- uart->BDL = (divisor & UARTx_BDL_SBR);
-
- uart->C2 = UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector70) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector74) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector78) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if KINETIS_SERIAL_USE_UART0
- /* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
- SD1.uart = UART0;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- /* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
- SD2.uart = UART1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart = UART2;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- SIM->SCGC4 |= SIM_SCGC4_UART0;
- SIM->SOPT2 =
- (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
- SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- SIM->SCGC4 |= SIM_SCGC4_UART1;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- SIM->SCGC4 |= SIM_SCGC4_UART2;
- configure_uart(sdp->uart, config);
- nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
- }
-#endif /* KINETIS_SERIAL_USE_UART2 */
-
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- /* TODO: Resets the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- nvicDisableVector(UART0_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART0;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
- nvicDisableVector(UART1_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART1;
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- nvicDisableVector(UART2_IRQn);
- SIM->SCGC4 &= ~SIM_SCGC4_UART2;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/ext_lld.c b/os/hal/ports/KINETIS/LLD/ext_lld.c index e85f032..21bb6e0 100644 --- a/os/hal/ports/KINETIS/LLD/ext_lld.c +++ b/os/hal/ports/KINETIS/LLD/ext_lld.c @@ -89,6 +89,19 @@ static void ext_lld_exti_irq_enable(void) { #if KINETIS_EXT_PORTA_WIDTH > 0
nvicEnableVector(PINA_IRQn, KINETIS_EXT_PORTA_IRQ_PRIORITY);
#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicEnableVector(PINBCDE_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicEnableVector(PINCD_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
#if KINETIS_EXT_PORTB_WIDTH > 0
nvicEnableVector(PINB_IRQn, KINETIS_EXT_PORTB_IRQ_PRIORITY);
#endif
@@ -101,6 +114,7 @@ static void ext_lld_exti_irq_enable(void) { #if KINETIS_EXT_PORTE_WIDTH > 0
nvicEnableVector(PINE_IRQn, KINETIS_EXT_PORTE_IRQ_PRIORITY);
#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
}
/**
@@ -113,6 +127,19 @@ static void ext_lld_exti_irq_disable(void) { #if KINETIS_EXT_PORTA_WIDTH > 0
nvicDisableVector(PINA_IRQn);
#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicDisableVector(PINBCDE_IRQn);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicDisableVector(PINCD_IRQn);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
#if KINETIS_EXT_PORTB_WIDTH > 0
nvicDisableVector(PINB_IRQn);
#endif
@@ -125,6 +152,7 @@ static void ext_lld_exti_irq_disable(void) { #if KINETIS_EXT_PORTE_WIDTH > 0
nvicDisableVector(PINE_IRQn);
#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
}
/*===========================================================================*/
@@ -164,6 +192,49 @@ OSAL_IRQ_HANDLER(KINETIS_PORTA_IRQ_VECTOR) { }
#endif /* KINETIS_EXT_PORTA_WIDTH > 0 */
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTB_WIDTH > 0)
+ irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
+#endif
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+#if (KINETIS_EXT_PORTE_WIDTH > 0)
+ irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
/**
* @brief PORTB interrupt handler.
*
@@ -224,6 +295,8 @@ OSAL_IRQ_HANDLER(KINETIS_PORTE_IRQ_VECTOR) { }
#endif /* KINETIS_EXT_PORTE_WIDTH > 0 */
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.c b/os/hal/ports/KINETIS/LLD/gpt_lld.c index 09d759b..6e88f88 100644 --- a/os/hal/ports/KINETIS/K20x/gpt_lld.c +++ b/os/hal/ports/KINETIS/LLD/gpt_lld.c @@ -30,11 +30,6 @@ /* Driver local definitions. */
/*===========================================================================*/
-#define KINETIS_PIT0_HANDLER VectorB8
-#define KINETIS_PIT1_HANDLER VectorBC
-#define KINETIS_PIT2_HANDLER VectorC0
-#define KINETIS_PIT3_HANDLER VectorC4
-
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -75,6 +70,10 @@ GPTDriver GPTD4; /* Driver local variables and types. */
/*===========================================================================*/
+#if KINETIS_HAS_PIT_COMMON_IRQ
+static uint8_t active_channels = 0;
+#endif /* KINETIS_HAS_PIT_COMMON_IRQ */
+
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@@ -87,7 +86,7 @@ GPTDriver GPTD4; static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
/* Clear the interrupt */
- gptp->channel->TFLG |= PIT_TCTRL_TIE;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
if (gptp->state == GPT_ONESHOT) {
gptp->state = GPT_READY; /* Back in GPT_READY state. */
@@ -100,82 +99,89 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
#if KINETIS_GPT_USE_PIT0
-#if !defined(KINETIS_PIT0_HANDLER)
-#error "KINETIS_PIT0_HANDLER not defined"
-#endif
/**
* @brief PIT1 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT0_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD1);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT0 */
#if KINETIS_GPT_USE_PIT1
-#if !defined(KINETIS_PIT1_HANDLER)
-#error "KINETIS_PIT1_HANDLER not defined"
-#endif
/**
* @brief PIT1 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT1_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD2);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT1 */
#if KINETIS_GPT_USE_PIT2
-#if !defined(KINETIS_PIT2_HANDLER)
-#error "KINETIS_PIT2_HANDLER not defined"
-#endif
/**
* @brief PIT2 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT2_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD3);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT2 */
#if KINETIS_GPT_USE_PIT3
-#if !defined(KINETIS_PIT3_HANDLER)
-#error "KINETIS_PIT3_HANDLER not defined"
-#endif
/**
* @brief PIT3 interrupt handler.
*
* @isr
*/
-OSAL_IRQ_HANDLER(KINETIS_PIT3_HANDLER) {
-
+OSAL_IRQ_HANDLER(KINETIS_PIT3_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
-
gpt_lld_serve_interrupt(&GPTD4);
-
OSAL_IRQ_EPILOGUE();
}
#endif /* KINETIS_GPT_USE_PIT3 */
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+/**
+ * @brief Common PIT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+#if KINETIS_GPT_USE_PIT0
+ if(GPTD1.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD1);
+#endif /* KINETIS_GPT_USE_PIT0 */
+#if KINETIS_GPT_USE_PIT1
+ if(GPTD2.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD2);
+#endif /* KINETIS_GPT_USE_PIT1 */
+#if KINETIS_GPT_USE_PIT2
+ if(GPTD3.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD3);
+#endif /* KINETIS_GPT_USE_PIT2 */
+#if KINETIS_GPT_USE_PIT3
+ if(GPTD4.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD4);
+#endif /* KINETIS_GPT_USE_PIT3 */
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -227,6 +233,8 @@ void gpt_lld_start(GPTDriver *gptp) { SIM->SCGC6 |= SIM_SCGC6_PIT;
gptp->clock = KINETIS_SYSCLK_FREQUENCY;
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
#if KINETIS_GPT_USE_PIT0
if (&GPTD1 == gptp) {
nvicEnableVector(PITChannel0_IRQn, KINETIS_GPT_PIT0_IRQ_PRIORITY);
@@ -248,6 +256,10 @@ void gpt_lld_start(GPTDriver *gptp) { }
#endif
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ nvicEnableVector(PIT_IRQn, KINETIS_GPT_PIT_IRQ_PRIORITY);
+ active_channels++;
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
}
/* Prescaler value calculation.*/
@@ -275,7 +287,9 @@ void gpt_lld_stop(GPTDriver *gptp) { gptp->channel->TCTRL = 0;
/* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLG_TIF;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
+
+#if !KINETIS_HAS_PIT_COMMON_IRQ
#if KINETIS_GPT_USE_PIT0
if (&GPTD1 == gptp) {
@@ -297,6 +311,11 @@ void gpt_lld_stop(GPTDriver *gptp) { nvicDisableVector(PITChannel3_IRQn);
}
#endif
+
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ if(--active_channels == 0)
+ nvicDisableVector(PIT_IRQn);
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
}
}
@@ -311,13 +330,13 @@ void gpt_lld_stop(GPTDriver *gptp) { void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
/* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLG_TIF;
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
/* Set the interval */
- gptp->channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
+ gpt_lld_change_interval(gptp, interval);
/* Start the timer */
- gptp->channel->TCTRL |= PIT_TCTRL_TIE | PIT_TCTRL_TEN;
+ gptp->channel->TCTRL |= PIT_TCTRLn_TIE | PIT_TCTRLn_TEN;
}
/**
@@ -351,16 +370,16 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { channel->TCTRL = 0;
/* Clear the interrupt flag */
- channel->TFLG |= PIT_TFLG_TIF;
+ channel->TFLG |= PIT_TFLGn_TIF;
/* Set the interval */
channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
/* Enable Timer but keep interrupts disabled */
- channel->TCTRL = PIT_TCTRL_TEN;
+ channel->TCTRL = PIT_TCTRLn_TEN;
/* Wait for the interrupt flag to be set */
- while (!(channel->TFLG & PIT_TFLG_TIF))
+ while (!(channel->TFLG & PIT_TFLGn_TIF))
;
/* Disable timer and disable interrupts */
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.h b/os/hal/ports/KINETIS/LLD/gpt_lld.h index 0e72309..5c3e233 100644 --- a/os/hal/ports/KINETIS/K20x/gpt_lld.h +++ b/os/hal/ports/KINETIS/LLD/gpt_lld.h @@ -103,6 +103,14 @@ #define KINETIS_GPT_PIT3_IRQ_PRIORITY 7
#endif
+/**
+ * @brief GPTD* common interrupt priority level setting.
+ */
+#if (KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_GPT_PIT_IRQ_PRIORITY)) \
+ || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT_IRQ_PRIORITY 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -123,31 +131,60 @@ #error "PIT3 not present in the selected device"
#endif
-#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
+#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
!KINETIS_GPT_USE_PIT2 && !KINETIS_GPT_USE_PIT3
#error "GPT driver activated but no PIT peripheral assigned"
#endif
-#if KINETIS_GPT_USE_PIT0 && \
+#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT0"
#endif
-#if KINETIS_GPT_USE_PIT1 && \
+#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT1"
#endif
-#if KINETIS_GPT_USE_PIT2 && \
+#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT2"
#endif
-#if KINETIS_GPT_USE_PIT3 && \
+#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT_COMMON_IRQ && \
!OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to PIT3"
#endif
+#if KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT"
+#endif
+
+#if KINETIS_GPT_USE_PIT0 && !defined(KINETIS_PIT0_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT0_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !defined(KINETIS_PIT1_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT1_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !defined(KINETIS_PIT2_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT2_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !defined(KINETIS_PIT3_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT3_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_PIT_IRQ_VECTOR)
+#error "KINETIS_PIT_IRQ_VECTOR not defined"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -226,7 +263,9 @@ struct GPTDriver { * @notapi
*/
#define gpt_lld_change_interval(gptp, interval) \
- ((gptp)->channel->LDVAL = (uint32_t)((interval)))
+ ((gptp)->channel->LDVAL = (uint32_t)( \
+ ( (gptp)->clock / (gptp)->config->frequency ) * \
+ ( interval ) ))
/**
* @brief Returns the interval of GPT peripheral.
@@ -237,7 +276,9 @@ struct GPTDriver { *
* @notapi
*/
-#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].LDVAL)
+#define gpt_lld_get_interval(gptp) \
+ ((uint32_t)( ( (uint64_t)(gptp)->channel->LDVAL * (gptp)->config->frequency ) / \
+ ( (uint32_t)(gptp)->clock ) ))
/**
* @brief Returns the counter value of GPT peripheral.
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.c b/os/hal/ports/KINETIS/LLD/i2c_lld.c index 4e42d16..3659a93 100644 --- a/os/hal/ports/KINETIS/LLD/i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/i2c_lld.c
+ * @file KINETIS/LLD/i2c_lld.c
* @brief KINETIS I2C subsystem low level driver source.
*
* @addtogroup I2C
@@ -191,8 +191,7 @@ OSAL_IRQ_HANDLER(KINETIS_I2C0_IRQ_VECTOR) { #if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/* FIXME: KL2x has I2C1 on Vector64; K2x don't have I2C1! */
-OSAL_IRQ_HANDLER(Vector64) {
+OSAL_IRQ_HANDLER(KINETIS_I2C1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&I2CD2);
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.h b/os/hal/ports/KINETIS/LLD/i2c_lld.h index 11de3ae..5f1ed87 100644 --- a/os/hal/ports/KINETIS/LLD/i2c_lld.h +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/i2c_lld.h
+ * @file KINETIS/LLD/i2c_lld.h
* @brief KINETIS I2C subsystem low level driver header.
*
* @addtogroup I2C
@@ -63,10 +63,38 @@ #endif
/** @} */
+/**
+ * @brief I2C0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C0_PRIORITY 12
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C1_PRIORITY 12
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/** @brief error checks */
+#if KINETIS_I2C_USE_I2C0 && !KINETIS_HAS_I2C0
+#error "I2C0 not present in the selected device"
+#endif
+
+#if KINETIS_I2C_USE_I2C1 && !KINETIS_HAS_I2C1
+#error "I2C1 not present in the selected device"
+#endif
+
+
+#if !(KINETIS_I2C_USE_I2C0 || KINETIS_I2C_USE_I2C1)
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.c b/os/hal/ports/KINETIS/LLD/pal_lld.c index 101d574..b307833 100644 --- a/os/hal/ports/KINETIS/K20x/pal_lld.c +++ b/os/hal/ports/KINETIS/LLD/pal_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file MK20D5/pal_lld.c
+ * @file KINETIS/LLD/pal_lld.c
* @brief PAL subsystem low level driver.
*
* @addtogroup PAL
@@ -108,7 +108,7 @@ void _pal_lld_setpadmode(ioportid_t port, PORT_TypeDef *portcfg = NULL;
- chDbgAssert(pad <= 31, "pal_lld_setpadmode() #1, invalid pad");
+ chDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
if (mode == PAL_MODE_OUTPUT_PUSHPULL)
port->PDDR |= ((uint32_t) 1 << pad);
@@ -134,10 +134,14 @@ void _pal_lld_setpadmode(ioportid_t port, case PAL_MODE_OUTPUT_PUSHPULL:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
break;
+#if KINETIS_GPIO_HAS_OPENDRAIN
case PAL_MODE_OUTPUT_OPENDRAIN:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
PORTx_PCRn_ODE;
break;
+#else
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+#endif
case PAL_MODE_INPUT_PULLUP:
portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
PORTx_PCRn_PE |
diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.h b/os/hal/ports/KINETIS/LLD/pal_lld.h index 242583a..2bd9872 100644 --- a/os/hal/ports/KINETIS/K20x/pal_lld.h +++ b/os/hal/ports/KINETIS/LLD/pal_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file MK20D5/pal_lld.h
+ * @file KINETIS/LLD/pal_lld.h
* @brief PAL subsystem low level driver header.
*
* @addtogroup PAL
@@ -31,13 +31,13 @@ /* Unsupported modes and specific modes */
/*===========================================================================*/
-#define PAL_MODE_ALTERNATIVE_1 10
-#define PAL_MODE_ALTERNATIVE_2 11
-#define PAL_MODE_ALTERNATIVE_3 12
-#define PAL_MODE_ALTERNATIVE_4 13
-#define PAL_MODE_ALTERNATIVE_5 14
-#define PAL_MODE_ALTERNATIVE_6 15
-#define PAL_MODE_ALTERNATIVE_7 16
+#define PAL_MODE_ALTERNATIVE_1 0x10
+#define PAL_MODE_ALTERNATIVE_2 0x11
+#define PAL_MODE_ALTERNATIVE_3 0x12
+#define PAL_MODE_ALTERNATIVE_4 0x13
+#define PAL_MODE_ALTERNATIVE_5 0x14
+#define PAL_MODE_ALTERNATIVE_6 0x15
+#define PAL_MODE_ALTERNATIVE_7 0x16
#define PIN_MUX_ALTERNATIVE(x) PORTx_PCRn_MUX(x)
@@ -151,7 +151,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_readport(port) (port)->PDIR
+#define pal_lld_readport(port) \
+ (port)->PDIR
/**
* @brief Reads the output latch.
@@ -163,7 +164,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_readlatch(port) (port)->PDOR
+#define pal_lld_readlatch(port) \
+ (port)->PDOR
/**
* @brief Writes a bits mask on a I/O port.
@@ -173,7 +175,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_writeport(port, bits) (port)->PDOR = (bits)
+#define pal_lld_writeport(port, bits) \
+ (port)->PDOR = (bits)
/**
* @brief Sets a bits mask on a I/O port.
@@ -186,7 +189,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_setport(port, bits) (port)->PSOR = (bits)
+#define pal_lld_setport(port, bits) \
+ (port)->PSOR = (bits)
/**
* @brief Clears a bits mask on a I/O port.
@@ -199,7 +203,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_clearport(port, bits) (port)->PCOR = (bits)
+#define pal_lld_clearport(port, bits) \
+ (port)->PCOR = (bits)
/**
* @brief Toggles a bits mask on a I/O port.
@@ -212,7 +217,8 @@ typedef struct { *
* @notapi
*/
-#define pal_lld_toggleport(port, bits) (port)->PTOR = (bits)
+#define pal_lld_toggleport(port, bits) \
+ (port)->PTOR = (bits)
/**
* @brief Reads a group of bits.
@@ -364,6 +370,11 @@ extern "C" { void _pal_lld_setpadmode(ioportid_t port,
uint8_t pad,
iomode_t mode);
+ uint8_t _pal_lld_readpad(ioportid_t port,
+ uint8_t pad);
+ void _pal_lld_writepad(ioportid_t port,
+ uint8_t pad,
+ uint8_t bit);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/KINETIS/LLD/serial_lld.c b/os/hal/ports/KINETIS/LLD/serial_lld.c new file mode 100644 index 0000000..c80cf22 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/serial_lld.c @@ -0,0 +1,583 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.c
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] isr UART s1 register value
+ */
+static void set_error(SerialDriver *sdp, uint8_t s1) {
+ eventflags_t sts = 0;
+
+ if (s1 & UARTx_S1_OR)
+ sts |= SD_OVERRUN_ERROR;
+ if (s1 & UARTx_S1_PF)
+ sts |= SD_PARITY_ERROR;
+ if (s1 & UARTx_S1_FE)
+ sts |= SD_FRAMING_ERROR;
+ if (s1 & UARTx_S1_NF)
+ sts |= SD_NOISE_ERROR;
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common error IRQ handler.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_error_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
+ /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ * then reading D.*/
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1) {
+ if(s1 & UARTx_S1_IDLE) {
+ *(u->s1_p) |= UARTx_S1_IDLE;
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ }
+ return;
+ }
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
+ }
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ if (s1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&sdp->iqueue, *(u->d_p)) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (s1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ *(u->c2_p) &= ~UARTx_C2_TIE;
+ } else {
+ *(u->d_p) = b;
+ }
+ }
+
+ serve_error_interrupt(sdp);
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+
+ if (*(u->s1_p) & UARTx_S1_TDRE) {
+ msg_t b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ *(u->d_p) = b;
+ *(u->c2_p) |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
+
+ UART_w_TypeDef *uart = &(sdp->uart);
+ uint32_t divisor;
+
+ /* Discard any incoming data. */
+ while (*(uart->s1_p) & UARTx_S1_RDRF) {
+ (void)*(uart->d_p);
+ }
+
+ /* Disable UART while configuring */
+ *(uart->c2_p) &= ~(UARTx_C2_RE | UARTx_C2_TE);
+
+ /* The clock sources for various UARTs can be different. */
+ divisor=KINETIS_BUSCLK_FREQUENCY;
+
+#if defined(KL2x)
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ /* UART0 can be clocked from several sources on KL2x. */
+ divisor = KINETIS_UART0_CLOCK_FREQ;
+ /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
+ /* Note: OSR only works on KL2x/UART0; further UARTs have fixed 16. */
+ *(uart->c4_p) = UARTx_C4_OSR(16 - 1);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#elif defined(K20x) /* KL2x */
+
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+#if KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART0 */
+#if KINETIS_SERIAL_USE_UART1
+ if(sdp == &SD2)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#else /* K20x */
+#error Baud rate selection not implemented for this MCU type
+#endif /* K20x */
+
+ divisor = (divisor * 2 + 1) / config->sc_speed;
+
+ *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
+ *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
+#if defined(K20x)
+ *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
+#endif /* K20x */
+
+ /* Line settings. */
+ *(uart->c1_p) = 0;
+ /* Enable error event interrupts (overrun, noise, framing, parity) */
+ *(uart->c3_p) = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+ /* Enable the peripheral; including receive interrupts. */
+ *(uart->c2_p) |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+#if ! KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.bdh_p = &(UART0->BDH);
+ SD1.uart.bdl_p = &(UART0->BDL);
+ SD1.uart.c1_p = &(UART0->C1);
+ SD1.uart.c2_p = &(UART0->C2);
+ SD1.uart.c3_p = &(UART0->C3);
+ SD1.uart.c4_p = &(UART0->C4);
+ SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
+ SD1.uart.s2_p = &(UART0->S2);
+ SD1.uart.d_p = &(UART0->D);
+#else /* ! KINETIS_SERIAL0_IS_LPUART */
+ /* little endian! */
+ SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD1.uart.c2_p = ((uint8_t *)&(LPUART0->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD1.uart.c3_p = ((uint8_t *)&(LPUART0->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD1.uart.c4_p = ((uint8_t *)&(LPUART0->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD1.uart.s1_p = ((uint8_t *)&(LPUART0->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD1.uart.s2_p = ((uint8_t *)&(LPUART0->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD1.uart.d_p = ((uint8_t *)&(LPUART0->DATA)) + 0; /* D: DATA, byte 4 */
+#endif /* ! KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SD1.uart.uartlp_p = UART0;
+ SD1.uart.uart_p = NULL;
+#elif KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.lpuart_p = LPUART0;
+ SD1.uart.uart_p = NULL;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SD1.uart.uart_p = UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+#if ! KINETIS_SERIAL1_IS_LPUART
+ SD2.uart.bdh_p = &(UART1->BDH);
+ SD2.uart.bdl_p = &(UART1->BDL);
+ SD2.uart.c1_p = &(UART1->C1);
+ SD2.uart.c2_p = &(UART1->C2);
+ SD2.uart.c3_p = &(UART1->C3);
+ SD2.uart.c4_p = &(UART1->C4);
+ SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
+ SD2.uart.s2_p = &(UART1->S2);
+ SD2.uart.d_p = &(UART1->D);
+ SD2.uart.uart_p = UART1;
+#else /* ! KINETIS_SERIAL1_IS_LPUART */
+ /* little endian! */
+ SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD2.uart.c2_p = ((uint8_t *)&(LPUART1->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD2.uart.c3_p = ((uint8_t *)&(LPUART1->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD2.uart.c4_p = ((uint8_t *)&(LPUART1->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD2.uart.s1_p = ((uint8_t *)&(LPUART1->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD2.uart.s2_p = ((uint8_t *)&(LPUART1->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD2.uart.d_p = ((uint8_t *)&(LPUART1->DATA)) + 0; /* D: DATA, byte 4 */
+ SD2.uart.lpuart_p = LPUART1;
+ SD2.uart.uart_p = NULL;
+#endif /* ! KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart.bdh_p = &(UART2->BDH);
+ SD3.uart.bdl_p = &(UART2->BDL);
+ SD3.uart.c1_p = &(UART2->C1);
+ SD3.uart.c2_p = &(UART2->C2);
+ SD3.uart.c3_p = &(UART2->C3);
+ SD3.uart.c4_p = &(UART2->C4);
+ SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
+ SD3.uart.s2_p = &(UART2->S2);
+ SD3.uart.d_p = &(UART2->D);
+ SD3.uart.uart_p = UART2;
+#endif /* KINETIS_SERIAL_USE_UART2 */
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART0;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) |
+ SIM_SOPT2_LPUART0SRC(KINETIS_UART0_CLOCK_SRC);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
+ SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
+#endif /* KINETIS_SERIAL0_IS_UARTLP */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ nvicEnableVector(UART0Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicEnableVector(LPUART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART1;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) |
+ SIM_SOPT2_LPUART1SRC(KINETIS_UART1_CLOCK_SRC);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ nvicEnableVector(UART1Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicEnableVector(LPUART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ nvicEnableVector(UART2Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART0Status_IRQn);
+ nvicDisableVector(UART0Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicDisableVector(LPUART0_IRQn);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicDisableVector(UART0_IRQn);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART0;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART1Status_IRQn);
+ nvicDisableVector(UART1Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicDisableVector(LPUART1_IRQn);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicDisableVector(UART1_IRQn);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART1;
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART2Status_IRQn);
+ nvicDisableVector(UART2Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicDisableVector(UART2_IRQn);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.h b/os/hal/ports/KINETIS/LLD/serial_lld.h index 2d003b0..cc66eb3 100644 --- a/os/hal/ports/KINETIS/KL2x/serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/serial_lld.h @@ -82,12 +82,44 @@ #define KINETIS_SERIAL_UART2_PRIORITY 12
#endif
+/**
+ * @brief UART0 clock source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1 /* MCGFLLCLK clock, or MCGPLLCLK/2; or IRC48M */
+#endif
+
+/**
+ * @brief UART1 clock source.
+ */
+#if !defined(KINETIS_UART1_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART1_CLOCK_SRC 1 /* IRC48M */
+#endif
+
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+/** @brief error checks */
+#if KINETIS_SERIAL_USE_UART0 && !KINETIS_HAS_SERIAL0
+#error "UART0 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !KINETIS_HAS_SERIAL1
+#error "UART1 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !KINETIS_HAS_SERIAL2
+#error "UART2 not present in the selected device"
+#endif
+
+#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
+ KINETIS_SERIAL_USE_UART2)
+#error "Serial driver activated but no UART peripheral assigned"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -108,6 +140,31 @@ typedef struct { } SerialConfig;
/**
+ * @brief Generic UART register structure.
+ * @note Individual UART register blocks (even within the same chip) can differ.
+ */
+
+typedef struct {
+ volatile uint8_t* bdh_p;
+ volatile uint8_t* bdl_p;
+ volatile uint8_t* c1_p;
+ volatile uint8_t* c2_p;
+ volatile uint8_t* c3_p;
+ volatile uint8_t* c4_p;
+ volatile uint8_t* s1_p;
+ volatile uint8_t* s2_p;
+ volatile uint8_t* d_p;
+ UART_TypeDef *uart_p;
+#if KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP
+ UARTLP_TypeDef *uartlp_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP */
+#if (KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART) \
+ || (KINETIS_SERIAL_USE_UART1 && KINETIS_SERIAL1_IS_LPUART)
+ LPUART_TypeDef *lpuart_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART */
+} UART_w_TypeDef;
+
+/**
* @brief @p SerialDriver specific data.
*/
#define _serial_driver_data \
@@ -124,7 +181,7 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the UART registers block.*/ \
- UARTLP_TypeDef *uart;
+ UART_w_TypeDef uart;
/*===========================================================================*/
/* Driver macros. */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.c b/os/hal/ports/KINETIS/LLD/st_lld.c index 1f8cb63..e6ed9e5 100644 --- a/os/hal/ports/KINETIS/KL2x/st_lld.c +++ b/os/hal/ports/KINETIS/LLD/st_lld.c @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/KL2x/st_lld.c
+ * @file KINETIS/LLD/st_lld.c
* @brief ST Driver subsystem low level driver code.
*
* @addtogroup ST
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.h b/os/hal/ports/KINETIS/LLD/st_lld.h index 24044e5..c67a5d0 100644 --- a/os/hal/ports/KINETIS/KL2x/st_lld.h +++ b/os/hal/ports/KINETIS/LLD/st_lld.h @@ -15,7 +15,7 @@ */
/**
- * @file KINETIS/st_lld.h
+ * @file KINETIS/LLD/st_lld.h
* @brief ST Driver subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
diff --git a/os/hal/ports/KINETIS/LLD/usb_lld.c b/os/hal/ports/KINETIS/LLD/usb_lld.c new file mode 100644 index 0000000..159aef9 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/usb_lld.c @@ -0,0 +1,832 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.c
+ * @brief KINETIS USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USB0 driver identifier.*/
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief IN EP0 state.
+ */
+USBInEndpointState ep0in;
+
+/**
+ * @brief OUT EP0 state.
+ */
+USBOutEndpointState ep0out;
+
+/**
+ * @brief Buffer for the EP0 setup packets.
+ */
+static uint8_t ep0setup_buffer[8];
+
+/**
+ * @brief EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+ USB_EP_MODE_TYPE_CTRL,
+ _usb_ep0setup,
+ _usb_ep0in,
+ _usb_ep0out,
+ 64,
+ 64,
+ &ep0in,
+ &ep0out,
+ 1,
+ ep0setup_buffer
+};
+
+/*
+ * Buffer Descriptor Table (BDT)
+ */
+
+/*
+ * Buffer Descriptor (BD)
+ * */
+typedef struct {
+ uint32_t desc;
+ uint8_t* addr;
+} bd_t;
+
+/*
+ * Buffer Descriptor fields - p.889
+ */
+#define BDT_OWN 0x80
+#define BDT_DATA 0x40
+#define BDT_KEEP 0x20
+#define BDT_NINC 0x10
+#define BDT_DTS 0x08
+#define BDT_STALL 0x04
+
+#define BDT_DESC(bc, data) (BDT_OWN | BDT_DTS | ((data&0x1)<<6) | ((bc) << 16))
+
+/*
+ * BDT PID - p.891
+ */
+#define BDT_PID_OUT 0x01
+#define BDT_PID_IN 0x09
+#define BDT_PID_SETUP 0x0D
+#define BDT_TOK_PID(n) (((n)>>2)&0xF)
+
+/*
+ * BDT index fields
+ */
+#define DATA0 0
+#define DATA1 1
+
+#define RX 0
+#define TX 1
+
+#define EVEN 0
+#define ODD 1
+
+#define BDT_INDEX(endpoint, tx, odd) (((endpoint)<<2) | ((tx)<<1) | (odd))
+/*
+ * Get RX-ed/TX-ed bytes count from BDT entry
+ */
+#define BDT_BC(n) (((n)>>16)&0x3FF)
+
+/* The USB-FS needs 2 BDT entry per endpoint direction
+ * that adds to: 2*2*16 BDT entries for 16 bi-directional EP
+ */
+static volatile bd_t _bdt[(KINETIS_USB_ENDPOINTS)*2*2] __attribute__((aligned(512)));
+
+/* FIXME later with dyn alloc
+ * 16 EP
+ * 2 directions per EP
+ * 2 buffer per direction
+ * => 64 buffers
+ */
+static uint8_t _usbb[KINETIS_USB_ENDPOINTS*4][64] __attribute__((aligned(4)));
+static volatile uint8_t _usbbn=0;
+uint8_t* usb_alloc(uint8_t size)
+{
+ (void)size;
+ if(_usbbn < (KINETIS_USB_ENDPOINTS)*4)
+ return _usbb[_usbbn++];
+ while(1); /* Should not happen, ever */
+}
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/* Called from locked ISR. */
+void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBInEndpointState *isp = epc->in_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
+
+ if (n > (size_t)epc->in_maxsize)
+ n = (size_t)epc->in_maxsize;
+
+ /* Copy from buf to _usbb[] */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ bd->addr[i] = isp->txbuf[i];
+
+ /* Update the Buffer status */
+ bd->desc = BDT_DESC(n, isp->data_bank);
+ /* Toggle the odd and data bits for next TX */
+ isp->data_bank ^= DATA1;
+ isp->odd_even ^= ODD;
+}
+
+/* Called from locked ISR. */
+void usb_packet_receive(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBOutEndpointState *osp = epc->out_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, RX, osp->odd_even)];
+
+ if (n > (size_t)epc->out_maxsize)
+ n = (size_t)epc->out_maxsize;
+
+ /* Copy from _usbb[] to buf */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ osp->rxbuf[i] = bd->addr[i];
+
+ /* Update the Buffer status
+ * Set current buffer to same DATA bank and then toggle.
+ * Since even/odd buffers are ping-pong and setup re-initialized them
+ * this should work correctly */
+ bd->desc = BDT_DESC(epc->out_maxsize, osp->data_bank);
+ osp->data_bank ^= DATA1;
+ usb_lld_start_out(usbp, ep);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*============================================================================*/
+
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+/**
+ * @brief USB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
+ USBDriver *usbp = &USBD1;
+ uint8_t istat = USB0->ISTAT;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* 04 - Bit2 - Start Of Frame token received */
+ if(istat & USBx_ISTAT_SOFTOK) {
+ _usb_isr_invoke_sof_cb(usbp);
+ USB0->ISTAT = USBx_ISTAT_SOFTOK;
+ }
+
+ /* 08 - Bit3 - Token processing completed */
+ while(istat & USBx_ISTAT_TOKDNE) {
+ uint8_t stat = USB0->STAT;
+ uint8_t ep = stat >> 4;
+ if(ep > KINETIS_USB_ENDPOINTS) {
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+ const USBEndpointConfig *epc = usbp->epc[ep];
+
+ /* Get the correct BDT entry */
+ uint8_t odd_even = (stat & USBx_STAT_ODD_MASK) >> USBx_STAT_ODD_SHIFT;
+ uint8_t tx_rx = (stat & USBx_STAT_TX_MASK) >> USBx_STAT_TX_SHIFT;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep,tx_rx,odd_even)];
+
+ /* Update the ODD/EVEN state for RX */
+ if(tx_rx == RX && epc->out_state != NULL)
+ epc->out_state->odd_even = odd_even;
+
+ switch(BDT_TOK_PID(bd->desc))
+ {
+ case BDT_PID_SETUP: // SETUP
+ {
+ /* Clear any pending IN stuff */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ /* Also in the chibios state machine */
+ (usbp)->receiving &= ~1;
+ /* After a SETUP, IN is always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
+
+ /* Call SETUP function (ChibiOS core), which sends back stuff */
+ _usb_isr_invoke_setup_cb(usbp, ep);
+ /* Buffer is released by the above callback. */
+ /* from Paul: "unfreeze the USB, now that we're ready" */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+ } break;
+ case BDT_PID_IN: // IN
+ {
+ if(epc->in_state == NULL)
+ break;
+ /* Special case for SetAddress for EP0 */
+ if(ep == 0 && (((uint16_t)usbp->setup[0]<<8)|usbp->setup[1]) == 0x0500)
+ {
+ usbp->address = usbp->setup[2];
+ usb_lld_set_address(usbp);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
+ usbp->state = USB_SELECTED;
+ }
+ uint16_t txed = BDT_BC(bd->desc);
+ epc->in_state->txcnt += txed;
+ if(epc->in_state->txcnt < epc->in_state->txsize)
+ {
+ epc->in_state->txbuf += txed;
+ osalSysLockFromISR();
+ usb_packet_transmit(usbp,ep,epc->in_state->txsize - epc->in_state->txcnt);
+ osalSysUnlockFromISR();
+ }
+ else
+ {
+ if(epc->in_cb != NULL)
+ _usb_isr_invoke_in_cb(usbp,ep);
+ }
+ } break;
+ case BDT_PID_OUT: // OUT
+ {
+ if(epc->out_state == NULL)
+ break;
+ uint16_t rxed = BDT_BC(bd->desc);
+
+ osalSysLockFromISR();
+ usb_packet_receive(usbp,ep,rxed);
+ osalSysUnlockFromISR();
+ if(rxed)
+ {
+ epc->out_state->rxbuf += rxed;
+
+ /* Update transaction data */
+ epc->out_state->rxcnt += rxed;
+ epc->out_state->rxsize -= rxed;
+ epc->out_state->rxpkts -= 1;
+
+ /* The transaction is completed if the specified number of packets
+ has been received or the current packet is a short packet.*/
+ if ((rxed < epc->out_maxsize) || (epc->out_state->rxpkts == 0))
+ {
+ if(epc->out_cb != NULL)
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+ }
+ } break;
+ default:
+ break;
+ }
+ USB0->ISTAT = USBx_ISTAT_TOKDNE;
+ istat = USB0->ISTAT;
+ }
+
+ /* 01 - Bit0 - Valid USB Reset received */
+ if(istat & USBx_ISTAT_USBRST) {
+ _usb_reset(usbp);
+ USB0->ISTAT = USBx_ISTAT_USBRST;
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+
+ /* 80 - Bit7 - STALL handshake received */
+ if(istat & USBx_ISTAT_STALL) {
+ USB0->ISTAT = USBx_ISTAT_STALL;
+ }
+
+ /* 02 - Bit1 - ERRSTAT condition triggered */
+ if(istat & USBx_ISTAT_ERROR) {
+ uint8_t err = USB0->ERRSTAT;
+ USB0->ERRSTAT = err;
+ USB0->ISTAT = USBx_ISTAT_ERROR;
+ }
+
+ /* 10 - Bit4 - Constant IDLE on USB bus detected */
+ if(istat & USBx_ISTAT_SLEEP) {
+ /* This seems to fire a few times before the device is
+ * configured - need to ignore those occurences somehow. */
+ /* The other option would be to only activate INTEN_SLEEPEN
+ * on CONFIGURED event, but that would need to be done in
+ * user firmware. */
+ if(usbp->state == USB_ACTIVE) {
+ _usb_suspend(usbp);
+ /* Enable interrupt on resume */
+ USB0->INTEN |= USBx_INTEN_RESUMEEN;
+ }
+
+ // low-power version (check!):
+ // enable wakeup interrupt on resume USB signaling
+ // (check that it was a wakeup int with USBx_USBTRC0_USB_RESUME_INT)
+ //? USB0->USBTRC0 |= USBx_USBTRC0_USBRESMEN
+ // suspend the USB module
+ //? USB0->USBCTRL |= USBx_USBCTRL_SUSP;
+
+ USB0->ISTAT = USBx_ISTAT_SLEEP;
+ }
+
+ /* 20 - Bit5 - Resume - Only allowed in sleep=suspend mode */
+ if(istat & USBx_ISTAT_RESUME) {
+ /* Disable interrupt on resume (should be disabled
+ * during normal operation according to datasheet). */
+ USB0->INTEN &= ~USBx_INTEN_RESUMEEN;
+
+ // low power version (check!):
+ // desuspend the USB module
+ //? USB0->USBCTRL &= ~USBx_USBCTRL_SUSP;
+ // maybe also
+ //? USB0->CTL = USBx_CTL_USBENSOFEN;
+ _usb_wakeup(usbp);
+ USB0->ISTAT = USBx_ISTAT_RESUME;
+ }
+
+ /* 40 - Bit6 - ATTACH - used */
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_USB_USE_USB0 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+ /* Driver initialization.*/
+ usbObjectInit(&USBD1);
+
+#if KINETIS_USB_USE_USB0
+
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC;
+
+#if defined(K20x5) || defined(K20x7)
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+
+ /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ #define KINETIS_USBCLK_FREQUENCY 48000000UL
+ uint32_t i,j;
+ for(i=0; i < 2; i++) {
+ for(j=0; j < 8; j++) {
+ if((KINETIS_PLLCLK_FREQUENCY * (i+1)) == (KINETIS_USBCLK_FREQUENCY*(j+1))) {
+ SIM->CLKDIV2 = i | SIM_CLKDIV2_USBDIV(j);
+ goto usbfrac_match_found;
+ }
+ }
+ }
+ usbfrac_match_found:
+ chDbgAssert(i<2 && j <8,"USB Init error");
+
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error USB clock setting not implemented for this KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#elif defined(KL25) || defined (KL26) || defined(KL27)
+
+ /* No extra clock dividers for USB clock */
+
+#else /* defined(KL25) || defined (KL26) || defined(KL27) */
+#error USB driver not implemented for your MCU type
+#endif
+
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Configures and activates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+ /* Clear BDT */
+ uint8_t i;
+ for(i=0;i<KINETIS_USB_ENDPOINTS;i++) {
+ _bdt[i].desc=0;
+ _bdt[i].addr=0;
+ }
+
+ /* Enable Clock */
+#if KINETIS_USB0_IS_USBOTG
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG;
+#else /* KINETIS_USB0_IS_USBOTG */
+ SIM->SCGC4 |= SIM_SCGC4_USBFS;
+#endif /* KINETIS_USB0_IS_USBOTG */
+
+#if KINETIS_HAS_USB_CLOCK_RECOVERY
+ USB0->CLK_RECOVER_IRC_EN |= USBx_CLK_RECOVER_IRC_EN_IRC_EN;
+ USB0->CLK_RECOVER_CTRL |= USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN;
+#endif /* KINETIS_HAS_USB_CLOCK_RECOVERY */
+
+ /* Reset USB module, wait for completion */
+ USB0->USBTRC0 |= USBx_USBTRC0_USBRESET;
+ while ((USB0->USBTRC0 & USBx_USBTRC0_USBRESET));
+
+ /* Set BDT Address */
+ USB0->BDTPAGE1 = ((uint32_t)_bdt) >> 8;
+ USB0->BDTPAGE2 = ((uint32_t)_bdt) >> 16;
+ USB0->BDTPAGE3 = ((uint32_t)_bdt) >> 24;
+
+ /* Clear all ISR flags */
+ USB0->ISTAT = 0xFF;
+ USB0->ERRSTAT = 0xFF;
+#if KINETIS_USB0_IS_USBOTG
+ USB0->OTGISTAT = 0xFF;
+#endif /* KINETIS_USB0_IS_USBOTG */
+ USB0->USBTRC0 |= 0x40; //a hint was given that this is an undocumented interrupt bit
+
+ /* Enable USB */
+ USB0->CTL = USBx_CTL_ODDRST | USBx_CTL_USBENSOFEN;
+ USB0->USBCTRL = 0;
+
+ /* Enable reset interrupt */
+ USB0->INTEN |= USBx_INTEN_USBRSTEN;
+
+ /* Enable interrupt in NVIC */
+#if KINETIS_USB0_IS_USBOTG
+ nvicEnableVector(USB_OTG_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicEnableVector(USB_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief Deactivates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+ /* TODO: If in ready state then disables the USB clock.*/
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+#if KINETIS_USB0_IS_USBOTG
+ nvicDisableVector(USB_OTG_IRQn);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicDisableVector(USB_IRQn);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief USB low level reset routine.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+ // FIXME, dyn alloc
+ _usbbn = 0;
+
+#if KINETIS_USB_USE_USB0
+
+ /* Reset BDT ODD/EVEN bits */
+ USB0->CTL = USBx_CTL_ODDRST;
+
+ /* EP0 initialization.*/
+ usbp->epc[0] = &ep0config;
+ usb_lld_init_endpoint(usbp, 0);
+
+ /* Clear all pending interrupts */
+ USB0->ERRSTAT = 0xFF;
+ USB0->ISTAT = 0xFF;
+
+ /* Set the address to zero during enumeration */
+ usbp->address = 0;
+ USB0->ADDR = 0;
+
+ /* Enable other interrupts */
+ USB0->ERREN = 0xFF;
+ USB0->INTEN = USBx_INTEN_TOKDNEEN |
+ USBx_INTEN_SOFTOKEN |
+ USBx_INTEN_STALLEN |
+ USBx_INTEN_ERROREN |
+ USBx_INTEN_USBRSTEN |
+ USBx_INTEN_SLEEPEN;
+
+ /* "is this necessary?", Paul from PJRC */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Sets the USB address.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+
+#if KINETIS_USB_USE_USB0
+ USB0->ADDR = usbp->address&0x7F;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Enables an endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+
+ if(ep > KINETIS_USB_ENDPOINTS)
+ return;
+
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ uint8_t mask=0;
+
+ if(epc->out_state != NULL)
+ {
+ /* OUT Endpoint */
+ epc->out_state->odd_even = EVEN;
+ epc->out_state->data_bank = DATA0;
+ /* RXe */
+ _bdt[BDT_INDEX(ep, RX, EVEN)].desc = BDT_DESC(epc->out_maxsize, DATA0);
+ _bdt[BDT_INDEX(ep, RX, EVEN)].addr = usb_alloc(epc->out_maxsize);
+ /* RXo */
+ _bdt[BDT_INDEX(ep, RX, ODD)].desc = BDT_DESC(epc->out_maxsize, DATA1);
+ _bdt[BDT_INDEX(ep, RX, ODD)].addr = usb_alloc(epc->out_maxsize);
+ /* Enable OUT direction */
+ mask |= USBx_ENDPTn_EPRXEN;
+ }
+ if(epc->in_state != NULL)
+ {
+ /* IN Endpoint */
+ epc->in_state->odd_even = EVEN;
+ epc->in_state->data_bank = DATA0;
+ /* TXe, not used yet */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, EVEN)].addr = usb_alloc(epc->in_maxsize);
+ /* TXo, not used yet */
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].addr = usb_alloc(epc->in_maxsize);
+ /* Enable IN direction */
+ mask |= USBx_ENDPTn_EPTXEN;
+ }
+
+ /* EPHSHK should be set for CTRL, BULK, INTR not for ISOC*/
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_ISOC)
+ mask |= USBx_ENDPTn_EPHSHK;
+ /* Endpoint is not a CTRL endpoint, disable SETUP transfers */
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL)
+ mask |= USBx_ENDPTn_EPCTLDIS;
+
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V = mask;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+ (void)usbp;
+ uint8_t i;
+#if KINETIS_USB_USE_USB0
+ for(i=1;i<KINETIS_USB_ENDPOINTS;i++)
+ USB0->ENDPT[i].V = 0;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPRXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+#if KINETIS_USB_USE_USB0
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPTXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ * callback in order to read the received setup packet.
+ * @pre In order to use this function the endpoint must have been
+ * initialized as a control endpoint.
+ * @post The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+ /* Get the BDT entry */
+ USBOutEndpointState *os = usbp->epc[ep]->out_state;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even)];
+ /* Copy the 8 bytes of data */
+ uint8_t n;
+ for (n = 0; n < 8; n++) {
+ buf[n] = bd->addr[n];
+ }
+ /* Release the buffer
+ * Setup packet is always DATA0
+ * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ os->data_bank = DATA1;
+}
+
+/**
+ * @brief Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+ USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+ /* Transfer initialization.*/
+ if (osp->rxsize == 0) /* Special case for zero sized packets.*/
+ osp->rxpkts = 1;
+ else
+ osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
+ usbp->epc[ep]->out_maxsize);
+}
+
+/**
+ * @brief Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @note Called from ISR and locked zone.
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ (void)ep;
+ usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
+}
+
+/**
+ * @brief Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/usb_lld.h b/os/hal/ports/KINETIS/LLD/usb_lld.h new file mode 100644 index 0000000..978e8a6 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/usb_lld.h @@ -0,0 +1,428 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.h
+ * @brief KINETIS USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _USB_LLD_H_
+#define _USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum endpoint address.
+ */
+#define USB_MAX_ENDPOINTS 15
+
+/**
+ * @brief Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
+
+/**
+ * @brief Address ack handling
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
+
+/**
+ * @brief This device requires the address change after the status packet.
+ */
+#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief USB1 driver enable switch.
+ * @details If set to @p TRUE the support for USB1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_USB_USE_USB0) || defined(__DOXYGEN__)
+#define KINETIS_USB_USE_USB0 FALSE
+#endif
+
+/**
+ * @brief USB1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_USB_USB0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_USB_USB0_IRQ_PRIORITY 5
+#endif
+
+#if !defined(KINETIS_USB_ENDPOINTS) || defined(__DOXYGEN__)
+ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !KINETIS_HAS_USB
+#error "USB not present in the selected device"
+#endif
+
+#if !KINETIS_USB_USE_USB0
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if KINETIS_USB_USE_USB0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_USB_USB0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_USB_USB0_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_USB_IRQ_VECTOR)
+#error "KINETIS_USB_IRQ_VECTOR not defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an IN endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested transmit transfer size.
+ */
+ size_t txsize;
+ /**
+ * @brief Transmitted bytes so far.
+ */
+ size_t txcnt;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBInEndpointState;
+
+/**
+ * @brief Type of an OUT endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested receive transfer size.
+ */
+ size_t rxsize;
+ /**
+ * @brief Received bytes so far.
+ */
+ size_t rxcnt;
+ /**
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Number of packets to receive.
+ */
+ uint16_t rxpkts;
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBOutEndpointState;
+
+/**
+ * @brief Type of an USB endpoint configuration structure.
+ * @note Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+ /**
+ * @brief Type and mode of the endpoint.
+ */
+ uint32_t ep_mode;
+ /**
+ * @brief Setup packet notification callback.
+ * @details This callback is invoked when a setup packet has been
+ * received.
+ * @post The application must immediately call @p usbReadPacket() in
+ * order to access the received packet.
+ * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+ * endpoints, it should be set to @p NULL for other endpoint
+ * types.
+ */
+ usbepcallback_t setup_cb;
+ /**
+ * @brief IN endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t in_cb;
+ /**
+ * @brief OUT endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t out_cb;
+ /**
+ * @brief IN endpoint maximum packet size.
+ * @details This field must be set to zero if the IN endpoint is not used.
+ */
+ uint16_t in_maxsize;
+ /**
+ * @brief OUT endpoint maximum packet size.
+ * @details This field must be set to zero if the OUT endpoint is not used.
+ */
+ uint16_t out_maxsize;
+ /**
+ * @brief @p USBEndpointState associated to the IN endpoint.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
+ */
+ USBInEndpointState *in_state;
+ /**
+ * @brief @p USBEndpointState associated to the OUT endpoint.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
+ */
+ USBOutEndpointState *out_state;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Reserved field, not currently used.
+ * @note Initialize this field to 1 in order to be forward compatible.
+ */
+ uint16_t ep_buffers;
+ /**
+ * @brief Pointer to a buffer for setup packets.
+ * @details Setup packets require a dedicated 8-bytes buffer, set this
+ * field to @p NULL for non-control endpoints.
+ */
+ uint8_t *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief Type of an USB driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief USB events callback.
+ * @details This callback is invoked when an USB driver event is registered.
+ */
+ usbeventcb_t event_cb;
+ /**
+ * @brief Device GET_DESCRIPTOR request callback.
+ * @note This callback is mandatory and cannot be set to @p NULL.
+ */
+ usbgetdescriptor_t get_descriptor_cb;
+ /**
+ * @brief Requests hook callback.
+ * @details This hook allows to be notified of standard requests or to
+ * handle non standard requests.
+ */
+ usbreqhandler_t requests_hook_cb;
+ /**
+ * @brief Start Of Frame callback.
+ */
+ usbcallback_t sof_cb;
+ /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief Structure representing an USB driver.
+ */
+struct USBDriver {
+ /**
+ * @brief Driver state.
+ */
+ usbstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const USBConfig *config;
+ /**
+ * @brief Bit map of the transmitting IN endpoints.
+ */
+ uint16_t transmitting;
+ /**
+ * @brief Bit map of the receiving OUT endpoints.
+ */
+ uint16_t receiving;
+ /**
+ * @brief Active endpoints configurations.
+ */
+ const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an IN endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *in_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an OUT endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *out_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Endpoint 0 state.
+ */
+ usbep0state_t ep0state;
+ /**
+ * @brief Next position in the buffer to be transferred through endpoint 0.
+ */
+ uint8_t *ep0next;
+ /**
+ * @brief Number of bytes yet to be transferred through endpoint 0.
+ */
+ size_t ep0n;
+ /**
+ * @brief Endpoint 0 end transaction callback.
+ */
+ usbcallback_t ep0endcb;
+ /**
+ * @brief Setup packet buffer.
+ */
+ uint8_t setup[8];
+ /**
+ * @brief Current USB device status.
+ */
+ uint16_t status;
+ /**
+ * @brief Assigned USB address.
+ */
+ uint8_t address;
+ /**
+ * @brief Current USB device configuration.
+ */
+ uint8_t configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+ USB_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the next address in the packet memory.
+ */
+ uint32_t pmnext;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current frame number.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The current frame number.
+ *
+ * @notapi
+ */
+#define usb_lld_get_frame_number(usbp) ((USB0->FRMNUMH<<8)|USB0->FRMNUML)
+
+/**
+ * @brief Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ * @p usbStartReceiveI() because the last packet could have a size
+ * different from the expected one.
+ * @pre The OUT endpoint must have been configured in transaction mode
+ * in order to use this function.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep) \
+ ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief Connects the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_connect_bus)
+#define usb_lld_connect_bus(usbp) (USB0->CONTROL |= USBx_CONTROL_DPPULLUPNONOTG)
+#endif
+
+/**
+ * @brief Disconnect the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_disconnect_bus)
+/* Writing to USB0->CONTROL causes an unhandled exception when USB module is not clocked. */
+#if KINETIS_USB0_IS_USBOTG
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBOTG) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#else /* KINETIS_USB0_IS_USBOTG */
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBFS) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#endif /* KINETIS_USB0_IS_USBOTG */
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void usb_lld_init(void);
+ void usb_lld_start(USBDriver *usbp);
+ void usb_lld_stop(USBDriver *usbp);
+ void usb_lld_reset(USBDriver *usbp);
+ void usb_lld_set_address(USBDriver *usbp);
+ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+ void usb_lld_disable_endpoints(USBDriver *usbp);
+ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+ void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* _USB_LLD_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-K20D50M/I2C/Makefile b/testhal/KINETIS/FRDM-K20D50M/I2C/Makefile new file mode 100644 index 0000000..3ee409d --- /dev/null +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/Makefile @@ -0,0 +1,216 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -DCRT0_INIT_STACKS=0
+# USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/ADC/chconf.h b/testhal/KINETIS/FRDM-K20D50M/I2C/chconf.h index b7a340d..eecc0a6 100644 --- a/testhal/KINETIS/ADC/chconf.h +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/chconf.h @@ -27,6 +27,8 @@ #ifndef _CHCONF_H_
#define _CHCONF_H_
+ +#define _CHIBIOS_RT_CONF_ /*===========================================================================*/
/**
@@ -263,14 +265,6 @@ #define CH_CFG_USE_MAILBOXES TRUE
/**
- * @brief I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note The default is @p TRUE.
- */
-#define CH_CFG_USE_QUEUES TRUE
-
-/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
@@ -443,6 +437,20 @@ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
+ +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /**
* @brief Idle thread enter hook.
@@ -487,6 +495,15 @@ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
+ +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} /** @} */
diff --git a/testhal/KINETIS/I2C/halconf.h b/testhal/KINETIS/FRDM-K20D50M/I2C/halconf.h index 6430fb2..6430fb2 100644 --- a/testhal/KINETIS/I2C/halconf.h +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/halconf.h diff --git a/testhal/KINETIS/I2C/main.c b/testhal/KINETIS/FRDM-K20D50M/I2C/main.c index 8c0df50..8c0df50 100644 --- a/testhal/KINETIS/I2C/main.c +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/main.c diff --git a/testhal/KINETIS/ADC/mcuconf.h b/testhal/KINETIS/FRDM-K20D50M/I2C/mcuconf.h index 03a7de5..0b7c312 100644 --- a/testhal/KINETIS/ADC/mcuconf.h +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/mcuconf.h @@ -17,21 +17,7 @@ #ifndef _MCUCONF_H_
#define _MCUCONF_H_
-/*
- * STM32F0xx drivers configuration.
- * The following settings override the default settings present in
- * the various device driver implementation headers.
- * Note that the settings for each driver only have effect if the whole
- * driver is enabled in halconf.h.
- *
- * IRQ priorities:
- * 3...0 Lowest...Highest.
- *
- * DMA priorities:
- * 0...3 Lowest...Highest.
- */
-
-#define KL2x_MCUCONF
+#define K20x_MCUCONF
/*
* HAL driver system settings.
@@ -39,32 +25,51 @@ /* Select the MCU clocking mode below by enabling the appropriate block. */
-/* FEI mode */
+/* Enable clock initialization by HAL */
+#define KINETIS_NO_INIT FALSE
+
+/* PEE mode - external (8 MHz) crystal with PLL for 48 MHz core/system clock. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
-#define KINETIS_SYSCLK_FREQUENCY 21000000UL
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
+#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
+/* not implemented */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
@@ -72,10 +77,7 @@ * SERIAL driver system settings.
*/
#define KINETIS_SERIAL_USE_UART0 FALSE
-
-/*
- * ADC driver system settings.
- */
-#define KINETIS_ADC_USE_ADC0 TRUE
+#define KINETIS_I2C_USE_I2C0 TRUE
+#define KINETIS_I2C_I2C0_PRIORITY 8
#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/I2C/readme.txt b/testhal/KINETIS/FRDM-K20D50M/I2C/readme.txt index 0a9a5fc..0a9a5fc 100644 --- a/testhal/KINETIS/I2C/readme.txt +++ b/testhal/KINETIS/FRDM-K20D50M/I2C/readme.txt diff --git a/testhal/KINETIS/ADC/.cproject b/testhal/KINETIS/FRDM-KL25Z/ADC/.cproject index 4e28c4a..4e28c4a 100644 --- a/testhal/KINETIS/ADC/.cproject +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/.cproject diff --git a/testhal/KINETIS/ADC/.project b/testhal/KINETIS/FRDM-KL25Z/ADC/.project index 0bd79df..0bd79df 100644 --- a/testhal/KINETIS/ADC/.project +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/.project diff --git a/testhal/KINETIS/FRDM-KL25Z/ADC/Makefile b/testhal/KINETIS/FRDM-KL25Z/ADC/Makefile new file mode 100644 index 0000000..59476de --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/Makefile @@ -0,0 +1,207 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT = -std=gnu99
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/I2C/chconf.h b/testhal/KINETIS/FRDM-KL25Z/ADC/chconf.h index b7a340d..eecc0a6 100644 --- a/testhal/KINETIS/I2C/chconf.h +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/chconf.h @@ -27,6 +27,8 @@ #ifndef _CHCONF_H_
#define _CHCONF_H_
+ +#define _CHIBIOS_RT_CONF_ /*===========================================================================*/
/**
@@ -263,14 +265,6 @@ #define CH_CFG_USE_MAILBOXES TRUE
/**
- * @brief I/O Queues APIs.
- * @details If enabled then the I/O queues APIs are included in the kernel.
- *
- * @note The default is @p TRUE.
- */
-#define CH_CFG_USE_QUEUES TRUE
-
-/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
@@ -443,6 +437,20 @@ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
+ +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /**
* @brief Idle thread enter hook.
@@ -487,6 +495,15 @@ #define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
+ +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} /** @} */
diff --git a/testhal/KINETIS/ADC/debug/RT-FREEDOM-KL25Z-ADC.launch b/testhal/KINETIS/FRDM-KL25Z/ADC/debug/RT-FREEDOM-KL25Z-ADC.launch index 67d3e82..67d3e82 100644 --- a/testhal/KINETIS/ADC/debug/RT-FREEDOM-KL25Z-ADC.launch +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/debug/RT-FREEDOM-KL25Z-ADC.launch diff --git a/testhal/KINETIS/ADC/halconf.h b/testhal/KINETIS/FRDM-KL25Z/ADC/halconf.h index f8b4e8c..f8b4e8c 100644 --- a/testhal/KINETIS/ADC/halconf.h +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/halconf.h diff --git a/testhal/KINETIS/ADC/main.c b/testhal/KINETIS/FRDM-KL25Z/ADC/main.c index f01051b..f01051b 100644 --- a/testhal/KINETIS/ADC/main.c +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/main.c diff --git a/testhal/KINETIS/I2C/mcuconf.h b/testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h index c5d56f2..b657ccf 100644 --- a/testhal/KINETIS/I2C/mcuconf.h +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/mcuconf.h @@ -17,30 +17,29 @@ #ifndef _MCUCONF_H_
#define _MCUCONF_H_
-#define K20x_MCUCONF
+#define KL2x_MCUCONF
/*
* HAL driver system settings.
*/
/* Select the MCU clocking mode below by enabling the appropriate block. */
+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
-/* Enable clock initialization by HAL */
-#define KINETIS_NO_INIT FALSE
-
-/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
+/* PEE mode - 48MHz system clock driven by external crystal. */
#if 1
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
-#define KINETIS_XTAL_FREQUENCY 8000000UL
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#endif
-/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
@@ -48,12 +47,12 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
#endif /* 0 */
/* FEE mode - 48 MHz */
@@ -61,8 +60,8 @@ #define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
-#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
-#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
@@ -70,7 +69,10 @@ * SERIAL driver system settings.
*/
#define KINETIS_SERIAL_USE_UART0 FALSE
-#define KINETIS_I2C_USE_I2C0 TRUE
-#define KINETIS_I2C_I2C0_PRIORITY 8
+
+/*
+ * ADC driver system settings.
+ */
+#define KINETIS_ADC_USE_ADC0 TRUE
#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/ADC/readme.txt b/testhal/KINETIS/FRDM-KL25Z/ADC/readme.txt index 4077343..4077343 100644 --- a/testhal/KINETIS/ADC/readme.txt +++ b/testhal/KINETIS/FRDM-KL25Z/ADC/readme.txt diff --git a/testhal/KINETIS/FRDM-KL25Z/GPT/Makefile b/testhal/KINETIS/FRDM-KL25Z/GPT/Makefile new file mode 100644 index 0000000..7b8653a --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/GPT/Makefile @@ -0,0 +1,211 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/FRDM-KL25Z/GPT/chconf.h b/testhal/KINETIS/FRDM-KL25Z/GPT/chconf.h new file mode 100644 index 0000000..b7ffc80 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/GPT/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL25Z/GPT/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL25Z/GPT/halconf.h b/testhal/KINETIS/FRDM-KL25Z/GPT/halconf.h new file mode 100644 index 0000000..bd57f0a --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/GPT/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL25Z/GPT/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT TRUE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL25Z/GPT/main.c b/testhal/KINETIS/FRDM-KL25Z/GPT/main.c new file mode 100644 index 0000000..926730d --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/GPT/main.c @@ -0,0 +1,75 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#define POLLED_TEST FALSE
+
+void gptcb(GPTDriver *gptp) {
+ (void)gptp;
+ palTogglePad(GPIO_LED_GREEN, PIN_LED_GREEN);
+}
+
+/*
+ * GPT configuration structure.
+ */
+static const GPTConfig gpt1cfg = {
+ 4,
+ gptcb
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Turn off the RGB LED.
+ */
+ palSetPad(GPIO_LED_RED, PIN_LED_RED); /* red */
+ palSetPad(GPIO_LED_GREEN, PIN_LED_GREEN); /* green */
+ palSetPad(GPIO_LED_BLUE, PIN_LED_BLUE); /* blue */
+
+ /*
+ * Initializes the GPT driver 1.
+ */
+ gptStart(&GPTD1, &gpt1cfg);
+
+#if !POLLED_TEST
+ gptStartContinuous(&GPTD1, 2);
+#endif
+
+ while (1) {
+#if POLLED_TEST
+ gpt_lld_polled_delay(&GPTD1, 1) ;
+ palTogglePad(GPIO_LED_GREEN, PIN_LED_GREEN);
+#else
+ chThdSleepMilliseconds(500);
+#endif
+ }
+}
diff --git a/testhal/KINETIS/FRDM-KL25Z/GPT/mcuconf.h b/testhal/KINETIS/FRDM-KL25Z/GPT/mcuconf.h new file mode 100644 index 0000000..6a2d2d7 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/GPT/mcuconf.h @@ -0,0 +1,42 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by (8 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+
+/*
+ * GPT driver system settings.
+ */
+#define KINETIS_GPT_USE_PIT0 TRUE
+#define KINETIS_GPT_PIT0_IRQ_PRIORITY 2
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/FRDM-KL25Z/PWM/Makefile b/testhal/KINETIS/FRDM-KL25Z/PWM/Makefile new file mode 100644 index 0000000..7b8653a --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/PWM/Makefile @@ -0,0 +1,211 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/FRDM-KL25Z/PWM/chconf.h b/testhal/KINETIS/FRDM-KL25Z/PWM/chconf.h new file mode 100644 index 0000000..25dd7b8 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/PWM/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL25Z/PWM/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL25Z/PWM/halconf.h b/testhal/KINETIS/FRDM-KL25Z/PWM/halconf.h new file mode 100644 index 0000000..89d31a5 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/PWM/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FRDM-KL25Z/PWM/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/KINETIS/FRDM-KL25Z/PWM/main.c b/testhal/KINETIS/FRDM-KL25Z/PWM/main.c new file mode 100644 index 0000000..b7e873c --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/PWM/main.c @@ -0,0 +1,128 @@ +/* + * (c) 2015 flabbergast <s3+flabbergast@sdfeu.org> + * Based on ChibiOS 3.0.1 demo code, license below. + * Licensed under the Apache License, Version 2.0. + */ + +/* + * ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ch.h" +#include "hal.h" + +/* + * on FRDM-KL25Z: + * red LED on PTB18/TPM2_CH0 (AF3) + * green LED on PTB19/TPM2_CH1 (AF3) + */ + +#define PWM_DRIVER PWMD3 + +/* PWM config structure */ +/* Note: the PWM clock frequency must be so that + * SYSCLK / FREQ is a power of 2 between 1 and 128. + */ +static const PWMConfig pwmcfg = { + 750000, /* 750kHz PWM clock frequency. */ + 1000, /* PWM period is 1000 cycles. */ + /* meaning PWM resolution is 750 */ + NULL, /* no callback */ + { + {PWM_OUTPUT_ACTIVE_LOW, NULL}, /* ch0: mode, no callback */ + {PWM_OUTPUT_ACTIVE_LOW, NULL}, /* ch1: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL}, /* ch2: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL}, /* ch3: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL}, /* ch4: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL} /* ch5: mode, no callback */ + }, +}; + +#define BREATHE_STEP 16 /* ms; = 4000ms/TABLE_SIZE */ + +/* Breathing Sleep LED brighness(PWM On period) table + * + * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63 + * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i } + */ +/* ruby -e "a = ((0..255).map{|x| Math.exp(Math.cos(Math::PI+(2*x*(Math::PI)/255)))-Math.exp(-1) }); m = a.max; a.map\!{|x| (10000*x/m).to_i}; p a" */ +#define TABLE_SIZE 256 +static const uint16_t breathing_table[TABLE_SIZE] = { + 0, 0, 1, 4, 7, 11, 17, 23, 30, 38, 47, 58, 69, 81, 94, 109, 124, 141, 159, 177, 197, 218, 241, 264, 289, 315, 343, 372, 402, 433, 466, 501, 537, 574, 613, 654, 696, 741, 786, 834, 883, 935, 988, 1043, 1100, 1159, 1220, 1283, 1349, 1416, 1486, 1558, 1632, 1709, 1788, 1870, 1954, 2040, 2129, 2220, 2314, 2411, 2510, 2611, 2715, 2822, 2932, 3044, 3158, 3275, 3395, 3517, 3641, 3768, 3897, 4028, 4162, 4298, 4436, 4576, 4717, 4861, 5006, 5152, 5300, 5449, 5600, 5751, 5903, 6055, 6208, 6361, 6513, 6666, 6818, 6970, 7120, 7269, 7417, 7563, 7708, 7850, 7990, 8127, 8261, 8391, 8519, 8643, 8762, 8878, 8989, 9095, 9196, 9293, 9383, 9469, 9548, 9622, 9689, 9750, 9805, 9853, 9895, 9930, 9957, 9978, 9992, 9999, 10000, 9992, 9978, 9957, 9930, 9895, 9853, 9805, 9750, 9689, 9622, 9548, 9469, 9383, 9293, 9196, 9095, 8989, 8878, 8762, 8643, 8519, 8391, 8261, 8127, 7990, 7850, 7708, 7563, 7417, 7269, 7120, 6970, 6818, 6666, 6513, 6361, 6208, 6055, 5903, 5751, 5600, 5449, 5300, 5152, 5006, 4861, 4717, 4576, 4436, 4298, 4162, 4028, 3897, 3768, 3641, 3517, 3395, 3275, 3158, 3044, 2932, 2822, 2715, 2611, 2510, 2411, 2314, 2220, 2129, 2040, 1954, 1870, 1788, 1709, 1632, 1558, 1486, 1416, 1349, 1283, 1220, 1159, 1100, 1043, 988, 935, 883, 834, 786, 741, 696, 654, 613, 574, 537, 501, 466, 433, 402, 372, 343, 315, 289, 264, 241, 218, 197, 177, 159, 141, 124, 109, 94, 81, 69, 58, 47, 38, 30, 23, 17, 11, 7, 4, 1, 0, 0 +}; + +uint16_t table_pos = 0; +uint8_t active_led = 0; + +static THD_WORKING_AREA(waBreatheThread, 128); +static THD_FUNCTION(BreatheThread, arg) { + (void)arg; + chRegSetThreadName("breatheThread"); + + while(true) { + pwmEnableChannel(&PWM_DRIVER, active_led, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos])); + table_pos++; + if(table_pos == TABLE_SIZE) { + table_pos = 0; + active_led = (active_led+1) % 2; + } + chThdSleepMilliseconds(BREATHE_STEP); + } +} + +/* + * Application entry point. + */ +int main(void) { + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Turn off the RGB LED. + */ + palSetPad(GPIO_LED_RED, PIN_LED_RED); /* red */ + palSetPad(GPIO_LED_GREEN, PIN_LED_GREEN); /* green */ + palSetPad(GPIO_LED_BLUE, PIN_LED_BLUE); /* blue */ + + /* + * Start the PWM driver, route TPM2 output to PTB18, PTB19. + * Enable channels now to avoid a blink later. + */ + pwmStart(&PWM_DRIVER, &pwmcfg); + palSetPadMode(GPIO_LED_RED, PIN_LED_RED, PAL_MODE_ALTERNATIVE_3); + palSetPadMode(GPIO_LED_GREEN, PIN_LED_GREEN, PAL_MODE_ALTERNATIVE_3); + pwmEnableChannel(&PWM_DRIVER, 0, 0); + pwmEnableChannel(&PWM_DRIVER, 1, 0); + + /* + * Create the breathe thread. + */ + chThdCreateStatic(waBreatheThread, sizeof(waBreatheThread), NORMALPRIO, BreatheThread, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop. + */ + while(true) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/KINETIS/FRDM-KL25Z/PWM/mcuconf.h b/testhal/KINETIS/FRDM-KL25Z/PWM/mcuconf.h new file mode 100644 index 0000000..ff704e6 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/PWM/mcuconf.h @@ -0,0 +1,47 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by (8 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+/*
+ * PWM driver settings.
+ */
+#define KINETIS_PWM_USE_TPM2 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/Makefile b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/Makefile new file mode 100644 index 0000000..e738944 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/Makefile @@ -0,0 +1,217 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ usbcfg.c \ + main.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c \ + $(CHIBIOS)/os/various/shell/shell.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various/shell $(CHIBIOS)/os/hal/lib/streams
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chconf.h b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chconf.h new file mode 100644 index 0000000..a185ac6 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL25Z/USB_SERIAL/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chtsy.inf b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chtsy.inf new file mode 100644 index 0000000..4ae7d0b --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/chtsy.inf @@ -0,0 +1,106 @@ +;************************************************************
+; Windows USB CDC ACM Setup File
+; Copyright (c) 2000 Microsoft Corporation
+
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%MFGNAME%
+LayoutFile=layout.inf
+CatalogFile=%MFGFILENAME%.cat
+DriverVer=11/15/2007,5.1.2600.0
+
+[Manufacturer]
+%MFGNAME%=DeviceList, NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP/Vista-32bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.nt]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.nt
+AddReg=DriverInstall.nt.AddReg
+
+[DriverCopyFiles.nt]
+usbser.sys,,,0x20
+
+[DriverInstall.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.nt.Services]
+AddService=usbser, 0x00000002, DriverService.nt
+
+[DriverService.nt]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+;------------------------------------------------------------------------------
+; Vista-64bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+%DRIVERFILENAME%.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+
+;------------------------------------------------------------------------------
+; Vendor and Product ID Definitions
+;------------------------------------------------------------------------------
+; When developing your USB device, the VID and PID used in the PC side
+; application program and the firmware on the microcontroller must match.
+; Modify the below line to use your VID and PID. Use the format as shown below.
+; Note: One INF file can be used for multiple devices with different VID and PIDs.
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
+;------------------------------------------------------------------------------
+[SourceDisksFiles]
+[SourceDisksNames]
+[DeviceList]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+[DeviceList.NTamd64]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+;Modify these strings to customize your device
+;------------------------------------------------------------------------------
+[Strings]
+MFGFILENAME="ChTsy"
+DRIVERFILENAME ="usbser"
+MFGNAME="NopeLab"
+INSTDISK="ChTsy CDC driver"
+DESCRIPTION="ChTsy CDC driver"
+SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/halconf.h b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/halconf.h new file mode 100644 index 0000000..6bb60f7 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/halconf.h @@ -0,0 +1,362 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL25Z/USB_SERIAL/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*
+ * @brief Enable debugging messages over SD1.
+ *
+ * @note Requires HAL_USE_SERIAL.
+ */
+#if HAL_USE_SERIAL
+#define DEBUG_USB
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/main.c b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/main.c new file mode 100644 index 0000000..103991a --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/main.c @@ -0,0 +1,169 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "shell.h"
+#include "chprintf.h"
+
+#include "usbcfg.h"
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+
+/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/
+static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static uint8_t buf[] =
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: write\r\n");
+ return;
+ }
+
+ while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
+#if 1
+ /* Writing in channel mode.*/
+ chnWrite(&SDU1, buf, sizeof buf - 1);
+#else
+ /* Writing in buffer mode.*/
+ (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE);
+ memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE);
+ obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE);
+#endif
+ }
+ chprintf(chp, "\r\n\nstopped\r\n");
+}
+
+static const ShellCommand commands[] = {
+ {"write", cmd_write},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Generic code. */
+/*===========================================================================*/
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ systime_t time;
+
+ time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500;
+ palClearPad(GPIO_LED_RED, PIN_LED_RED);
+ chThdSleepMilliseconds(time);
+ palSetPad(GPIO_LED_RED, PIN_LED_RED);
+ chThdSleepMilliseconds(time);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Turn off the RGB LED.
+ */
+ palSetPad(GPIO_LED_RED, PIN_LED_RED); /* red */
+ palSetPad(GPIO_LED_GREEN, PIN_LED_GREEN); /* green */
+ palSetPad(GPIO_LED_BLUE, PIN_LED_BLUE); /* blue */
+
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1500);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, spawning shells.
+ */
+ while (true) {
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
+ "shell", NORMALPRIO + 1,
+ shellThread, (void *)&shell_cfg1);
+ chThdWait(shelltp); /* Waiting termination. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/mcuconf.h b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/mcuconf.h new file mode 100644 index 0000000..42c9361 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/mcuconf.h @@ -0,0 +1,53 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 0
+/* PEE mode - 48MHz system clock driven by (8 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 1
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+#endif /* _MCUCONF_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c new file mode 100644 index 0000000..3093640 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c @@ -0,0 +1,329 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+
+/*
+ * Endpoints to be used for USBD1.
+ */
+#define USBD1_DATA_REQUEST_EP 1
+#define USBD1_DATA_AVAILABLE_EP 1
+#define USBD1_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0179, /* idVendor. */
+ 0x0001, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(2+2*7), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'N', 0, 'o', 0, 'p', 0, 'e', 0, 'L', 0, 'a', 0, 'b', 0,
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(2+5*2), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'T', 0, 's', 0, 'y', 0,
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduDisconnectI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * Handles the USB driver global events.
+ */
+static void sof_handler(USBDriver *usbp) {
+
+ (void)usbp;
+
+ osalSysLockFromISR();
+ sduSOFHookI(&SDU1);
+ osalSysUnlockFromISR();
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ sof_handler
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD1,
+ USBD1_DATA_REQUEST_EP,
+ USBD1_DATA_AVAILABLE_EP,
+ USBD1_INTERRUPT_REQUEST_EP
+};
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.h b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.h new file mode 100644 index 0000000..5aa501e --- /dev/null +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.h @@ -0,0 +1,27 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+extern SerialUSBDriver SDU1;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL26Z/PWM/Makefile b/testhal/KINETIS/FRDM-KL26Z/PWM/Makefile new file mode 100644 index 0000000..ab8d090 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/PWM/Makefile @@ -0,0 +1,211 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/FRDM-KL26Z/PWM/chconf.h b/testhal/KINETIS/FRDM-KL26Z/PWM/chconf.h new file mode 100644 index 0000000..8c37f87 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/PWM/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL26Z/PWM/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL26Z/PWM/halconf.h b/testhal/KINETIS/FRDM-KL26Z/PWM/halconf.h new file mode 100644 index 0000000..c65617e --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/PWM/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org> + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file FRDM-KL26Z/PWM/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/KINETIS/FRDM-KL26Z/PWM/main.c b/testhal/KINETIS/FRDM-KL26Z/PWM/main.c new file mode 100644 index 0000000..9e41bf6 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/PWM/main.c @@ -0,0 +1,172 @@ +/* + * (c) 2015 flabbergast <s3+flabbergast@sdfeu.org> + * Based on ChibiOS 3.0.1 demo code, license below. + * Licensed under the Apache License, Version 2.0. + */ + +/* + * ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ch.h" +#include "hal.h" + +/* + * on FRDM-KL26Z: + * red LED on PTE29/TPM0_CH2 (AF3) + * green LED on PTE31/TPM0_CH4 (AF3) + * blue LED on PTD5/TPM0_CH5 (AF4) + */ + +#define PWM_DRIVER PWMD1 + +/* PWM config structure */ +/* Note: the PWM clock frequency must be so that + * SYSCLK / FREQ is a power of 2 between 1 and 128. + */ +static const PWMConfig pwmcfg = { + 750000, /* 750kHz PWM clock frequency. */ + 1000, /* PWM period is 1000 cycles. */ + /* meaning PWM resolution is 750 */ + NULL, /* no callback */ + { + {PWM_OUTPUT_DISABLED, NULL}, /* ch0: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL}, /* ch1: mode, no callback */ + {PWM_OUTPUT_ACTIVE_LOW, NULL}, /* ch2: mode, no callback */ + {PWM_OUTPUT_DISABLED, NULL}, /* ch3: mode, no callback */ + {PWM_OUTPUT_ACTIVE_LOW, NULL}, /* ch4: mode, no callback */ + {PWM_OUTPUT_ACTIVE_LOW, NULL} /* ch5: mode, no callback */ + }, +}; + +#define BREATHE_STEP 16 /* ms; = 4000ms/TABLE_SIZE */ + +/* Breathing Sleep LED brighness(PWM On period) table + * + * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63 + * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i } + */ +/* ruby -e "a = ((0..255).map{|x| Math.exp(Math.cos(Math::PI+(2*x*(Math::PI)/255)))-Math.exp(-1) }); m = a.max; a.map\!{|x| (10000*x/m).to_i}; p a" */ +#define TABLE_SIZE 256 +static const uint16_t breathing_table[TABLE_SIZE] = { + 0, 0, 1, 4, 7, 11, 17, 23, 30, 38, 47, 58, 69, 81, 94, 109, 124, 141, 159, 177, 197, 218, 241, 264, 289, 315, 343, 372, 402, 433, 466, 501, 537, 574, 613, 654, 696, 741, 786, 834, 883, 935, 988, 1043, 1100, 1159, 1220, 1283, 1349, 1416, 1486, 1558, 1632, 1709, 1788, 1870, 1954, 2040, 2129, 2220, 2314, 2411, 2510, 2611, 2715, 2822, 2932, 3044, 3158, 3275, 3395, 3517, 3641, 3768, 3897, 4028, 4162, 4298, 4436, 4576, 4717, 4861, 5006, 5152, 5300, 5449, 5600, 5751, 5903, 6055, 6208, 6361, 6513, 6666, 6818, 6970, 7120, 7269, 7417, 7563, 7708, 7850, 7990, 8127, 8261, 8391, 8519, 8643, 8762, 8878, 8989, 9095, 9196, 9293, 9383, 9469, 9548, 9622, 9689, 9750, 9805, 9853, 9895, 9930, 9957, 9978, 9992, 9999, 10000, 9992, 9978, 9957, 9930, 9895, 9853, 9805, 9750, 9689, 9622, 9548, 9469, 9383, 9293, 9196, 9095, 8989, 8878, 8762, 8643, 8519, 8391, 8261, 8127, 7990, 7850, 7708, 7563, 7417, 7269, 7120, 6970, 6818, 6666, 6513, 6361, 6208, 6055, 5903, 5751, 5600, 5449, 5300, 5152, 5006, 4861, 4717, 4576, 4436, 4298, 4162, 4028, 3897, 3768, 3641, 3517, 3395, 3275, 3158, 3044, 2932, 2822, 2715, 2611, 2510, 2411, 2314, 2220, 2129, 2040, 1954, 1870, 1788, 1709, 1632, 1558, 1486, 1416, 1349, 1283, 1220, 1159, 1100, 1043, 988, 935, 883, 834, 786, 741, 696, 654, 613, 574, 537, 501, 466, 433, 402, 372, 343, 315, 289, 264, 241, 218, 197, 177, 159, 141, 124, 109, 94, 81, 69, 58, 47, 38, 30, 23, 17, 11, 7, 4, 1, 0, 0 +}; + +uint16_t table_pos = 0; +uint8_t active_led = 0; + +static THD_WORKING_AREA(waBreatheThread, 128); +static THD_FUNCTION(BreatheThread, arg) { + (void)arg; + chRegSetThreadName("breatheThread"); + + while(true) { + switch(active_led) { + case 0: /* red LED */ + pwmEnableChannel(&PWM_DRIVER, 2, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos])); + break; + case 1: /* green LED */ + pwmEnableChannel(&PWM_DRIVER, 4, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos])); + break; + case 2: /* blue LED */ + pwmEnableChannel(&PWM_DRIVER, 5, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos])); + break; + } + table_pos++; + if(table_pos == TABLE_SIZE) { + table_pos = 0; + active_led = (active_led+1) % 3; + } + chThdSleepMilliseconds(BREATHE_STEP); + } +} + +/* + * Check button thread + */ +static THD_WORKING_AREA(waButtonThread, 128); +static THD_FUNCTION(ButtonThread, arg) { + (void)arg; + chRegSetThreadName("buttonThread"); + + uint8_t newstate, state = PAL_HIGH; + + while(true) { + if(palReadPad(GPIO_BUTTON, PIN_BUTTON) != state) { + chThdSleepMilliseconds(20); /* debounce */ + newstate = palReadPad(GPIO_BUTTON, PIN_BUTTON); + if(newstate != state) { + state = newstate; + if(newstate == PAL_LOW) { + table_pos = (table_pos + 120)%TABLE_SIZE; + } + } + } + chThdSleepMilliseconds(20); + } +} + +/* + * Application entry point. + */ +int main(void) { + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Turn off the RGB LED. + */ + palSetPad(GPIO_LED_RED, PIN_LED_RED); /* red */ + palSetPad(GPIO_LED_GREEN, PIN_LED_GREEN); /* green */ + palSetPad(GPIO_LED_BLUE, PIN_LED_BLUE); /* blue */ + + /* + * Create the button check thread. + */ + chThdCreateStatic(waButtonThread, sizeof(waButtonThread), NORMALPRIO, ButtonThread, NULL); + + /* + * Start the PWM driver, route TPM0 output to PTE29, PTE31, PTD5. + * Enable channels now to avoid a blink later. + */ + pwmStart(&PWM_DRIVER, &pwmcfg); + palSetPadMode(GPIO_LED_RED, PIN_LED_RED, PAL_MODE_ALTERNATIVE_3); + palSetPadMode(GPIO_LED_GREEN, PIN_LED_GREEN, PAL_MODE_ALTERNATIVE_3); + palSetPadMode(GPIO_LED_BLUE, PIN_LED_BLUE, PAL_MODE_ALTERNATIVE_4); + pwmEnableChannel(&PWM_DRIVER, 2, 0); + pwmEnableChannel(&PWM_DRIVER, 4, 0); + pwmEnableChannel(&PWM_DRIVER, 5, 0); + + /* + * Create the breathe thread. + */ + chThdCreateStatic(waBreatheThread, sizeof(waBreatheThread), NORMALPRIO, BreatheThread, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed ... nothing happens. + */ + while(true) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/KINETIS/FRDM-KL26Z/PWM/mcuconf.h b/testhal/KINETIS/FRDM-KL26Z/PWM/mcuconf.h new file mode 100644 index 0000000..3622a23 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/PWM/mcuconf.h @@ -0,0 +1,58 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* PEE mode - 48MHz system clock driven by (8 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 0
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+/*
+ * PWM driver settings.
+ */
+#define KINETIS_PWM_USE_TPM0 TRUE
+
+#endif /* _MCUCONF_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/Makefile b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/Makefile new file mode 100644 index 0000000..7ea082f --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/Makefile @@ -0,0 +1,217 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ main.c \
+ usbcfg.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c \
+ $(CHIBIOS)/os/various/shell/shell.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various/shell $(CHIBIOS)/os/hal/lib/streams
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chconf.h b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chconf.h new file mode 100644 index 0000000..48f3aae --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL26Z/USB_SERIAL/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chtsy.inf b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chtsy.inf new file mode 100644 index 0000000..4ae7d0b --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/chtsy.inf @@ -0,0 +1,106 @@ +;************************************************************
+; Windows USB CDC ACM Setup File
+; Copyright (c) 2000 Microsoft Corporation
+
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%MFGNAME%
+LayoutFile=layout.inf
+CatalogFile=%MFGFILENAME%.cat
+DriverVer=11/15/2007,5.1.2600.0
+
+[Manufacturer]
+%MFGNAME%=DeviceList, NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP/Vista-32bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.nt]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.nt
+AddReg=DriverInstall.nt.AddReg
+
+[DriverCopyFiles.nt]
+usbser.sys,,,0x20
+
+[DriverInstall.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.nt.Services]
+AddService=usbser, 0x00000002, DriverService.nt
+
+[DriverService.nt]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+;------------------------------------------------------------------------------
+; Vista-64bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+%DRIVERFILENAME%.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+
+;------------------------------------------------------------------------------
+; Vendor and Product ID Definitions
+;------------------------------------------------------------------------------
+; When developing your USB device, the VID and PID used in the PC side
+; application program and the firmware on the microcontroller must match.
+; Modify the below line to use your VID and PID. Use the format as shown below.
+; Note: One INF file can be used for multiple devices with different VID and PIDs.
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
+;------------------------------------------------------------------------------
+[SourceDisksFiles]
+[SourceDisksNames]
+[DeviceList]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+[DeviceList.NTamd64]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+;Modify these strings to customize your device
+;------------------------------------------------------------------------------
+[Strings]
+MFGFILENAME="ChTsy"
+DRIVERFILENAME ="usbser"
+MFGNAME="NopeLab"
+INSTDISK="ChTsy CDC driver"
+DESCRIPTION="ChTsy CDC driver"
+SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/halconf.h b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/halconf.h new file mode 100644 index 0000000..a299d39 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FRDM-KL26Z/USB_SERIAL/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/main.c b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/main.c new file mode 100644 index 0000000..103991a --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/main.c @@ -0,0 +1,169 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "shell.h"
+#include "chprintf.h"
+
+#include "usbcfg.h"
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+
+/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/
+static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static uint8_t buf[] =
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: write\r\n");
+ return;
+ }
+
+ while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
+#if 1
+ /* Writing in channel mode.*/
+ chnWrite(&SDU1, buf, sizeof buf - 1);
+#else
+ /* Writing in buffer mode.*/
+ (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE);
+ memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE);
+ obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE);
+#endif
+ }
+ chprintf(chp, "\r\n\nstopped\r\n");
+}
+
+static const ShellCommand commands[] = {
+ {"write", cmd_write},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Generic code. */
+/*===========================================================================*/
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ systime_t time;
+
+ time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500;
+ palClearPad(GPIO_LED_RED, PIN_LED_RED);
+ chThdSleepMilliseconds(time);
+ palSetPad(GPIO_LED_RED, PIN_LED_RED);
+ chThdSleepMilliseconds(time);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Turn off the RGB LED.
+ */
+ palSetPad(GPIO_LED_RED, PIN_LED_RED); /* red */
+ palSetPad(GPIO_LED_GREEN, PIN_LED_GREEN); /* green */
+ palSetPad(GPIO_LED_BLUE, PIN_LED_BLUE); /* blue */
+
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1500);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, spawning shells.
+ */
+ while (true) {
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
+ "shell", NORMALPRIO + 1,
+ shellThread, (void *)&shell_cfg1);
+ chThdWait(shelltp); /* Waiting termination. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/mcuconf.h b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/mcuconf.h new file mode 100644 index 0000000..42c9361 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/mcuconf.h @@ -0,0 +1,53 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 0
+/* PEE mode - 48MHz system clock driven by (8 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 1
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+#endif /* _MCUCONF_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c new file mode 100644 index 0000000..3093640 --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c @@ -0,0 +1,329 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+
+/*
+ * Endpoints to be used for USBD1.
+ */
+#define USBD1_DATA_REQUEST_EP 1
+#define USBD1_DATA_AVAILABLE_EP 1
+#define USBD1_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0179, /* idVendor. */
+ 0x0001, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(2+2*7), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'N', 0, 'o', 0, 'p', 0, 'e', 0, 'L', 0, 'a', 0, 'b', 0,
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(2+5*2), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'T', 0, 's', 0, 'y', 0,
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduDisconnectI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * Handles the USB driver global events.
+ */
+static void sof_handler(USBDriver *usbp) {
+
+ (void)usbp;
+
+ osalSysLockFromISR();
+ sduSOFHookI(&SDU1);
+ osalSysUnlockFromISR();
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ sof_handler
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD1,
+ USBD1_DATA_REQUEST_EP,
+ USBD1_DATA_AVAILABLE_EP,
+ USBD1_INTERRUPT_REQUEST_EP
+};
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.h b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.h new file mode 100644 index 0000000..5aa501e --- /dev/null +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.h @@ -0,0 +1,27 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+extern SerialUSBDriver SDU1;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/ADC/Makefile b/testhal/KINETIS/KL27Z/BLINK/Makefile index d438436..4f0d62a 100644 --- a/testhal/KINETIS/ADC/Makefile +++ b/testhal/KINETIS/KL27Z/BLINK/Makefile @@ -1,205 +1,211 @@ -##############################################################################
-# Build global options
-# NOTE: Can be overridden externally.
-#
-
-# Compiler options here.
-ifeq ($(USE_OPT),)
- USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
-endif
-
-# C specific options here (added to USE_OPT).
-ifeq ($(USE_COPT),)
- USE_COPT = -std=gnu99
-endif
-
-# C++ specific options here (added to USE_OPT).
-ifeq ($(USE_CPPOPT),)
- USE_CPPOPT = -fno-rtti
-endif
-
-# Enable this if you want the linker to remove unused code and data
-ifeq ($(USE_LINK_GC),)
- USE_LINK_GC = yes
-endif
-
-# Linker extra options here.
-ifeq ($(USE_LDOPT),)
- USE_LDOPT =
-endif
-
-# Enable this if you want link time optimizations (LTO)
-ifeq ($(USE_LTO),)
- USE_LTO = no
-endif
-
-# If enabled, this option allows to compile the application in THUMB mode.
-ifeq ($(USE_THUMB),)
- USE_THUMB = yes
-endif
-
-# Enable this if you want to see the full log while compiling.
-ifeq ($(USE_VERBOSE_COMPILE),)
- USE_VERBOSE_COMPILE = no
-endif
-
-# If enabled, this option makes the build process faster by not compiling
-# modules not used in the current configuration.
-ifeq ($(USE_SMART_BUILD),)
- USE_SMART_BUILD = yes
-endif
-
-#
-# Build global options
-##############################################################################
-
-##############################################################################
-# Architecture or project specific options
-#
-
-# Stack size to be allocated to the Cortex-M process stack. This stack is
-# the stack used by the main() thread.
-ifeq ($(USE_PROCESS_STACKSIZE),)
- USE_PROCESS_STACKSIZE = 0x200
-endif
-
-# Stack size to the allocated to the Cortex-M main/exceptions stack. This
-# stack is used for processing interrupts and exceptions.
-ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
- USE_EXCEPTIONS_STACKSIZE = 0x400
-endif
-
-#
-# Architecture or project specific options
-##############################################################################
-
-##############################################################################
-# Project, sources and paths
-#
-
-# Define project name here
-PROJECT = ch
-
-# Imported source files and paths
-CHIBIOS = ../../..
-include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
-include $(CHIBIOS)/os/hal/hal.mk
-include $(CHIBIOS)/os/hal/ports/KINETIS/KL2x/platform.mk
-include $(CHIBIOS)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
-include $(CHIBIOS)/os/hal/osal/rt/osal.mk
-include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
-
-# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/KL25Z128.ld
-
-# C sources that can be compiled in ARM or THUMB mode depending on the global
-# setting.
-CSRC = $(STARTUPSRC) \
- $(KERNSRC) \
- $(PORTSRC) \
- $(OSALSRC) \
- $(HALSRC) \
- $(PLATFORMSRC) \
- $(BOARDSRC) \
- main.c
-
-# C++ sources that can be compiled in ARM or THUMB mode depending on the global
-# setting.
-CPPSRC =
-
-# C sources to be compiled in ARM mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-ACSRC =
-
-# C++ sources to be compiled in ARM mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-ACPPSRC =
-
-# C sources to be compiled in THUMB mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-TCSRC =
-
-# C sources to be compiled in THUMB mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-TCPPSRC =
-
-# List ASM source files here
-ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
-
-INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
- $(HALINC) $(PLATFORMINC) $(BOARDINC) \
- $(CHIBIOS)/os/various
-
-#
-# Project, sources and paths
-##############################################################################
-
-##############################################################################
-# Compiler settings
-#
-
-MCU = cortex-m0
-
-#TRGT = arm-elf-
-TRGT = arm-none-eabi-
-CC = $(TRGT)gcc
-CPPC = $(TRGT)g++
-# Enable loading with g++ only if you need C++ runtime support.
-# NOTE: You can use C++ even without C++ support if you are careful. C++
-# runtime support makes code size explode.
-LD = $(TRGT)gcc
-#LD = $(TRGT)g++
-CP = $(TRGT)objcopy
-AS = $(TRGT)gcc -x assembler-with-cpp
-OD = $(TRGT)objdump
-SZ = $(TRGT)size
-HEX = $(CP) -O ihex
-BIN = $(CP) -O binary
-SREC = $(CP) -O srec
-
-# ARM-specific options here
-AOPT =
-
-# THUMB-specific options here
-TOPT = -mthumb -DTHUMB
-
-# Define C warning options here
-CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
-
-# Define C++ warning options here
-CPPWARN = -Wall -Wextra -Wundef
-
-#
-# Compiler settings
-##############################################################################
-
-##############################################################################
-# Start of user section
-#
-
-# List all user C define here, like -D_DEBUG=1
-UDEFS =
-
-# Define ASM defines here
-UADEFS =
-
-# List all user directories here
-UINCDIR =
-
-# List the user directory to look for the libraries here
-ULIBDIR =
-
-# List all user libraries here
-ULIBS =
-
-#
-# End of user defines
-##############################################################################
-
-RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
-include $(RULESPATH)/rules.mk
+############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk +include ./board/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MKL27Z256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/KL27Z/BLINK/board/board.c b/testhal/KINETIS/KL27Z/BLINK/board/board.c new file mode 100644 index 0000000..0f34452 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/board/board.c @@ -0,0 +1,158 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ /*
+ * PORTA setup.
+ *
+ * on pads: PTA1, PTA2, PTA5, PTA18, PTA19
+ *
+ * PTA0/3 SWD (default SWD, ALT_7: SWD, ALT_1: PTA0/3)
+ * PTA4 NMI button (default NMI_b, ALT_1: PTA4)
+ * PTA20 RESET button (default RESET, ALT_7: RESET, ALT_1: PTA20)
+ */
+ .port = IOPORT1,
+ .pads = {
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_ALTERNATIVE_7,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTB setup.
+ *
+ * on pads: PTB0, PTB1
+ * LED: PTB18
+ */
+ .port = IOPORT2,
+ .pads = {
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTC setup.
+ *
+ * on pads: PTC1, PTC2, PTC3, PTC6, PTC7, PTC8, PTC9
+ */
+ .port = IOPORT3,
+ .pads = {
+ PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTD setup.
+ *
+ * on pads: PTD0 - PTD7
+ */
+ .port = IOPORT4,
+ .pads = {
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTE setup.
+ *
+ * on pads: PTE0, PTE1, PTE24, PTE25, PTE29, PTE30
+ */
+ .port = IOPORT5,
+ .pads = {
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_PULLUP,
+ PAL_MODE_INPUT_PULLUP, PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ kl2x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/testhal/KINETIS/KL27Z/BLINK/board/board.h b/testhal/KINETIS/KL27Z/BLINK/board/board.h new file mode 100644 index 0000000..1c61915 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/board/board.h @@ -0,0 +1,53 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a custom KL27Z breakout board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_KL27Z_BREAKOUT
+#define BOARD_NAME "Custom KL27Z breakout"
+
+/*
+ * MCU type
+ */
+#define KL27Zxxx
+
+/*
+ * Onboard features.
+ */
+#define GPIO_LED IOPORT2
+#define PIN_LED 18
+#define GPIO_BUTTON IOPORT1
+#define PIN_BUTTON 4
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/testhal/KINETIS/KL27Z/BLINK/board/board.mk b/testhal/KINETIS/KL27Z/BLINK/board/board.mk new file mode 100644 index 0000000..14102c4 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/board/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ./board/board.c
+
+# Required include directories
+BOARDINC = ./board
diff --git a/testhal/KINETIS/KL27Z/BLINK/chconf.h b/testhal/KINETIS/KL27Z/BLINK/chconf.h new file mode 100644 index 0000000..41259a0 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/chconf.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL27Z/BLINK/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/KL27Z/BLINK/flash_via_bldr.sh b/testhal/KINETIS/KL27Z/BLINK/flash_via_bldr.sh new file mode 100755 index 0000000..8b0f26f --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/flash_via_bldr.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +if [ -z `which blhost` ]; then + echo "You'll need to get the 'blhost' utility from Freescale." + echo 'http://www.freescale.com/products/arm-processors/kinetis-cortex-m/kinetis-symbols-footprints-and-models/kinetis-bootloader:KBOOT' + exit 1 +fi + +if [ ! -f build/ch.bin ]; then + echo "Perhaps you should compile the firmware first." + exit 2 +fi + +if [[ `blhost -u -- get-property 1` == *"cannot open USB HID device"* ]]; then + echo "Perhaps you should put the device in the bootloader mode first." + exit 3 +fi + +echo "-> Erasing flash..." +blhost -u -- flash-erase-all + +echo "-> Flashing firmware..." +blhost -u -- write-memory 0 build/ch.bin + +echo "-> Resetting MCU (allow 5 seconds for the firmware to start)..." +blhost -u -- reset diff --git a/testhal/KINETIS/KL27Z/BLINK/halconf.h b/testhal/KINETIS/KL27Z/BLINK/halconf.h new file mode 100644 index 0000000..2e0b28c --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL27Z/BLINK/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/KL27Z/BLINK/main.c b/testhal/KINETIS/KL27Z/BLINK/main.c new file mode 100644 index 0000000..7af54b6 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/main.c @@ -0,0 +1,94 @@ +/*
+ ChibiOS/RT KL27 example - Copyright (C) 2015 flabbergast
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+/*
+ * Blink thread
+ */
+static THD_WORKING_AREA(waBlinkThread, 128);
+static THD_FUNCTION(BlinkThread, arg) {
+ (void)arg;
+
+ while(TRUE) {
+ palTogglePad(GPIO_LED, PIN_LED);
+ chThdSleepMilliseconds(700);
+ }
+}
+
+/*
+ * Check button thread
+ */
+static THD_WORKING_AREA(waButtonThread, 128);
+static THD_FUNCTION(ButtonThread, arg) {
+ (void)arg;
+ chRegSetThreadName("buttonThread");
+
+ uint8_t newstate, state = PAL_HIGH;
+
+ while(true) {
+ if(palReadPad(GPIO_BUTTON, PIN_BUTTON) != state) {
+ chThdSleepMilliseconds(20); /* debounce */
+ newstate = palReadPad(GPIO_BUTTON, PIN_BUTTON);
+ if(newstate != state) {
+ state = newstate;
+ if(newstate == PAL_LOW) {
+ // palTogglePad(GPIO_LED, PIN_LED);
+ /* jump to bootloader */
+ /* force boot from ROM */
+ RCM->FM = RCM_FM_FORCEROM(2);
+ /* request RESET */
+ #define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000
+ SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
+ }
+ }
+ }
+ chThdSleepMilliseconds(20);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Create the blink thread.
+ */
+ chThdCreateStatic(waBlinkThread, sizeof(waBlinkThread), NORMALPRIO, BlinkThread, NULL);
+
+ /*
+ * Create the button check thread.
+ */
+ chThdCreateStatic(waButtonThread, sizeof(waButtonThread), NORMALPRIO, ButtonThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while(TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/KL27Z/BLINK/mcuconf.h b/testhal/KINETIS/KL27Z/BLINK/mcuconf.h new file mode 100644 index 0000000..7048564 --- /dev/null +++ b/testhal/KINETIS/KL27Z/BLINK/mcuconf.h @@ -0,0 +1,79 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* High-frequency internal RC, 48MHz, possible USB clock recovery */
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#endif
+
+#if 0
+/* Low-frequency internal RC, 8 MHz mode */
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_LIRC8M
+#define KINETIS_SYSCLK_FREQUENCY 8000000UL
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+/*
+ * Kinetis FOPT configuration byte
+ */
+/* for KL27: */
+// #define KINETIS_NV_FOPT_BYTE 0x3D
+/* NV_FOPT: bit7-6/BOOTSRC_SEL=0b00 (11=from ROM; 00=from FLASH)
+ bit5/FAST_INIT=1, bit4/LPBOOT1=1,
+ bit3/RESET_PIN_CFG=1, bit2/NMI_DIS=1,
+ bit1/BOOTPIN_OPT=0, bit0/LPBOOT0=1 */
+/* BOOTPIN_OPT: 1=boot depends on BOOTSRC_SEL
+ 0=boot samples BOOTCFG0=NMI pin */
+/* Boot sequence, page 88 of manual:
+ * - If the NMI/BOOTCFG0 input is high or the NMI function is disabled in FTFA_FOPT, the CPU begins execution at the PC location.
+ * - If the NMI/BOOTCFG0 input is low, the NMI function is enabled in FTFA_FOPT, and FTFA_FOPT[BOOTPIN_OPT] = 1, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler.
+ * - When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/BOOTCFG0 pin set to 0.
+ *
+ * Observed behaviour:
+ * - when BOOTPIN_OPT=0, BOOTSRC_SEL still matters:
+ * - if 0b11 (from ROM), it still boots from ROM, even if BOOTCFG0 pin
+ * is high/floating, but leaves ROM and runs user app after
+ * 5 seconds delay.
+ * - if 0b00 (from FLASH), reset/powerup jumps to user app unless
+ * BOOTCFG0 pin is asserted.
+ * - in any case, reset when in bootloader induces the 5 second delay
+ * before starting the user app.
+ *
+ */
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/MCHCK/BOOTLOADER/Makefile b/testhal/KINETIS/MCHCK/BOOTLOADER/Makefile new file mode 100644 index 0000000..fee6658 --- /dev/null +++ b/testhal/KINETIS/MCHCK/BOOTLOADER/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/MCHCK_K20/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader +LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader, +# 0xc00 for a 3k bootloader +UDEFS = -DCORTEX_VTOR_INIT=0x00001000 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/MCHCK/BOOTLOADER/chconf.h b/testhal/KINETIS/MCHCK/BOOTLOADER/chconf.h new file mode 100644 index 0000000..b2448a9 --- /dev/null +++ b/testhal/KINETIS/MCHCK/BOOTLOADER/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/BOOTLOADER/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/BOOTLOADER/halconf.h b/testhal/KINETIS/MCHCK/BOOTLOADER/halconf.h new file mode 100644 index 0000000..ef54a5d --- /dev/null +++ b/testhal/KINETIS/MCHCK/BOOTLOADER/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/BOOTLOADER/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/BOOTLOADER/main.c b/testhal/KINETIS/MCHCK/BOOTLOADER/main.c new file mode 100644 index 0000000..a3729b7 --- /dev/null +++ b/testhal/KINETIS/MCHCK/BOOTLOADER/main.c @@ -0,0 +1,77 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define BTN_GPIO TEENSY_PIN2_IOPORT
+#define BTN_PIN TEENSY_PIN2
+
+/*
+ * Jump to bootloader on MCHCK.
+ */
+#define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000
+const uint8_t sys_reset_to_loader_magic[] = "\xff\x00\x7fRESET TO LOADER\x7f\x00\xff";
+
+void jump_to_bootloader(void) {
+ __builtin_memcpy((void *)VBAT, (const void *)sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic));
+ // request reset
+ SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
+}
+
+/*
+ * Blink thread.
+ */
+
+static THD_WORKING_AREA(waBlinkThread, 128);
+static THD_FUNCTION(BlinkThread, arg) {
+ (void)arg;
+ uint8_t i;
+
+ // while(TRUE) {
+ for(i=0; i<10; i++) {
+ palTogglePad(GPIOB, GPIOB_LED);
+ chThdSleepMilliseconds(700);
+ }
+ jump_to_bootloader();
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Create the blink thread.
+ */
+ chThdCreateStatic(waBlinkThread, sizeof(waBlinkThread), NORMALPRIO, BlinkThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while(TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/MCHCK/BOOTLOADER/mcuconf.h b/testhal/KINETIS/MCHCK/BOOTLOADER/mcuconf.h new file mode 100644 index 0000000..6b69edb --- /dev/null +++ b/testhal/KINETIS/MCHCK/BOOTLOADER/mcuconf.h @@ -0,0 +1,41 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 1
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
+
+/*
+ * PWM driver system settings.
+ */
+#define KINETIS_PWM_USE_FTM0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/MCHCK/PWM/Makefile b/testhal/KINETIS/MCHCK/PWM/Makefile new file mode 100644 index 0000000..fee6658 --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/MCHCK_K20/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader +LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader, +# 0xc00 for a 3k bootloader +UDEFS = -DCORTEX_VTOR_INIT=0x00001000 + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/MCHCK/PWM/README.md b/testhal/KINETIS/MCHCK/PWM/README.md new file mode 100644 index 0000000..6367722 --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/README.md @@ -0,0 +1,7 @@ +# "Soft" PWM demo + +The PWM in this demo is "soft", meaning that it does use a hardware timer to run, but the output is not directly routed to a pin; a callback functions which turn a LED on and off are used instead. + +## Notes + +The brightness percentages it goes only up to 9900 (99%) instead of 10000 (100%); otherwise there is a noticeable blink in the top of the cycle. The reason is that the on/off callback functions take too long to execute for this kind of (relatively fast) timer. Likewise, '0' (0%) in the cycle actually means that the LED doesn't get turned off, because the channel notification function that turns the LED off doesn't get called. So in a setup like this one, '1' should be the minimum; although it does mean that the LED is never fully off. diff --git a/testhal/KINETIS/MCHCK/PWM/chconf.h b/testhal/KINETIS/MCHCK/PWM/chconf.h new file mode 100644 index 0000000..034c6cc --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/PWM/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/PWM/halconf.h b/testhal/KINETIS/MCHCK/PWM/halconf.h new file mode 100644 index 0000000..f691656 --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/PWM/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/PWM/main.c b/testhal/KINETIS/MCHCK/PWM/main.c new file mode 100644 index 0000000..9ac569f --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/main.c @@ -0,0 +1,116 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define PWM_DRIVER PWMD1
+
+static void pwmpcb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palSetPad(GPIOB, GPIOB_LED);
+}
+
+static void pwmc0cb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palClearPad(GPIOB, GPIOB_LED);
+}
+
+static PWMConfig pwmcfg = {
+ 24000000, /* 24MHz PWM clock frequency. */
+ 12000, /* Initial PWM period 1ms */
+ pwmpcb,
+ {
+ {PWM_OUTPUT_DISABLED, pwmc0cb},
+ {PWM_OUTPUT_DISABLED, NULL},
+ },
+};
+
+/* Breathing Sleep LED brighness(PWM On period) table
+ *
+ * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63
+ * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i }
+ */
+/* ruby -e "a = ((0..255).map{|x| Math.exp(Math.cos(Math::PI+(2*x*(Math::PI)/255)))-Math.exp(-1) }); m = a.max; a.map\!{|x| (9900*x/m).to_i+1}; p a" */
+#define BREATHE_STEP 16 /* ms; = 4000ms/TABLE_SIZE */
+#define TABLE_SIZE 256
+static const uint16_t breathing_table[TABLE_SIZE] = {
+ 1, 1, 2, 5, 8, 12, 17, 24, 31, 39, 48, 58, 69, 81, 95, 109, 124, 140, 158, 177, 196, 217, 239, 263, 287, 313, 340, 369, 399, 430, 463, 497, 532, 570, 608, 649, 691, 734, 779, 827, 875, 926, 979, 1033, 1090, 1148, 1209, 1271, 1336, 1403, 1472, 1543, 1617, 1693, 1771, 1852, 1935, 2021, 2109, 2199, 2292, 2387, 2486, 2586, 2689, 2795, 2903, 3014, 3127, 3243, 3362, 3482, 3606, 3731, 3859, 3989, 4122, 4256, 4392, 4531, 4671, 4813, 4957, 5102, 5248, 5396, 5545, 5694, 5845, 5995, 6147, 6298, 6449, 6600, 6751, 6901, 7050, 7198, 7344, 7489, 7632, 7772, 7911, 8046, 8179, 8309, 8435, 8557, 8676, 8790, 8900, 9005, 9105, 9201, 9291, 9375, 9454, 9527, 9593, 9654, 9708, 9756, 9797, 9831, 9859, 9880, 9894, 9900, 9901, 9894, 9880, 9859, 9831, 9797, 9756, 9708, 9654, 9593, 9527, 9454, 9375, 9291, 9201, 9105, 9005, 8900, 8790, 8676, 8557, 8435, 8309, 8179, 8046, 7911, 7772, 7632, 7489, 7344, 7198, 7050, 6901, 6751, 6600, 6449, 6298, 6147, 5995, 5845, 5694, 5545, 5396, 5248, 5102, 4957, 4813, 4671, 4531, 4392, 4256, 4122, 3989, 3859, 3731, 3606, 3482, 3362, 3243, 3127, 3014, 2903, 2795, 2689, 2586, 2486, 2387, 2292, 2199, 2109, 2021, 1935, 1852, 1771, 1693, 1617, 1543, 1472, 1403, 1336, 1271, 1209, 1148, 1090, 1033, 979, 926, 875, 827, 779, 734, 691, 649, 608, 570, 532, 497, 463, 430, 399, 369, 340, 313, 287, 263, 239, 217, 196, 177, 158, 140, 124, 109, 95, 81, 69, 58, 48, 39, 31, 24, 17, 12, 8, 5, 2, 1, 1
+};
+
+uint16_t table_pos = 0;
+
+static THD_WORKING_AREA(waBreatheThread, 128);
+static THD_FUNCTION(BreatheThread, arg) {
+ (void)arg;
+ chRegSetThreadName("breatheThread");
+
+ while(!chThdShouldTerminateX()) {
+ pwmEnableChannel(&PWM_DRIVER, 0, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos]));
+ table_pos = (table_pos+1) % TABLE_SIZE;
+ chThdSleepMilliseconds(BREATHE_STEP);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Initialize the PWM driver.
+ */
+ pwmStart(&PWM_DRIVER, &pwmcfg);
+ pwmEnablePeriodicNotification(&PWM_DRIVER);
+
+ /*
+ * Starts the PWM channel 0; turn the LED off.
+ */
+ pwmEnableChannel(&PWM_DRIVER, 0, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER, 0));
+ pwmEnableChannelNotification(&PWM_DRIVER, 0); // MUST be before EnableChannel...
+
+ /*
+ * Create the breathe thread.
+ */
+ thread_t *breathe_thread_p;
+ breathe_thread_p = chThdCreateStatic(waBreatheThread, sizeof(waBreatheThread), NORMALPRIO, BreatheThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (!chThdShouldTerminateX()) {
+ chThdSleepMilliseconds(500);
+ }
+
+ chThdTerminate(breathe_thread_p);
+ chThdSleepMilliseconds(2*BREATHE_STEP);
+
+ /*
+ * Disables channel 0 and stops the drivers.
+ */
+ pwmDisableChannel(&PWM_DRIVER, 0);
+ pwmStop(&PWM_DRIVER);
+
+ return 0;
+}
diff --git a/testhal/KINETIS/MCHCK/PWM/mcuconf.h b/testhal/KINETIS/MCHCK/PWM/mcuconf.h new file mode 100644 index 0000000..6b69edb --- /dev/null +++ b/testhal/KINETIS/MCHCK/PWM/mcuconf.h @@ -0,0 +1,41 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 1
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
+
+/*
+ * PWM driver system settings.
+ */
+#define KINETIS_PWM_USE_FTM0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/Makefile b/testhal/KINETIS/MCHCK/USB_SERIAL/Makefile new file mode 100644 index 0000000..b3010a1 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/Makefile @@ -0,0 +1,225 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/MCHCK_K20/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+# Use BLDR4 for a 4k bootloader, BLDR3 for a 3k bootloader
+LDSCRIPT= $(STARTUPLD)/MK20DX128BLDR4.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ usbcfg.c \ + main.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c \ + $(CHIBIOS)/os/various/shell/shell.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various/shell $(CHIBIOS)/os/hal/lib/streams
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+# VTOR moved to after the bootloader; use 0x1000 for a 4k bootloader,
+# 0xc00 for a 3k bootloader
+UDEFS = -DCORTEX_VTOR_INIT=0x00001000
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/chconf.h b/testhal/KINETIS/MCHCK/USB_SERIAL/chconf.h new file mode 100644 index 0000000..7371b49 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/chconf.h @@ -0,0 +1,513 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/USB_SERIAL/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/chtsy.inf b/testhal/KINETIS/MCHCK/USB_SERIAL/chtsy.inf new file mode 100644 index 0000000..4ae7d0b --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/chtsy.inf @@ -0,0 +1,106 @@ +;************************************************************
+; Windows USB CDC ACM Setup File
+; Copyright (c) 2000 Microsoft Corporation
+
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%MFGNAME%
+LayoutFile=layout.inf
+CatalogFile=%MFGFILENAME%.cat
+DriverVer=11/15/2007,5.1.2600.0
+
+[Manufacturer]
+%MFGNAME%=DeviceList, NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP/Vista-32bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.nt]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.nt
+AddReg=DriverInstall.nt.AddReg
+
+[DriverCopyFiles.nt]
+usbser.sys,,,0x20
+
+[DriverInstall.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.nt.Services]
+AddService=usbser, 0x00000002, DriverService.nt
+
+[DriverService.nt]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+;------------------------------------------------------------------------------
+; Vista-64bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+%DRIVERFILENAME%.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+
+;------------------------------------------------------------------------------
+; Vendor and Product ID Definitions
+;------------------------------------------------------------------------------
+; When developing your USB device, the VID and PID used in the PC side
+; application program and the firmware on the microcontroller must match.
+; Modify the below line to use your VID and PID. Use the format as shown below.
+; Note: One INF file can be used for multiple devices with different VID and PIDs.
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
+;------------------------------------------------------------------------------
+[SourceDisksFiles]
+[SourceDisksNames]
+[DeviceList]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+[DeviceList.NTamd64]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+;Modify these strings to customize your device
+;------------------------------------------------------------------------------
+[Strings]
+MFGFILENAME="ChTsy"
+DRIVERFILENAME ="usbser"
+MFGNAME="NopeLab"
+INSTDISK="ChTsy CDC driver"
+DESCRIPTION="ChTsy CDC driver"
+SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/halconf.h b/testhal/KINETIS/MCHCK/USB_SERIAL/halconf.h new file mode 100644 index 0000000..466af01 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/halconf.h @@ -0,0 +1,362 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MCHCK/USB_SERIAL/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*
+ * @brief Enable debugging messages over SD1.
+ *
+ * @note Requires HAL_USE_SERIAL.
+ */
+#if HAL_USE_SERIAL
+#define DEBUG_USB
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/main.c b/testhal/KINETIS/MCHCK/USB_SERIAL/main.c new file mode 100644 index 0000000..62771c9 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/main.c @@ -0,0 +1,162 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "shell.h"
+#include "chprintf.h"
+
+#include "usbcfg.h"
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+
+/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/
+static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static uint8_t buf[] =
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: write\r\n");
+ return;
+ }
+
+ while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
+#if 1
+ /* Writing in channel mode.*/
+ chnWrite(&SDU1, buf, sizeof buf - 1);
+#else
+ /* Writing in buffer mode.*/
+ (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE);
+ memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE);
+ obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE);
+#endif
+ }
+ chprintf(chp, "\r\n\nstopped\r\n");
+}
+
+static const ShellCommand commands[] = {
+ {"write", cmd_write},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Generic code. */
+/*===========================================================================*/
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ systime_t time;
+
+ time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500;
+ palClearPad(GPIOB, GPIOB_LED);
+ chThdSleepMilliseconds(time);
+ palSetPad(GPIOB, GPIOB_LED);
+ chThdSleepMilliseconds(time);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1500);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, spawning shells.
+ */
+ while (true) {
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
+ "shell", NORMALPRIO + 1,
+ shellThread, (void *)&shell_cfg1);
+ chThdWait(shelltp); /* Waiting termination. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/mcuconf.h b/testhal/KINETIS/MCHCK/USB_SERIAL/mcuconf.h new file mode 100644 index 0000000..caf4228 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/mcuconf.h @@ -0,0 +1,49 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+
+#define KINETIS_NO_INIT FALSE
+
+/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1
+#define KINETIS_CLKDIV1_OUTDIV2 1
+#define KINETIS_CLKDIV1_OUTDIV4 2
+#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+
+#endif /* _MCUCONF_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c new file mode 100644 index 0000000..3093640 --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c @@ -0,0 +1,329 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+
+/*
+ * Endpoints to be used for USBD1.
+ */
+#define USBD1_DATA_REQUEST_EP 1
+#define USBD1_DATA_AVAILABLE_EP 1
+#define USBD1_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0179, /* idVendor. */
+ 0x0001, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(2+2*7), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'N', 0, 'o', 0, 'p', 0, 'e', 0, 'L', 0, 'a', 0, 'b', 0,
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(2+5*2), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'T', 0, 's', 0, 'y', 0,
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduDisconnectI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * Handles the USB driver global events.
+ */
+static void sof_handler(USBDriver *usbp) {
+
+ (void)usbp;
+
+ osalSysLockFromISR();
+ sduSOFHookI(&SDU1);
+ osalSysUnlockFromISR();
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ sof_handler
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD1,
+ USBD1_DATA_REQUEST_EP,
+ USBD1_DATA_AVAILABLE_EP,
+ USBD1_INTERRUPT_REQUEST_EP
+};
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.h b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.h new file mode 100644 index 0000000..5aa501e --- /dev/null +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.h @@ -0,0 +1,27 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+extern SerialUSBDriver SDU1;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/ADC/Makefile b/testhal/KINETIS/TEENSY3_x/ADC/Makefile new file mode 100644 index 0000000..c409898 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/ADC/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/ADC/chconf.h b/testhal/KINETIS/TEENSY3_x/ADC/chconf.h new file mode 100644 index 0000000..caae0c2 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/ADC/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/ADC/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/ADC/halconf.h b/testhal/KINETIS/TEENSY3_x/ADC/halconf.h new file mode 100644 index 0000000..ebc0331 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/ADC/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/ADC/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/ADC/main.c b/testhal/KINETIS/TEENSY3_x/ADC/main.c new file mode 100644 index 0000000..7a2dc3a --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/ADC/main.c @@ -0,0 +1,135 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define ADC_GRP1_NUM_CHANNELS 2
+#define ADC_GRP1_BUF_DEPTH 1
+
+static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
+static virtual_timer_t vt;
+
+static void ledoff(void *p) {
+
+ (void)p;
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static void adc_end_cb(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
+
+ (void)adcp;
+ (void)n;
+
+ /*
+ * The bandgap value represents the ADC reading for 1.0V
+ */
+ uint16_t sensor = buffer[0];
+ uint16_t bandgap = buffer[1];
+
+ /*
+ * The v25 value is the voltage reading at 25C, it comes from the ADC
+ * electricals table in the processor manual. V25 is in millivolts.
+ */
+ int32_t v25 = 716;
+
+ /*
+ * The m value is slope of the temperature sensor values, again from
+ * the ADC electricals table in the processor manual.
+ * M in microvolts per degree.
+ */
+ int32_t m = 1620;
+
+ /*
+ * Divide the temperature sensor reading by the bandgap to get
+ * the voltage for the ambient temperature in millivolts.
+ */
+ int32_t vamb = (sensor * 1000) / bandgap;
+
+ /*
+ * This formula comes from the reference manual.
+ * Temperature is in millidegrees C.
+ */
+ int32_t delta = (((vamb - v25) * 1000000) / m);
+ int32_t temp = 25000 - delta;
+
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chSysLockFromISR();
+ chVTResetI(&vt);
+ if (temp < 19000) {
+ chVTSetI(&vt, MS2ST(10), ledoff, NULL);
+ } else if (temp > 28000) {
+ chVTSetI(&vt, MS2ST(20), ledoff, NULL);
+ } else {
+ chVTSetI(&vt, MS2ST(40), ledoff, NULL);
+ }
+ chSysUnlockFromISR();
+}
+
+
+/*
+ * ADC conversion group.
+ * Mode: Linear buffer, 8 samples of 1 channel, SW triggered.
+ */
+static const ADCConversionGroup adcgrpcfg1 = {
+ false,
+ ADC_GRP1_NUM_CHANNELS,
+ adc_end_cb,
+ NULL,
+ ADC_TEMP_SENSOR | ADC_BANDGAP,
+ /* CFG1 Regiser - ADCCLK = SYSCLK / 16, 16 bits per sample */
+ ADCx_CFG1_ADIV(ADCx_CFG1_ADIV_DIV_8) |
+ ADCx_CFG1_ADICLK(ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2) |
+ ADCx_CFG1_MODE(ADCx_CFG1_MODE_16_BITS),
+ /* SC3 Register - Average 32 readings per sample */
+ ADCx_SC3_AVGE |
+ ADCx_SC3_AVGS(ADCx_SC3_AVGS_AVERAGE_32_SAMPLES)
+};
+
+static const ADCConfig adccfg1 = {
+ /* Perform initial calibration */
+ true
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the ADC1 driver.
+ */
+ adcStart(&ADCD1, &adccfg1);
+
+ while (!chThdShouldTerminateX()) {
+ /*
+ * ADC linear conversion.
+ */
+ adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH);
+
+ chThdSleepMilliseconds(1000);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/ADC/mcuconf.h b/testhal/KINETIS/TEENSY3_x/ADC/mcuconf.h new file mode 100644 index 0000000..eefa840 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/ADC/mcuconf.h @@ -0,0 +1,35 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * ADC driver system settings.
+ */
+#define KINETIS_ADC_USE_ADC0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile new file mode 100644 index 0000000..50a3187 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + eeprom.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile.3_0 b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile.3_0 new file mode 100644 index 0000000..6f8f396 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/Makefile.3_0 @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX128.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + eeprom.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/README.md b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/README.md new file mode 100644 index 0000000..7f01bac --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/README.md @@ -0,0 +1,8 @@ +# Teensy 3.0 EEPROM via FlexRAM example + +FlexRAM, which is present on K20x MCUs, is configured to EEPROM mode, so it behaves like EEPROM. The maximum available size is 2K, but explicitly using a smaller chunk enables wear-levelling and increases write endurance. + + +## Credits + +Most of the actual EEPROM code is from [PJRC/Teensyduino](https://www.pjrc.com/teensy/teensyduino.html).
\ No newline at end of file diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/chconf.h b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/chconf.h new file mode 100644 index 0000000..ea87df8 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/chconf.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/EEPROM_EMU/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.c b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.c new file mode 100644 index 0000000..c78b39f --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.c @@ -0,0 +1,300 @@ +/* + * Eeprom emulation for K20x chips. + * (c) 2015 flabbergast + * Most of the code is from PJRC/Teensyduino (license below) + */ + +/* Teensyduino Core Library + * http://www.pjrc.com/teensy/ + * Copyright (c) 2013 PJRC.COM, LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * 1. The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * 2. If the Software is incorporated into a build system that allows + * selection among a list of target devices, then similar target + * devices manufactured by PJRC.COM must be included in the list of + * target devices and selectable in the same manner. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "ch.h" +#include "hal.h" + +// The EEPROM is really RAM with a hardware-based backup system to +// flash memory. Selecting a smaller size EEPROM allows more wear +// leveling, for higher write endurance. If you edit this file, +// set this to the smallest size your application can use. Also, +// due to Freescale's implementation, writing 16 or 32 bit words +// (aligned to 2 or 4 byte boundaries) has twice the endurance +// compared to writing 8 bit bytes. +// +#define EEPROM_SIZE 32 + +// Writing unaligned 16 or 32 bit data is handled automatically when +// this is defined, but at a cost of extra code size. Without this, +// any unaligned write will cause a hard fault exception! If you're +// absolutely sure all 16 and 32 bit writes will be aligned, you can +// remove the extra unnecessary code. +// +#define HANDLE_UNALIGNED_WRITES + +// Minimum EEPROM Endurance +// ------------------------ +#if (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word + #define EEESIZE 0x33 +#elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word + #define EEESIZE 0x34 +#elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word + #define EEESIZE 0x35 +#elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word + #define EEESIZE 0x36 +#elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word + #define EEESIZE 0x37 +#elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word + #define EEESIZE 0x38 +#elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word + #define EEESIZE 0x39 +#endif + +void eeprom_initialize(void) +{ + uint32_t count=0; + uint16_t do_flash_cmd[] = { + 0xf06f, 0x037f, 0x7003, 0x7803, + 0xf013, 0x0f80, 0xd0fb, 0x4770}; + uint8_t status; + + if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) { + // FlexRAM is configured as traditional RAM + // We need to reconfigure for EEPROM usage + FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command + FTFL->FCCOB4 = EEESIZE; // EEPROM Size + FTFL->FCCOB5 = 0x03; // 0K for Dataflash, 32K for EEPROM backup + __disable_irq(); + // do_flash_cmd() must execute from RAM. Luckily the C syntax is simple... + (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT)); + __enable_irq(); + status = FTFL->FSTAT; + if (status & (FTFL_FSTAT_RDCOLERR|FTFL_FSTAT_ACCERR|FTFL_FSTAT_FPVIOL)) { + FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR|FTFL_FSTAT_ACCERR|FTFL_FSTAT_FPVIOL)); + return; // error + } + } + // wait for eeprom to become ready (is this really necessary?) + while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) { + if (++count > 20000) break; + } +} + +#define FlexRAM ((uint8_t *)0x14000000) + +uint8_t eeprom_read_byte(const uint8_t *addr) +{ + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return FlexRAM[offset]; +} + +uint16_t eeprom_read_word(const uint16_t *addr) +{ + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE-1) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return *(uint16_t *)(&FlexRAM[offset]); +} + +uint32_t eeprom_read_dword(const uint32_t *addr) +{ + uint32_t offset = (uint32_t)addr; + if (offset >= EEPROM_SIZE-3) return 0; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + return *(uint32_t *)(&FlexRAM[offset]); +} + +void eeprom_read_block(void *buf, const void *addr, uint32_t len) +{ + uint32_t offset = (uint32_t)addr; + uint8_t *dest = (uint8_t *)buf; + uint32_t end = offset + len; + + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (end > EEPROM_SIZE) end = EEPROM_SIZE; + while (offset < end) { + *dest++ = FlexRAM[offset++]; + } +} + +int eeprom_is_ready(void) +{ + return (FTFL->FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0; +} + +static void flexram_wait(void) +{ + while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) { + // TODO: timeout + } +} + +void eeprom_write_byte(uint8_t *addr, uint8_t value) +{ + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (FlexRAM[offset] != value) { + FlexRAM[offset] = value; + flexram_wait(); + } +} + +void eeprom_write_word(uint16_t *addr, uint16_t value) +{ + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE-1) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); +#ifdef HANDLE_UNALIGNED_WRITES + if ((offset & 1) == 0) { +#endif + if (*(uint16_t *)(&FlexRAM[offset]) != value) { + *(uint16_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + } +#ifdef HANDLE_UNALIGNED_WRITES + } else { + if (FlexRAM[offset] != value) { + FlexRAM[offset] = value; + flexram_wait(); + } + if (FlexRAM[offset + 1] != (value >> 8)) { + FlexRAM[offset + 1] = value >> 8; + flexram_wait(); + } + } +#endif +} + +void eeprom_write_dword(uint32_t *addr, uint32_t value) +{ + uint32_t offset = (uint32_t)addr; + + if (offset >= EEPROM_SIZE-3) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); +#ifdef HANDLE_UNALIGNED_WRITES + switch (offset & 3) { + case 0: +#endif + if (*(uint32_t *)(&FlexRAM[offset]) != value) { + *(uint32_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + } + return; +#ifdef HANDLE_UNALIGNED_WRITES + case 2: + if (*(uint16_t *)(&FlexRAM[offset]) != value) { + *(uint16_t *)(&FlexRAM[offset]) = value; + flexram_wait(); + } + if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) { + *(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16; + flexram_wait(); + } + return; + default: + if (FlexRAM[offset] != value) { + FlexRAM[offset] = value; + flexram_wait(); + } + if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) { + *(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8; + flexram_wait(); + } + if (FlexRAM[offset + 3] != (value >> 24)) { + FlexRAM[offset + 3] = value >> 24; + flexram_wait(); + } + } +#endif +} + +void eeprom_write_block(const void *buf, void *addr, uint32_t len) +{ + uint32_t offset = (uint32_t)addr; + const uint8_t *src = (const uint8_t *)buf; + + if (offset >= EEPROM_SIZE) return; + if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); + if (len >= EEPROM_SIZE) len = EEPROM_SIZE; + if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset; + while (len > 0) { + uint32_t lsb = offset & 3; + if (lsb == 0 && len >= 4) { + // write aligned 32 bits + uint32_t val32; + val32 = *src++; + val32 |= (*src++ << 8); + val32 |= (*src++ << 16); + val32 |= (*src++ << 24); + if (*(uint32_t *)(&FlexRAM[offset]) != val32) { + *(uint32_t *)(&FlexRAM[offset]) = val32; + flexram_wait(); + } + offset += 4; + len -= 4; + } else if ((lsb == 0 || lsb == 2) && len >= 2) { + // write aligned 16 bits + uint16_t val16; + val16 = *src++; + val16 |= (*src++ << 8); + if (*(uint16_t *)(&FlexRAM[offset]) != val16) { + *(uint16_t *)(&FlexRAM[offset]) = val16; + flexram_wait(); + } + offset += 2; + len -= 2; + } else { + // write 8 bits + uint8_t val8 = *src++; + if (FlexRAM[offset] != val8) { + FlexRAM[offset] = val8; + flexram_wait(); + } + offset++; + len--; + } + } +} + +/* +void do_flash_cmd(volatile uint8_t *fstat) +{ + *fstat = 0x80; + while ((*fstat & 0x80) == 0) ; // wait +} +00000000 <do_flash_cmd>: + 0: f06f 037f mvn.w r3, #127 ; 0x7f + 4: 7003 strb r3, [r0, #0] + 6: 7803 ldrb r3, [r0, #0] + 8: f013 0f80 tst.w r3, #128 ; 0x80 + c: d0fb beq.n 6 <do_flash_cmd+0x6> + e: 4770 bx lr +*/ diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.h b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.h new file mode 100644 index 0000000..1bd714e --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/eeprom.h @@ -0,0 +1,21 @@ +/* + * Eeprom emulation for K20x chips. + * (c) 2015 flabbergast + * Most of the code is from PJRC/Teensyduino (license in eeprom.c) + */ + +#ifndef _EEPROM_H_ +#define _EEPROM_H_ + +void eeprom_initialize(void); +int eeprom_is_ready(void); +uint8_t eeprom_read_byte(const uint8_t *addr); +uint16_t eeprom_read_word(const uint16_t *addr); +uint32_t eeprom_read_dword(const uint32_t *addr); +void eeprom_read_block(void *buf, const void *addr, uint32_t len); +void eeprom_write_byte(uint8_t *addr, uint8_t data); +void eeprom_write_word(uint16_t *addr, uint16_t value); +void eeprom_write_dword(uint32_t *addr, uint32_t value); +void eeprom_write_block(const void *buf, void *addr, uint32_t len); + +#endif /* _EEPROM_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/halconf.h b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/halconf.h new file mode 100644 index 0000000..5cc1b57 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/EEPROM_EMU/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/main.c b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/main.c new file mode 100644 index 0000000..e1ef889 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/main.c @@ -0,0 +1,77 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#include "eeprom.h"
+
+#define LED_GPIO TEENSY_PIN13_IOPORT
+#define LED_PIN TEENSY_PIN13
+
+uint8_t n_of_blinks;
+
+static THD_WORKING_AREA(waBlinkThread, 128);
+static THD_FUNCTION(BlinkThread, arg) {
+ (void)arg;
+ uint8_t i;
+
+ for(i=0; i<n_of_blinks; i++) {
+ palSetPad(LED_GPIO, LED_PIN);
+ chThdSleepMilliseconds(400);
+ palClearPad(LED_GPIO, LED_PIN);
+ chThdSleepMilliseconds(400);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ n_of_blinks = 0;
+
+ uint8_t *ee_addr = (uint8_t *)3;
+
+ eeprom_write_byte(ee_addr,5);
+ chThdSleepMilliseconds(500);
+
+ eeprom_write_byte(ee_addr,10);
+ chThdSleepMilliseconds(500);
+
+ n_of_blinks = eeprom_read_byte(ee_addr);
+
+ /*
+ * Create the blink thread.
+ */
+ chThdCreateStatic(waBlinkThread, sizeof(waBlinkThread), NORMALPRIO, BlinkThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while(TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/mcuconf.h b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/mcuconf.h new file mode 100644 index 0000000..d614644 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EEPROM_EMU/mcuconf.h @@ -0,0 +1,51 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* PEE mode - 48MHz system clock driven by (16 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 0
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/EXT/Makefile b/testhal/KINETIS/TEENSY3_x/EXT/Makefile new file mode 100644 index 0000000..c409898 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EXT/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/EXT/chconf.h b/testhal/KINETIS/TEENSY3_x/EXT/chconf.h new file mode 100644 index 0000000..0389bed --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EXT/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/EXT/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/EXT/halconf.h b/testhal/KINETIS/TEENSY3_x/EXT/halconf.h new file mode 100644 index 0000000..eba8b32 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EXT/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/EXT/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT TRUE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/EXT/main.c b/testhal/KINETIS/TEENSY3_x/EXT/main.c new file mode 100644 index 0000000..3903897 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EXT/main.c @@ -0,0 +1,74 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+static void ledoff(void *p) {
+
+ (void)p;
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static virtual_timer_t vt;
+
+/* Triggered when the Teensy's pin 12 (PC7) changes; The LED is set to ON.*/
+static void extcb1(EXTDriver *extp, expchannel_t channel) {
+ (void)extp;
+ (void)channel;
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chSysLockFromISR();
+ chVTResetI(&vt);
+ /* LED set to OFF after 500mS.*/
+ chVTSetI(&vt, MS2ST(500), ledoff, NULL);
+ chSysUnlockFromISR();
+}
+
+static const EXTConfig extcfg = {
+ {
+ {EXT_CH_MODE_BOTH_EDGES|EXT_CH_MODE_AUTOSTART, extcb1, PORTC, 7}
+ }
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the EXT driver 1.
+ */
+ extStart(&EXTD1, &extcfg);
+ /*
+ * Normal main() thread activity, in this demo it enables and disables the
+ * button EXT channel using 10 seconds intervals.
+ */
+ while (!chThdShouldTerminateX()) {
+ extChannelDisable(&EXTD1, 0);
+ chThdSleepMilliseconds(10000);
+ extChannelEnable(&EXTD1, 0);
+ chThdSleepMilliseconds(10000);
+ }
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/EXT/mcuconf.h b/testhal/KINETIS/TEENSY3_x/EXT/mcuconf.h new file mode 100644 index 0000000..147622e --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/EXT/mcuconf.h @@ -0,0 +1,47 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * EXT driver system settings.
+ */
+#define KINETIS_EXTI_NUM_CHANNELS 1
+#define KINETIS_EXT_PORTA_IRQ_PRIORITY 12
+#define KINETIS_EXT_PORTB_IRQ_PRIORITY 12
+#define KINETIS_EXT_PORTC_IRQ_PRIORITY 12
+#define KINETIS_EXT_PORTD_IRQ_PRIORITY 12
+#define KINETIS_EXT_PORTE_IRQ_PRIORITY 12
+
+/* K20 64pin */
+#define KINETIS_EXT_PORTA_WIDTH 20
+#define KINETIS_EXT_PORTB_WIDTH 20
+#define KINETIS_EXT_PORTC_WIDTH 12
+#define KINETIS_EXT_PORTD_WIDTH 8
+#define KINETIS_EXT_PORTE_WIDTH 2
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/GPT/Makefile b/testhal/KINETIS/TEENSY3_x/GPT/Makefile new file mode 100644 index 0000000..c409898 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/GPT/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/GPT/chconf.h b/testhal/KINETIS/TEENSY3_x/GPT/chconf.h new file mode 100644 index 0000000..b2ed194 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/GPT/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/GPT/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/GPT/halconf.h b/testhal/KINETIS/TEENSY3_x/GPT/halconf.h new file mode 100644 index 0000000..80de20c --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/GPT/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/GPT/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT TRUE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/GPT/main.c b/testhal/KINETIS/TEENSY3_x/GPT/main.c new file mode 100644 index 0000000..4609f37 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/GPT/main.c @@ -0,0 +1,65 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+/*
+ * GPT1 callback.
+ */
+static void gpt1cb(GPTDriver *gptp) {
+
+ (void)gptp;
+ palTogglePad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static const GPTConfig gpt1cfg = {
+ 10000, /* 10kHz timer clock.*/
+ gpt1cb /* Timer callback.*/
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the GPT driver 1.
+ */
+ gptStart(&GPTD1, &gpt1cfg);
+ gptStartContinuous(&GPTD1, 5000); /* 500ms */
+ //~ gptPolledDelay(&GPTD1, 10); /* Small delay.*/
+
+ /*
+ * Normal main() thread activity, it changes the GPT1 period every
+ * five seconds.
+ */
+ while (!chThdShouldTerminateX()) {
+ chThdSleepMilliseconds(5000);
+ gptChangeInterval(&GPTD1,gptGetIntervalX(&GPTD1)/2); /* 25ms */
+ chThdSleepMilliseconds(5000);
+ gptChangeInterval(&GPTD1,gptGetIntervalX(&GPTD1)*2); /* 50ms */
+ }
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/GPT/mcuconf.h b/testhal/KINETIS/TEENSY3_x/GPT/mcuconf.h new file mode 100644 index 0000000..bb2f8bf --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/GPT/mcuconf.h @@ -0,0 +1,35 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * GPT driver system settings.
+ */
+#define KINETIS_GPT_USE_PIT0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/PWM/Makefile b/testhal/KINETIS/TEENSY3_x/PWM/Makefile new file mode 100644 index 0000000..c409898 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/PWM/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/PWM/chconf.h b/testhal/KINETIS/TEENSY3_x/PWM/chconf.h new file mode 100644 index 0000000..dda26e1 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/PWM/chconf.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/PWM/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/PWM/halconf.h b/testhal/KINETIS/TEENSY3_x/PWM/halconf.h new file mode 100644 index 0000000..9cb0ac9 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/PWM/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/PWM/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/PWM/main.c b/testhal/KINETIS/TEENSY3_x/PWM/main.c new file mode 100644 index 0000000..bef46a2 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/PWM/main.c @@ -0,0 +1,116 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define PWM_DRIVER PWMD1
+
+static void pwmpcb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static void pwmc0cb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static PWMConfig pwmcfg = {
+ 24000000, /* 24MHz PWM clock frequency. */
+ 12000, /* Initial PWM period 1ms */
+ pwmpcb,
+ {
+ {PWM_OUTPUT_DISABLED, pwmc0cb},
+ {PWM_OUTPUT_DISABLED, NULL},
+ },
+};
+
+/* Breathing Sleep LED brighness(PWM On period) table
+ *
+ * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63
+ * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i }
+ */
+/* ruby -e "a = ((0..255).map{|x| Math.exp(Math.cos(Math::PI+(2*x*(Math::PI)/255)))-Math.exp(-1) }); m = a.max; a.map\!{|x| (9900*x/m).to_i+1}; p a" */
+#define BREATHE_STEP 16 /* ms; = 4000ms/TABLE_SIZE */
+#define TABLE_SIZE 256
+static const uint16_t breathing_table[TABLE_SIZE] = {
+ 1, 1, 2, 5, 8, 12, 17, 24, 31, 39, 48, 58, 69, 81, 95, 109, 124, 140, 158, 177, 196, 217, 239, 263, 287, 313, 340, 369, 399, 430, 463, 497, 532, 570, 608, 649, 691, 734, 779, 827, 875, 926, 979, 1033, 1090, 1148, 1209, 1271, 1336, 1403, 1472, 1543, 1617, 1693, 1771, 1852, 1935, 2021, 2109, 2199, 2292, 2387, 2486, 2586, 2689, 2795, 2903, 3014, 3127, 3243, 3362, 3482, 3606, 3731, 3859, 3989, 4122, 4256, 4392, 4531, 4671, 4813, 4957, 5102, 5248, 5396, 5545, 5694, 5845, 5995, 6147, 6298, 6449, 6600, 6751, 6901, 7050, 7198, 7344, 7489, 7632, 7772, 7911, 8046, 8179, 8309, 8435, 8557, 8676, 8790, 8900, 9005, 9105, 9201, 9291, 9375, 9454, 9527, 9593, 9654, 9708, 9756, 9797, 9831, 9859, 9880, 9894, 9900, 9901, 9894, 9880, 9859, 9831, 9797, 9756, 9708, 9654, 9593, 9527, 9454, 9375, 9291, 9201, 9105, 9005, 8900, 8790, 8676, 8557, 8435, 8309, 8179, 8046, 7911, 7772, 7632, 7489, 7344, 7198, 7050, 6901, 6751, 6600, 6449, 6298, 6147, 5995, 5845, 5694, 5545, 5396, 5248, 5102, 4957, 4813, 4671, 4531, 4392, 4256, 4122, 3989, 3859, 3731, 3606, 3482, 3362, 3243, 3127, 3014, 2903, 2795, 2689, 2586, 2486, 2387, 2292, 2199, 2109, 2021, 1935, 1852, 1771, 1693, 1617, 1543, 1472, 1403, 1336, 1271, 1209, 1148, 1090, 1033, 979, 926, 875, 827, 779, 734, 691, 649, 608, 570, 532, 497, 463, 430, 399, 369, 340, 313, 287, 263, 239, 217, 196, 177, 158, 140, 124, 109, 95, 81, 69, 58, 48, 39, 31, 24, 17, 12, 8, 5, 2, 1, 1
+};
+
+uint16_t table_pos = 0;
+
+static THD_WORKING_AREA(waBreatheThread, 128);
+static THD_FUNCTION(BreatheThread, arg) {
+ (void)arg;
+ chRegSetThreadName("breatheThread");
+
+ while(!chThdShouldTerminateX()) {
+ pwmEnableChannel(&PWM_DRIVER, 0, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos]));
+ table_pos = (table_pos+1) % TABLE_SIZE;
+ chThdSleepMilliseconds(BREATHE_STEP);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Initialize the PWM driver.
+ */
+ pwmStart(&PWM_DRIVER, &pwmcfg);
+ pwmEnablePeriodicNotification(&PWM_DRIVER);
+
+ /*
+ * Starts the PWM channel 0; turn the LED off.
+ */
+ pwmEnableChannel(&PWM_DRIVER, 0, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER, 0));
+ pwmEnableChannelNotification(&PWM_DRIVER, 0); // MUST be before EnableChannel...
+
+ /*
+ * Create the breathe thread.
+ */
+ thread_t *breathe_thread_p;
+ breathe_thread_p = chThdCreateStatic(waBreatheThread, sizeof(waBreatheThread), NORMALPRIO, BreatheThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (!chThdShouldTerminateX()) {
+ chThdSleepMilliseconds(500);
+ }
+
+ chThdTerminate(breathe_thread_p);
+ chThdSleepMilliseconds(2*BREATHE_STEP);
+
+ /*
+ * Disables channel 0 and stops the drivers.
+ */
+ pwmDisableChannel(&PWM_DRIVER, 0);
+ pwmStop(&PWM_DRIVER);
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/PWM/mcuconf.h b/testhal/KINETIS/TEENSY3_x/PWM/mcuconf.h new file mode 100644 index 0000000..9f087dd --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/PWM/mcuconf.h @@ -0,0 +1,35 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * PWM driver system settings.
+ */
+#define KINETIS_PWM_USE_FTM0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile b/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile new file mode 100644 index 0000000..c409898 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX256.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile.3_0 b/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile.3_0 new file mode 100644 index 0000000..5553571 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/Makefile.3_0 @@ -0,0 +1,217 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MK20DX128.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/chconf.h b/testhal/KINETIS/TEENSY3_x/SERIAL/chconf.h new file mode 100644 index 0000000..95b505a --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/SERIAL/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/halconf.h b/testhal/KINETIS/TEENSY3_x/SERIAL/halconf.h new file mode 100644 index 0000000..6c7a97d --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/SERIAL/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/main.c b/testhal/KINETIS/TEENSY3_x/SERIAL/main.c new file mode 100644 index 0000000..722a398 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/main.c @@ -0,0 +1,81 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+static THD_WORKING_AREA(waSerEcho, 128);
+static THD_FUNCTION(thSerEcho, arg)
+{
+ (void)arg;
+ chRegSetThreadName("SerEcho");
+ event_listener_t elSerData;
+ eventflags_t flags;
+ chEvtRegisterMask((event_source_t *)chnGetEventSource(&SD1), &elSerData, EVENT_MASK(1));
+
+ while (!chThdShouldTerminateX())
+ {
+ chEvtWaitOneTimeout(EVENT_MASK(1), MS2ST(10));
+ flags = chEvtGetAndClearFlags(&elSerData);
+ if (flags & CHN_INPUT_AVAILABLE)
+ {
+ msg_t charbuf;
+ do
+ {
+ charbuf = chnGetTimeout(&SD1, TIME_IMMEDIATE);
+ if ( charbuf != Q_TIMEOUT )
+ {
+ streamPut(&SD1, charbuf);
+ }
+ }
+ while (charbuf != Q_TIMEOUT);
+ }
+ }
+}
+
+SerialConfig s0cfg =
+{
+ 19200
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates serial 1 (UART0) using the driver default configuration.
+ */
+ sdStart(&SD1, &s0cfg);
+
+ chThdCreateStatic(waSerEcho, sizeof(waSerEcho), NORMALPRIO, thSerEcho, NULL);
+
+ while (!chThdShouldTerminateX()) {
+ chThdSleepMilliseconds(1000);
+ palTogglePad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ sdPut(&SD1,'B');
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY3_x/SERIAL/mcuconf.h b/testhal/KINETIS/TEENSY3_x/SERIAL/mcuconf.h new file mode 100644 index 0000000..919719b --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/SERIAL/mcuconf.h @@ -0,0 +1,35 @@ +/*
+ ChibiOS - (C) 2015 RedoX https://github.com/RedoXyde
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile new file mode 100644 index 0000000..32688b5 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile @@ -0,0 +1,222 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3_1/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MK20DX256.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ usbcfg.c \ + main.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c \ + $(CHIBIOS)/os/various/shell/shell.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various/shell $(CHIBIOS)/os/hal/lib/streams
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile.3_0 b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile.3_0 new file mode 100644 index 0000000..87c6d9f --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/Makefile.3_0 @@ -0,0 +1,222 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_3/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ usbcfg.c \ + main.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ $(CHIBIOS)/os/various/shell/shell_cmd.c \ + $(CHIBIOS)/os/various/shell/shell.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various/shell $(CHIBIOS)/os/hal/lib/streams
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chconf.h b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chconf.h new file mode 100644 index 0000000..7d9ace3 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chconf.h @@ -0,0 +1,513 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/USB_SERIAL/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chtsy.inf b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chtsy.inf new file mode 100644 index 0000000..4ae7d0b --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/chtsy.inf @@ -0,0 +1,106 @@ +;************************************************************
+; Windows USB CDC ACM Setup File
+; Copyright (c) 2000 Microsoft Corporation
+
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%MFGNAME%
+LayoutFile=layout.inf
+CatalogFile=%MFGFILENAME%.cat
+DriverVer=11/15/2007,5.1.2600.0
+
+[Manufacturer]
+%MFGNAME%=DeviceList, NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP/Vista-32bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.nt]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.nt
+AddReg=DriverInstall.nt.AddReg
+
+[DriverCopyFiles.nt]
+usbser.sys,,,0x20
+
+[DriverInstall.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.nt.Services]
+AddService=usbser, 0x00000002, DriverService.nt
+
+[DriverService.nt]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+;------------------------------------------------------------------------------
+; Vista-64bit Sections
+;------------------------------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+%DRIVERFILENAME%.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%SERVICE%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\%DRIVERFILENAME%.sys
+
+
+;------------------------------------------------------------------------------
+; Vendor and Product ID Definitions
+;------------------------------------------------------------------------------
+; When developing your USB device, the VID and PID used in the PC side
+; application program and the firmware on the microcontroller must match.
+; Modify the below line to use your VID and PID. Use the format as shown below.
+; Note: One INF file can be used for multiple devices with different VID and PIDs.
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
+;------------------------------------------------------------------------------
+[SourceDisksFiles]
+[SourceDisksNames]
+[DeviceList]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+[DeviceList.NTamd64]
+%DESCRIPTION%=DriverInstall, USB\VID_0179&PID_0001
+
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+;Modify these strings to customize your device
+;------------------------------------------------------------------------------
+[Strings]
+MFGFILENAME="ChTsy"
+DRIVERFILENAME ="usbser"
+MFGNAME="NopeLab"
+INSTDISK="ChTsy CDC driver"
+DESCRIPTION="ChTsy CDC driver"
+SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/halconf.h b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/halconf.h new file mode 100644 index 0000000..329f831 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/halconf.h @@ -0,0 +1,353 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY3_x/USB_SERIAL/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/main.c b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/main.c new file mode 100644 index 0000000..3553c6b --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/main.c @@ -0,0 +1,162 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "shell.h"
+#include "chprintf.h"
+
+#include "usbcfg.h"
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+
+/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/
+static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static uint8_t buf[] =
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
+ "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: write\r\n");
+ return;
+ }
+
+ while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
+#if 1
+ /* Writing in channel mode.*/
+ chnWrite(&SDU1, buf, sizeof buf - 1);
+#else
+ /* Writing in buffer mode.*/
+ (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE);
+ memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE);
+ obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE);
+#endif
+ }
+ chprintf(chp, "\r\n\nstopped\r\n");
+}
+
+static const ShellCommand commands[] = {
+ {"write", cmd_write},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Generic code. */
+/*===========================================================================*/
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ systime_t time;
+
+ time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500;
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chThdSleepMilliseconds(time);
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chThdSleepMilliseconds(time);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1500);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, spawning shells.
+ */
+ while (true) {
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
+ "shell", NORMALPRIO + 1,
+ shellThread, (void *)&shell_cfg1);
+ chThdWait(shelltp); /* Waiting termination. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/mcuconf.h b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/mcuconf.h new file mode 100644 index 0000000..59e1e82 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/mcuconf.h @@ -0,0 +1,40 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+/* PEE mode - 48MHz system clock driven by external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+
+#endif /* _MCUCONF_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c new file mode 100644 index 0000000..3093640 --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c @@ -0,0 +1,329 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+
+/*
+ * Endpoints to be used for USBD1.
+ */
+#define USBD1_DATA_REQUEST_EP 1
+#define USBD1_DATA_AVAILABLE_EP 1
+#define USBD1_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0179, /* idVendor. */
+ 0x0001, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(2+2*7), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'N', 0, 'o', 0, 'p', 0, 'e', 0, 'L', 0, 'a', 0, 'b', 0,
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(2+5*2), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'T', 0, 's', 0, 'y', 0,
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduDisconnectI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * Handles the USB driver global events.
+ */
+static void sof_handler(USBDriver *usbp) {
+
+ (void)usbp;
+
+ osalSysLockFromISR();
+ sduSOFHookI(&SDU1);
+ osalSysUnlockFromISR();
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ sof_handler
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD1,
+ USBD1_DATA_REQUEST_EP,
+ USBD1_DATA_AVAILABLE_EP,
+ USBD1_INTERRUPT_REQUEST_EP
+};
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.h b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.h new file mode 100644 index 0000000..5aa501e --- /dev/null +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.h @@ -0,0 +1,27 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+ Based on ChibiOS USB_CDC demo - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+extern SerialUSBDriver SDU1;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/I2C/Makefile b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/Makefile index 9935923..7a3b78a 100644 --- a/testhal/KINETIS/I2C/Makefile +++ b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/Makefile @@ -1,206 +1,211 @@ -##############################################################################
-# Build global options
-# NOTE: Can be overridden externally.
-#
-
-# Compiler options here.
-ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -DCRT0_INIT_STACKS=0
-# USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
-endif
-
-# C specific options here (added to USE_OPT).
-ifeq ($(USE_COPT),)
- USE_COPT =
-endif
-
-# C++ specific options here (added to USE_OPT).
-ifeq ($(USE_CPPOPT),)
- USE_CPPOPT = -fno-rtti
-endif
-
-# Enable this if you want the linker to remove unused code and data
-ifeq ($(USE_LINK_GC),)
- USE_LINK_GC = yes
-endif
-
-# Linker extra options here.
-ifeq ($(USE_LDOPT),)
- USE_LDOPT =
-endif
-
-# Enable this if you want link time optimizations (LTO)
-ifeq ($(USE_LTO),)
- USE_LTO = no
-endif
-
-# If enabled, this option allows to compile the application in THUMB mode.
-ifeq ($(USE_THUMB),)
- USE_THUMB = yes
-endif
-
-# Enable this if you want to see the full log while compiling.
-ifeq ($(USE_VERBOSE_COMPILE),)
- USE_VERBOSE_COMPILE = no
-endif
-
-# If enabled, this option makes the build process faster by not compiling
-# modules not used in the current configuration.
-ifeq ($(USE_SMART_BUILD),)
- USE_SMART_BUILD = yes
-endif
-
-#
-# Build global options
-##############################################################################
-
-##############################################################################
-# Architecture or project specific options
-#
-
-# Stack size to be allocated to the Cortex-M process stack. This stack is
-# the stack used by the main() thread.
-ifeq ($(USE_PROCESS_STACKSIZE),)
- USE_PROCESS_STACKSIZE = 0x200
-endif
-
-# Stack size to the allocated to the Cortex-M main/exceptions stack. This
-# stack is used for processing interrupts and exceptions.
-ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
- USE_EXCEPTIONS_STACKSIZE = 0x400
-endif
-
-#
-# Architecture or project specific options
-##############################################################################
-
-##############################################################################
-# Project, sources and paths
-#
-
-# Define project name here
-PROJECT = ch
-
-# Imported source files and paths
-CHIBIOS = ../../..
-include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
-include $(CHIBIOS)/os/hal/hal.mk
-include $(CHIBIOS)/os/hal/ports/KINETIS/K20x/platform.mk
-include $(CHIBIOS)/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
-include $(CHIBIOS)/os/hal/osal/rt/osal.mk
-include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
-
-# Define linker script file here
-LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
-
-# C sources that can be compiled in ARM or THUMB mode depending on the global
-# setting.
-CSRC = $(STARTUPSRC) \
- $(KERNSRC) \
- $(PORTSRC) \
- $(OSALSRC) \
- $(HALSRC) \
- $(PLATFORMSRC) \
- $(BOARDSRC) \
- main.c
-
-# C++ sources that can be compiled in ARM or THUMB mode depending on the global
-# setting.
-CPPSRC =
-
-# C sources to be compiled in ARM mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-ACSRC =
-
-# C++ sources to be compiled in ARM mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-ACPPSRC =
-
-# C sources to be compiled in THUMB mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-TCSRC =
-
-# C sources to be compiled in THUMB mode regardless of the global setting.
-# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
-# option that results in lower performance and larger code size.
-TCPPSRC =
-
-# List ASM source files here
-ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
-
-INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
- $(HALINC) $(PLATFORMINC) $(BOARDINC) \
- $(CHIBIOS)/os/various
-
-#
-# Project, sources and paths
-##############################################################################
-
-##############################################################################
-# Compiler settings
-#
-
-MCU = cortex-m4
-
-#TRGT = arm-elf-
-TRGT = arm-none-eabi-
-CC = $(TRGT)gcc
-CPPC = $(TRGT)g++
-# Enable loading with g++ only if you need C++ runtime support.
-# NOTE: You can use C++ even without C++ support if you are careful. C++
-# runtime support makes code size explode.
-LD = $(TRGT)gcc
-#LD = $(TRGT)g++
-CP = $(TRGT)objcopy
-AS = $(TRGT)gcc -x assembler-with-cpp
-OD = $(TRGT)objdump
-SZ = $(TRGT)size
-HEX = $(CP) -O ihex
-BIN = $(CP) -O binary
-SREC = $(CP) -O srec
-
-# ARM-specific options here
-AOPT =
-
-# THUMB-specific options here
-TOPT = -mthumb -DTHUMB
-
-# Define C warning options here
-CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
-
-# Define C++ warning options here
-CPPWARN = -Wall -Wextra -Wundef
-
-#
-# Compiler settings
-##############################################################################
-
-##############################################################################
-# Start of user section
-#
-
-# List all user C define here, like -D_DEBUG=1
-UDEFS =
-
-# Define ASM defines here
-UADEFS =
-
-# List all user directories here
-UINCDIR =
-
-# List the user directory to look for the libraries here
-ULIBDIR =
-
-# List all user libraries here
-ULIBS =
-
-#
-# End of user defines
-##############################################################################
-
-RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
-include $(RULESPATH)/rules.mk
+############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_LC/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MKL26Z64.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY_LC/BOOTLOADER/chconf.h b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/chconf.h new file mode 100644 index 0000000..d6a7bf8 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/BOOTLOADER/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/BOOTLOADER/halconf.h b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/halconf.h new file mode 100644 index 0000000..bd1d2a3 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/BOOTLOADER/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/BOOTLOADER/main.c b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/main.c new file mode 100644 index 0000000..d2c50e6 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/main.c @@ -0,0 +1,103 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define BTN_GPIO TEENSY_PIN2_IOPORT
+#define BTN_PIN TEENSY_PIN2
+
+/*
+ * Jump to bootloader on ARM Teensies.
+ */
+
+static void jump_to_bootloader(void) {
+ /* __asm__ volatile("bkpt"); */
+ /* Same as above, CMSIS notation: */
+ __BKPT(0);
+}
+
+/*
+ * Blink thread.
+ */
+
+static THD_WORKING_AREA(waBlinkThread, 128);
+static THD_FUNCTION(BlinkThread, arg) {
+ (void)arg;
+ uint8_t i;
+
+ // while(TRUE) {
+ for(i=0; i<5; i++) {
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chThdSleepMilliseconds(700);
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+ chThdSleepMilliseconds(700);
+ }
+ jump_to_bootloader();
+}
+
+/*
+ * Button thread.
+ */
+
+static THD_WORKING_AREA(waButtonThread, 128);
+static THD_FUNCTION(ButtonThread, arg) {
+ (void)arg;
+
+ while(TRUE) {
+ if(palReadPad(BTN_GPIO, BTN_PIN) == PAL_LOW) {
+ jump_to_bootloader();
+ }
+ chThdSleepMilliseconds(50);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Button init.
+ */
+ palSetPadMode(BTN_GPIO, BTN_PIN, PAL_MODE_INPUT_PULLUP);
+
+ /*
+ * Create the blink thread.
+ */
+ chThdCreateStatic(waBlinkThread, sizeof(waBlinkThread), NORMALPRIO, BlinkThread, NULL);
+
+ /*
+ * Create the button thread.
+ */
+ chThdCreateStatic(waButtonThread, sizeof(waButtonThread), NORMALPRIO, ButtonThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while(TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY_LC/BOOTLOADER/mcuconf.h b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/mcuconf.h new file mode 100644 index 0000000..58a15b3 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/BOOTLOADER/mcuconf.h @@ -0,0 +1,53 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* PEE mode - 48MHz system clock driven by (16 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 0
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/MKL26Z64.ld b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/MKL26Z64.ld new file mode 100644 index 0000000..befc463 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/MKL26Z64.ld @@ -0,0 +1,60 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * KL25Z64 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0xc0
+ flashcfg : org = 0x00000400, len = 0x10
+ flash : org = 0x00000410, len = 62k - 0x410
+ eeprom_emu : org = 0x0000F800, len = 2k
+ ram0 : org = 0x1FFFF800, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+__eeprom_workarea_start__ = ORIGIN(eeprom_emu);
+__eeprom_workarea_size__ = LENGTH(eeprom_emu);
+__eeprom_workarea_end__ = __eeprom_workarea_start__ + __eeprom_workarea_size__;
+
+INCLUDE rules_kinetis.ld
diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/Makefile b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/Makefile new file mode 100644 index 0000000..ada2fa4 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/Makefile @@ -0,0 +1,212 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_LC/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT = MKL26Z64.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + eeprom.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/README.md b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/README.md new file mode 100644 index 0000000..5e11bd1 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/README.md @@ -0,0 +1,7 @@ +# Teensy LC EEPROM emulation example + +This example emulates 128 bytes of EEPROM, using 2K of flash. Some wear-levelling is done (see comments in `eeprom.c`). + +## Credits + +Most of the actual EEPROM code is from [PJRC/Teensyduino](https://www.pjrc.com/teensy/teensyduino.html). diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/chconf.h b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/chconf.h new file mode 100644 index 0000000..919e2b0 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/EEPROM_EMU/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.c b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.c new file mode 100644 index 0000000..05ee313 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.c @@ -0,0 +1,241 @@ +/* + * Eeprom emulation for KL2x chips. + * (c) 2015 flabbergast + * Most of the code is from PJRC/Teensyduino (license below) + * + * Notes: Some wear-levelling is done: + * - emulating 128 bytes of eeprom; i.e. 7 bit "eeprom addresses" + * - using 2048 bytes of flash + * - new values are written consecutively into flash + * as 16bit ("eeprom address",value) pairs + * - if all 2048 bytes of flash is used, it is erased and writes + * start from the beginning again + * - the 2048 bytes of flash used are at the end of the flash + * - BEWARE: there is no protection! Use a custom .ld script + * to make sure this area is never used for code! + */ + +/* Teensyduino Core Library + * http://www.pjrc.com/teensy/ + * Copyright (c) 2013 PJRC.COM, LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * 1. The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * 2. If the Software is incorporated into a build system that allows + * selection among a list of target devices, then similar target + * devices manufactured by PJRC.COM must be included in the list of + * target devices and selectable in the same manner. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "ch.h" +#include "hal.h" + +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +extern uint32_t __eeprom_workarea_start__; +extern uint32_t __eeprom_workarea_end__; + +#define EEPROM_SIZE 128 + +static uint32_t flashend = 0; + +void eeprom_initialize(void) +{ + const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); + + do { + if (*p++ == 0xFFFF) { + flashend = (uint32_t)(p - 2); + return; + } + } while (p < (uint16_t *)SYMVAL(__eeprom_workarea_end__)); + flashend = (uint32_t)((uint16_t *)SYMVAL(__eeprom_workarea_end__) - 1); +} + +uint8_t eeprom_read_byte(const uint8_t *addr) +{ + uint32_t offset = (uint32_t)addr; + const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); + const uint16_t *end = (const uint16_t *)((uint32_t)flashend); + uint16_t val; + uint8_t data=0xFF; + + if (!end) { + eeprom_initialize(); + end = (const uint16_t *)((uint32_t)flashend); + } + if (offset < EEPROM_SIZE) { + while (p <= end) { + val = *p++; + if ((val & 255) == offset) data = val >> 8; + } + } + return data; +} + +static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data) +{ + // with great power comes great responsibility.... + uint32_t stat; + *(uint32_t *)&(FTFA->FCCOB3) = 0x06000000 | (addr & 0x00FFFFFC); + *(uint32_t *)&(FTFA->FCCOB7) = data; + __disable_irq(); + (*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&(FTFA->FSTAT)); + __enable_irq(); + stat = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR|FTFA_FSTAT_ACCERR|FTFA_FSTAT_FPVIOL); + if (stat) { + FTFA->FSTAT = stat; + } + MCM->PLACR |= MCM_PLACR_CFCC; +} + +void eeprom_write_byte(uint8_t *addr, uint8_t data) +{ + uint32_t offset = (uint32_t)addr; + const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend); + uint32_t i, val, flashaddr; + uint16_t do_flash_cmd[] = { + 0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770}; + uint8_t buf[EEPROM_SIZE]; + + if (offset >= EEPROM_SIZE) return; + if (!end) { + eeprom_initialize(); + end = (const uint16_t *)((uint32_t)flashend); + } + if (++end < (uint16_t *)SYMVAL(__eeprom_workarea_end__)) { + val = (data << 8) | offset; + flashaddr = (uint32_t)end; + flashend = flashaddr; + if ((flashaddr & 2) == 0) { + val |= 0xFFFF0000; + } else { + val <<= 16; + val |= 0x0000FFFF; + } + flash_write(do_flash_cmd, flashaddr, val); + } else { + for (i=0; i < EEPROM_SIZE; i++) { + buf[i] = 0xFF; + } + for (p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); p < (uint16_t *)SYMVAL(__eeprom_workarea_end__); p++) { + val = *p; + if ((val & 255) < EEPROM_SIZE) { + buf[val & 255] = val >> 8; + } + } + buf[offset] = data; + for (flashaddr=(uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); flashaddr < (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_end__); flashaddr += 1024) { + *(uint32_t *)&(FTFA->FCCOB3) = 0x09000000 | flashaddr; + __disable_irq(); + (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFA->FSTAT)); + __enable_irq(); + val = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR|FTFA_FSTAT_ACCERR|FTFA_FSTAT_FPVIOL);; + if (val) FTFA->FSTAT = val; + MCM->PLACR |= MCM_PLACR_CFCC; + } + flashaddr=(uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); + for (i=0; i < EEPROM_SIZE; i++) { + if (buf[i] == 0xFF) continue; + if ((flashaddr & 2) == 0) { + val = (buf[i] << 8) | i; + } else { + val = val | (buf[i] << 24) | (i << 16); + flash_write(do_flash_cmd, flashaddr, val); + } + flashaddr += 2; + } + flashend = flashaddr; + if ((flashaddr & 2)) { + val |= 0xFFFF0000; + flash_write(do_flash_cmd, flashaddr, val); + } + } +} + +/* +void do_flash_cmd(volatile uint8_t *fstat) +{ + *fstat = 0x80; + while ((*fstat & 0x80) == 0) ; // wait +} +00000000 <do_flash_cmd>: + 0: 2380 movs r3, #128 ; 0x80 + 2: 7003 strb r3, [r0, #0] + 4: 7803 ldrb r3, [r0, #0] + 6: b25b sxtb r3, r3 + 8: 2b00 cmp r3, #0 + a: dafb bge.n 4 <do_flash_cmd+0x4> + c: 4770 bx lr +*/ + + +uint16_t eeprom_read_word(const uint16_t *addr) +{ + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8); +} + +uint32_t eeprom_read_dword(const uint32_t *addr) +{ + const uint8_t *p = (const uint8_t *)addr; + return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8) + | (eeprom_read_byte(p+2) << 16) | (eeprom_read_byte(p+3) << 24); +} + +void eeprom_read_block(void *buf, const void *addr, uint32_t len) +{ + const uint8_t *p = (const uint8_t *)addr; + uint8_t *dest = (uint8_t *)buf; + while (len--) { + *dest++ = eeprom_read_byte(p++); + } +} + +int eeprom_is_ready(void) +{ + return 1; +} + +void eeprom_write_word(uint16_t *addr, uint16_t value) +{ + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p, value >> 8); +} + +void eeprom_write_dword(uint32_t *addr, uint32_t value) +{ + uint8_t *p = (uint8_t *)addr; + eeprom_write_byte(p++, value); + eeprom_write_byte(p++, value >> 8); + eeprom_write_byte(p++, value >> 16); + eeprom_write_byte(p, value >> 24); +} + +void eeprom_write_block(const void *buf, void *addr, uint32_t len) +{ + uint8_t *p = (uint8_t *)addr; + const uint8_t *src = (const uint8_t *)buf; + while (len--) { + eeprom_write_byte(p++, *src++); + } +} diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.h b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.h new file mode 100644 index 0000000..74cf07b --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/eeprom.h @@ -0,0 +1,21 @@ +/* + * Eeprom emulation for KL2x chips. + * (c) 2015 flabbergast + * Most of the code is from PJRC/Teensyduino (license in eeprom.c) + */ + +#ifndef _EEPROM_H_ +#define _EEPROM_H_ + +void eeprom_initialize(void); +int eeprom_is_ready(void); +uint8_t eeprom_read_byte(const uint8_t *addr); +uint16_t eeprom_read_word(const uint16_t *addr); +uint32_t eeprom_read_dword(const uint32_t *addr); +void eeprom_read_block(void *buf, const void *addr, uint32_t len); +void eeprom_write_byte(uint8_t *addr, uint8_t data); +void eeprom_write_word(uint16_t *addr, uint16_t value); +void eeprom_write_dword(uint32_t *addr, uint32_t value); +void eeprom_write_block(const void *buf, void *addr, uint32_t len); + +#endif /* _EEPROM_H_ */
\ No newline at end of file diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/halconf.h b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/halconf.h new file mode 100644 index 0000000..278db95 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/EEPROM_EMU/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/main.c b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/main.c new file mode 100644 index 0000000..c827944 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/main.c @@ -0,0 +1,78 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#include "eeprom.h"
+
+#define LED_GPIO TEENSY_PIN13_IOPORT
+#define LED_PIN TEENSY_PIN13
+
+uint8_t n_of_blinks;
+
+static THD_WORKING_AREA(waBlinkThread, 128);
+static THD_FUNCTION(BlinkThread, arg) {
+ (void)arg;
+ uint8_t i;
+
+ for(i=0; i<n_of_blinks; i++) {
+ palSetPad(LED_GPIO, LED_PIN);
+ chThdSleepMilliseconds(300);
+ palClearPad(LED_GPIO, LED_PIN);
+ chThdSleepMilliseconds(300);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ n_of_blinks = 0;
+
+ uint8_t *ee_addr = (uint8_t *)3;
+
+ eeprom_write_byte(ee_addr,5);
+ chThdSleepMilliseconds(500);
+
+ eeprom_write_byte(ee_addr,10);
+ chThdSleepMilliseconds(500);
+
+ n_of_blinks = eeprom_read_byte(ee_addr);
+
+ /*
+ * Create the blink thread.
+ */
+ chThdCreateStatic(waBlinkThread, sizeof(waBlinkThread), NORMALPRIO, BlinkThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while(TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/mcuconf.h b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/mcuconf.h new file mode 100644 index 0000000..58a15b3 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/mcuconf.h @@ -0,0 +1,53 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* PEE mode - 48MHz system clock driven by (16 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 0
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/rules_kinetis.ld index d566d82..6b46ed2 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/KL25Z128.ld +++ b/testhal/KINETIS/TEENSY_LC/EEPROM_EMU/rules_kinetis.ld @@ -1,42 +1,21 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
+ This file is part of ChibiOS.
- http://www.apache.org/licenses/LICENSE-2.0
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * KL25Z128 memory setup.
- */
-MEMORY
-{
- flash0 : org = 0x00000000, len = 0x100
- flashcfg : org = 0x00000400, len = 0x10
- flash : org = 0x00000410, len = 128k - 0x410
- ram0 : org = 0x1FFFF000, len = 16k
- ram1 : org = 0x00000000, len = 0
- ram2 : org = 0x00000000, len = 0
- ram3 : org = 0x00000000, len = 0
- ram4 : org = 0x00000000, len = 0
- ram5 : org = 0x00000000, len = 0
- ram6 : org = 0x00000000, len = 0
- ram7 : org = 0x00000000, len = 0
-}
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
-REGION_ALIAS("DATA_RAM", ram0);
-REGION_ALIAS("BSS_RAM", ram0);
-REGION_ALIAS("HEAP_RAM", ram0);
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
__ram0_start__ = ORIGIN(ram0);
__ram0_size__ = LENGTH(ram0);
@@ -69,7 +48,7 @@ SECTIONS {
. = 0;
- startup : ALIGN(16) SUBALIGN(16)
+ .isr : ALIGN(4) SUBALIGN(4)
{
KEEP(*(.vectors))
} > flash0
@@ -184,7 +163,7 @@ SECTIONS . = ALIGN(4);
_bss_end = .;
PROVIDE(end = .);
- } > BSS_RAM
+ } > BSS_RAM
.ram0_init : ALIGN(4)
{
diff --git a/testhal/KINETIS/TEENSY_LC/PWM/Makefile b/testhal/KINETIS/TEENSY_LC/PWM/Makefile new file mode 100644 index 0000000..fc9ec80 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/PWM/Makefile @@ -0,0 +1,212 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x200 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/PJRC_TEENSY_LC/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/MKL26Z64.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/KINETIS/TEENSY_LC/PWM/chconf.h b/testhal/KINETIS/TEENSY_LC/PWM/chconf.h new file mode 100644 index 0000000..b18de54 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/PWM/chconf.h @@ -0,0 +1,514 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/PWM/chconf.h
+ * @brief Configuration file.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+#define _CHIBIOS_RT_CONF_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 20
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/PWM/halconf.h b/testhal/KINETIS/TEENSY_LC/PWM/halconf.h new file mode 100644 index 0000000..9cbb6b9 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/PWM/halconf.h @@ -0,0 +1,187 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file TEENSY_LC/PWM/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/KINETIS/TEENSY_LC/PWM/main.c b/testhal/KINETIS/TEENSY_LC/PWM/main.c new file mode 100644 index 0000000..b366e9e --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/PWM/main.c @@ -0,0 +1,120 @@ +/*
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#define PWM_DRIVER PWMD1
+
+static void pwmpcb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palSetPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static void pwmc0cb(PWMDriver *pwmp) {
+ (void)pwmp;
+ palClearPad(TEENSY_PIN13_IOPORT, TEENSY_PIN13);
+}
+
+static PWMConfig pwmcfg = {
+ 12000000, /* 12MHz PWM clock frequency. */
+ 12000, /* Initial PWM period 1ms */
+ pwmpcb, /* Callback on counter overflow */
+ {
+ {PWM_OUTPUT_DISABLED, pwmc0cb}, /* ch2: mode, callback! */
+ {PWM_OUTPUT_DISABLED, NULL}, /* ch2: mode, no callback */
+ {PWM_OUTPUT_DISABLED, NULL}, /* ch2: mode, no callback */
+ {PWM_OUTPUT_DISABLED, NULL}, /* ch3: mode, no callback */
+ {PWM_OUTPUT_DISABLED, NULL}, /* ch4: mode, no callback */
+ {PWM_OUTPUT_DISABLED, NULL} /* ch5: mode, no callback */
+ },
+};
+
+/* Breathing Sleep LED brighness(PWM On period) table
+ *
+ * http://www.wolframalpha.com/input/?i=%28sin%28+x%2F64*pi%29**8+*+255%2C+x%3D0+to+63
+ * (0..63).each {|x| p ((sin(x/64.0*PI)**8)*255).to_i }
+ */
+/* ruby -e "a = ((0..255).map{|x| Math.exp(Math.cos(Math::PI+(2*x*(Math::PI)/255)))-Math.exp(-1) }); m = a.max; a.map\!{|x| (9900*x/m).to_i+1}; p a" */
+#define BREATHE_STEP 16 /* ms; = 4000ms/TABLE_SIZE */
+#define TABLE_SIZE 256
+static const uint16_t breathing_table[TABLE_SIZE] = {
+ 1, 1, 2, 5, 8, 12, 17, 24, 31, 39, 48, 58, 69, 81, 95, 109, 124, 140, 158, 177, 196, 217, 239, 263, 287, 313, 340, 369, 399, 430, 463, 497, 532, 570, 608, 649, 691, 734, 779, 827, 875, 926, 979, 1033, 1090, 1148, 1209, 1271, 1336, 1403, 1472, 1543, 1617, 1693, 1771, 1852, 1935, 2021, 2109, 2199, 2292, 2387, 2486, 2586, 2689, 2795, 2903, 3014, 3127, 3243, 3362, 3482, 3606, 3731, 3859, 3989, 4122, 4256, 4392, 4531, 4671, 4813, 4957, 5102, 5248, 5396, 5545, 5694, 5845, 5995, 6147, 6298, 6449, 6600, 6751, 6901, 7050, 7198, 7344, 7489, 7632, 7772, 7911, 8046, 8179, 8309, 8435, 8557, 8676, 8790, 8900, 9005, 9105, 9201, 9291, 9375, 9454, 9527, 9593, 9654, 9708, 9756, 9797, 9831, 9859, 9880, 9894, 9900, 9901, 9894, 9880, 9859, 9831, 9797, 9756, 9708, 9654, 9593, 9527, 9454, 9375, 9291, 9201, 9105, 9005, 8900, 8790, 8676, 8557, 8435, 8309, 8179, 8046, 7911, 7772, 7632, 7489, 7344, 7198, 7050, 6901, 6751, 6600, 6449, 6298, 6147, 5995, 5845, 5694, 5545, 5396, 5248, 5102, 4957, 4813, 4671, 4531, 4392, 4256, 4122, 3989, 3859, 3731, 3606, 3482, 3362, 3243, 3127, 3014, 2903, 2795, 2689, 2586, 2486, 2387, 2292, 2199, 2109, 2021, 1935, 1852, 1771, 1693, 1617, 1543, 1472, 1403, 1336, 1271, 1209, 1148, 1090, 1033, 979, 926, 875, 827, 779, 734, 691, 649, 608, 570, 532, 497, 463, 430, 399, 369, 340, 313, 287, 263, 239, 217, 196, 177, 158, 140, 124, 109, 95, 81, 69, 58, 48, 39, 31, 24, 17, 12, 8, 5, 2, 1, 1
+};
+
+uint16_t table_pos = 0;
+
+static THD_WORKING_AREA(waBreatheThread, 128);
+static THD_FUNCTION(BreatheThread, arg) {
+ (void)arg;
+ chRegSetThreadName("breatheThread");
+
+ while(!chThdShouldTerminateX()) {
+ pwmEnableChannel(&PWM_DRIVER, 0, PWM_PERCENTAGE_TO_WIDTH(&PWM_DRIVER,breathing_table[table_pos]));
+ table_pos = (table_pos+1) % TABLE_SIZE;
+ chThdSleepMilliseconds(BREATHE_STEP);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Initialize the PWM driver.
+ */
+ pwmStart(&PWM_DRIVER, &pwmcfg);
+ pwmEnablePeriodicNotification(&PWM_DRIVER);
+
+ /*
+ * Starts the PWM channel 0, turn the LED off.
+ */
+ pwmEnableChannel(&PWM_DRIVER, 0, 0);
+ pwmEnableChannelNotification(&PWM_DRIVER, 0); // MUST be before EnableChannel...
+
+ /*
+ * Create the breathe thread.
+ */
+ thread_t *breathe_thread_p;
+ breathe_thread_p = chThdCreateStatic(waBreatheThread, sizeof(waBreatheThread), NORMALPRIO, BreatheThread, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (!chThdShouldTerminateX()) {
+ chThdSleepMilliseconds(500);
+ }
+
+ chThdTerminate(breathe_thread_p);
+ chThdSleepMilliseconds(2*BREATHE_STEP);
+
+ /*
+ * Disables channel 0 and stops the drivers.
+ */
+ pwmDisableChannel(&PWM_DRIVER, 0);
+ pwmStop(&PWM_DRIVER);
+
+ return 0;
+}
diff --git a/testhal/KINETIS/TEENSY_LC/PWM/mcuconf.h b/testhal/KINETIS/TEENSY_LC/PWM/mcuconf.h new file mode 100644 index 0000000..189fcb6 --- /dev/null +++ b/testhal/KINETIS/TEENSY_LC/PWM/mcuconf.h @@ -0,0 +1,58 @@ +/*
+ ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define KL2x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#if 1
+/* PEE mode - 48MHz system clock driven by (16 MHz) external crystal. */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+#if 0
+/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
+#endif
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * USB driver settings
+ */
+#define KINETIS_USB_USE_USB0 TRUE
+/* need to redefine this, since the default is for K20x */
+#define KINETIS_USB_USB0_IRQ_PRIORITY 2
+
+/*
+ * PWM driver settings.
+ */
+#define KINETIS_PWM_USE_TPM0 TRUE
+
+#endif /* _MCUCONF_H_ */
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