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path: root/src/map/mio/mio.h
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* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-031-0/+1
* Updates and bug fixes.Alan Mishchenko2017-10-041-1/+1
* Maintenance and updates.Alan Mishchenko2017-09-241-0/+4
* Maintenance and updates.Alan Mishchenko2017-09-181-0/+1
* Experiments with new network data-structure.Alan Mishchenko2017-03-201-0/+1
* Equivalent fault detection code.Alan Mishchenko2016-11-091-0/+1
* Factoring out library preprocessing code in &nf and putting it elsewhere.Alan Mishchenko2016-05-161-0/+4
* Added switch 'read_genlib -n' to anonymize Genlib library.Alan Mishchenko2016-05-161-0/+1
* Adding API to convert Genlib into a simple Liberty.Alan Mishchenko2016-03-111-0/+1
* Consolidating timing manager Scl_Con_t and propagating changes.Alan Mishchenko2016-01-071-3/+0
* Migrating to using 32-bit timing representation in &nf.Alan Mishchenko2016-01-051-2/+2
* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-051-1/+2
* Adding code to support gate profiles.Alan Mishchenko2015-12-141-1/+4
* Adding code to support gate profiles.Alan Mishchenko2015-12-071-0/+7
* Adding commands to read/write/print gate profiles.Alan Mishchenko2015-12-051-0/+5
* Extending and improving timing manager.Alan Mishchenko2015-11-081-0/+1
* Extending and improving timing manager.Alan Mishchenko2015-11-081-0/+2
* Experiments with precomputation and matching.Alan Mishchenko2015-10-271-0/+1
* Extending library handling to 8 inputs.Alan Mishchenko2015-10-251-1/+2
* Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.Alan Mishchenko2015-10-231-1/+1
* Changes for delay-oriented computation.Alan Mishchenko2015-10-231-2/+3
* Experiments with precomputation and matching.Alan Mishchenko2015-10-151-0/+1
* Experiments with precomputation and matching.Alan Mishchenko2015-10-121-1/+2
* Updating Mio to use int instead of float.Alan Mishchenko2015-08-311-2/+18
* Adding APIs to retrieve NOR/OR gates from the library.Alan Mishchenko2015-04-141-0/+2
* Getting default AND-node delay from Genlib library.Alan Mishchenko2015-04-061-0/+1
* Major rehash of the CBA code.Alan Mishchenko2015-01-311-0/+1
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-251-1/+12
* Several changes to allow Liberty files without delay info.Alan Mishchenko2013-11-211-0/+1
* Improvements to buffering and sizing.Alan Mishchenko2013-10-131-1/+1
* Unifying standard cell library representations.Alan Mishchenko2013-09-171-3/+5
* Infrastructure to support full Liberty format and unitification of library re...Alan Mishchenko2013-09-151-1/+1
* Improved gate-sizing.Alan Mishchenko2013-07-291-0/+1
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-241-0/+4
* Modified SCL gate library to read/write gate formula.Alan Mishchenko2013-03-261-0/+1
* Replacing 'st_table' by 'st__table' to resolve linker problems.Alan Mishchenko2012-09-291-1/+1
* Cleaned up interfaces of genlib/liberty/supergate reading/writing.Alan Mishchenko2012-09-251-0/+1
* Cleaned up interfaces of genlib/liberty/supergate reading/writing.Alan Mishchenko2012-09-251-1/+1
* Changed printouts in a few places in supergate computation.Alan Mishchenko2012-09-241-1/+1
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-191-1/+2
* Extending BLIF parser/write to hangle multi-output cells.Alan Mishchenko2012-09-191-4/+5
* Added delay multipliers to 'map'.Alan Mishchenko2012-09-161-1/+2
* Added features 'map -M <float>' to control the use of large gates.Alan Mishchenko2012-08-271-1/+2
* Improving printouts of critical path.Alan Mishchenko2012-04-061-0/+1
* Additional features for delay optimizationAlan Mishchenko2012-03-211-4/+1
* Major restructuring of the code.Alan Mishchenko2012-01-211-2/+2
* Made gate library package Mio independent of CUDD.Alan Mishchenko2011-03-301-4/+12
* initial commit of public abcAlan Mishchenko2010-11-011-7/+11
* Version abc90215Alan Mishchenko2009-02-151-4/+4
* Version abc90118Alan Mishchenko2009-01-181-0/+3
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