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* chipset_enable.c: Mark Intel HM65 as DEPAngel Pons2018-10-081-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Toshiba L755 laptop with an Intel HM65. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25U8032EAngel Pons2018-10-072-0/+41
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I422c3d51e5011e081ff6bccff294817c8c1765d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q128.V..WPatrick Rudolph2018-10-052-0/+38
| | | | | | | | | | | Port the code from chromeos flashrom. Tested using W25Q128JVSIM in SPI mode. Change-Id: I38397a0c831407afa21cddca8485664576fce92c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove unneeded whitespaceElyes HAOUAS2018-10-052-2/+1
| | | | | | | | Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark S25FL208K as testedNico Huber2018-10-041-1/+1
| | | | | | | | | | As report by Frédéric Germain on 2017-12-17. Change-Id: I0a7fc10e75f4a675de41e9765525defe2d2640e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ISSI IS25WP064 and IS25WP032Nico Huber2018-10-042-1/+88
| | | | | | | | | | | | The IS25WP064 was tested successfully by Simon Buhrow as reported on 2018-9-4. While we are at it, also add the 32Mbit version which shares the datasheet (as does the already supported 128Mbit version). Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add ATMEL AT25SL128AHal Martin2018-10-032-0/+40
| | | | | | | | | Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/26576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Enable native 4BA instructions for Spansion 25FL256SNico Huber2018-10-031-1/+4
| | | | | | | | | Change-Id: I0ffc816ca714ecce5b89b1eaadb5e73ccb38d9ab Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Enable 4BA mode for Spansion 25FL256SNico Huber2018-10-034-8/+12
| | | | | | | | | | | 4BA mode is entered by setting bit 7 for the extended address register. Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add Spansion 25FL256S......0Nico Huber2018-10-033-1/+47
| | | | | | | | | | | | | | | | The Spansion 25SFL256S supports 4BA through an extended address register, a 4BA mode set by bit 7 of that register, or native 4BA instructions. Enable the former only for now. Unfortunately the S25SF256S uses another instruction to write the exten- ded address register. So we add an override for the instruction byte. Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Mark Spansion S25FL128P......0 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | Tested with a Spansion FL128PIF. Change-Id: Ic99eabb67d5bce3910e9275d0056a7cfa8cff36f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Atmel AT45DB081D as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I225984b9e2589713f25d0f9b49eb1c3abdcff3cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q40BW as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | | As per `The_Raven Raven` on the mailing list. The tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW` when the `W25Q40EW` was added. Change-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD040 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: Ied8d07c54f8a222dbe05503f859f82bba27d8336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Sanyo LE25FU406C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I1dba38d03c826a53bff3ddad0aa536032c5532a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark PMC Pm25LD020 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per `The_Raven Raven` on the mailing list. Change-Id: I16d5a207599b434fe52b42709e42f1f32a8e6698 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25Q128C as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Tomasz Walach on the mailing list. Change-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark AMIC A25L40PU as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Stefan Szwarnowski on the mailing list. Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Broadwell U Premium as DEPAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | As per Laurent Grimaud on the mailing list. I also have said chipset. Since all ME-enable chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Winbond W25Q256.V as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Richard Hughes via the mailing list. Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Macronix MX66L51235 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Nick (cel366) on 2018-05-16 via mailing list. Change-Id: I44363e6755167adbc120444a481b09bb4e1063c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Atmel AT25DF161 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As per Konstantin on 2018-06-08 via mailing list. Change-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Macronix MX25U12835F as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | | As reported by David Martinka on the mailing list. Erase has not been tested, but since writes are reported as working, it is very likely erase works as well. Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Eon EN25S40 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As reported by `The_Raven Raven` on the mailing list. Change-Id: I00f9c6fcf13c486765d0ac4fe06a8b0989b03f91 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25B128B/GD25Q128B as testedAngel Pons2018-10-031-2/+2
| | | | | | | | | | | | Alexander reported this chip as tested using a GD25B128CPIG (same device ID, apparently) on 2018-08-30 via the mailing list. The chip name is updated as well. Change-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add ISSI IS25LP064Angel Pons2018-10-032-0/+42
| | | | | | | | | | | Grabbed from mailing list, created by Simon Buhrow. Since no logs were attached, the chip is marked as untested. Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark Micron MT25QL512 as testedAngel Pons2018-10-031-1/+1
| | | | | | | | | | As reported by `Yuta Teshima` on the mailing list. Change-Id: I7325d42b43b71ab5fc2c7618e0577e4a7b31f01a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add initial support for Dediprog SF200.Jay Thompson2018-09-111-5/+14
| | | | | | | | | | Change-Id: I025d1533e249f6a75b6d9015a18a6abf350456b6 Signed-off-by: Jay Thompson <thompson.jay.thomas@gmail.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/28272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* helpers: Add reverse_byte() and reverse_bytes()Marc Schink2018-08-303-11/+21
| | | | | | | | Change-Id: I9d2e1e2856c835d22eed3b3a34bc0379773dd831 Signed-off-by: Marc Schink <flashrom-dev@marcschink.de> Reviewed-on: https://review.coreboot.org/28086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* usbdev: Refactor device discovery codeDaniel Thompson2018-08-301-58/+70
| | | | | | | | | | | | | | | | | Currently there is a lot of code shared between usb_dev_get_by_vid_pid_serial() and usb_dev_get_by_vid_pid_number(). Fix this by pulling out the conditional filtering at the heart of each loop and calling it via a function pointer. I haven't got (two) dediprog programmers to test with but I have tested both by...serial() and by...number() calls using a pair of Developerboxen and a hacked driver. Change-Id: I31ed572501e4314b9455e1b70a5e934ec96408b1 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/27444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* usbdev: Extract libusb1 device discovery into a separate fileDaniel Thompson2018-08-305-108/+141
| | | | | | | | | | | | Currently there is a TODO-like comment in the dediprog driver: "Might be useful for other USB devices as well". Act on this comment by collecting all the device discovery code for libusb1 devices into a separate file. Change-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/27443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM55 as DEPAngel Pons2018-08-221-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP 630 laptop with an Intel HM55. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix typosElyes HAOUAS2018-08-198-10/+10
| | | | | | | | Change-Id: I20745d5f30f9577622e27abf2f45220f026f65ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove empty line at EOFElyes HAOUAS2018-08-194-4/+0
| | | | | | | | Change-Id: Id6063cb5d406d7139abf7fcdf2ae265363640f9f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Mark GigaDevice GD25Q512 as testedNico Huber2018-08-191-1/+1
| | | | | | | | | | As reported by `nvflash` on IRC. Change-Id: Id3928e3790ddac34645959535e646d552ce5328e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
* Add support for MX25R6435FNathan Rennie-Waldock2018-08-172-0/+41
| | | | | | | | | Change-Id: I664ffce6f9aa7544e17b516a1b4179d561208b2f Signed-off-by: Nathan Rennie-Waldock <nathan.renniewaldock@gmail.com> Reviewed-on: https://review.coreboot.org/28004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add Macronix MX25U51245GDaniel Thompson2018-08-172-0/+50
| | | | | | | | | | | | | | | | Copy 'n paste support for Macronix MX25U51245G. I don't pretend to know a whole lot about SPI FLASH so its mostly copied from other MX25U devices and double checked a few bits and pieces against the datasheet. I have tested basic probe, read, erase and write using layout files. I tested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I have tested 4-byte addressing). Change-Id: I2117fc205006088967f3d97644375d10db1791f1 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/26949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer: Add Developerbox/CP2104 bit bang driverDaniel Thompson2018-08-174-2/+278
| | | | | | | | | | | | | | | | | | | | | | | | The 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102 debug UART with its GPIO pins hooked up to the SPI NOR FLASH. The circuit is intended to provide emergency recovery functions without requiring any additional tools (such as a JTAG or SPI programmer). This was expected to be very slow (and it is) but CP2102 is much cheaper than a full dual channel USB comms chip. Read performance is roughly on par with a 2400 baud modem (between 60 and 70 minutes per megabyte if you prefer) and write performance is 50% slower still. The full recovery process, with backup and verification of 4MB data written takes between 14 and 15 hours. Thus it is only really practical as an emergency recovery tool, firmware developers will need to use an alternative programmer. Change-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* bitbang_spi: Add half-duplex optimizationsDaniel Thompson2018-08-171-5/+19
| | | | | | | | | | | | | | | | | | Currently, the core of bitbang_spi is a full-duplex SPI loop but in practice this code is only ever used half-duplex. Spliting this code into two half duplex loops allows us to optimize performance by reducing communications and/or CPU pipeline stalls. The speed up varies depending on how much the overhead of getting/setting pins dominates execution time. For a USB bit bang driver running on a 7th generation Core i5, the time to probe drops from ~7.7 seconds to ~6.7 seconds when this patch is applied. Change-Id: I33b9f363716f651146c09113bda5fffe53b16738 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/26947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* bitbang_spi: Add functions to optimize xfersDaniel Thompson2018-08-172-16/+27
| | | | | | | | | | | | | | | | | | | | On systems where the overhead of getting/setting pins is much greater than the half period (for example, USB bit banging) it significantly boosts performance if we can bang more than one bit at the same time. Add support for setting sck at the same time as mosi or miso activity. The speed up varies depending on how much the overhead of getting/setting pins dominates execution time. For a USB bit bang driver running on a 7th generation Core i5, the time to probe drops from ~9.2 seconds to ~7.7 seconds when set_clk_set_mosi() is implemented. Change-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/26946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* board_enable.c: Fix dmi_match string for ThinkPad X201Arthur Heymans2018-07-311-1/+1
| | | | | | | | | | | | TESTED, flashrom now properly works on Thinkpad X201 running vendor firmware and coreboot. Change-Id: I40dc7204499323148707b392d94ecd4b212f9ace Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* digilent_spi: Avoid deprecated libusb functionsArthur Heymans2018-07-311-0/+4
| | | | | | | | | | | libusb 1.0.22 marked libusb_set_debug as deprecated. For such versions of libusb, use libusb_set_option instead. Change-Id: Ie139de36f15c4f4d87787cab0f968a2f0e6f0c8c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* digilent_spi: add a driver for the iCEblink40 development boardLubomir Rintel2018-06-265-2/+508
| | | | | | | | | | | | | | | This is driver that supports the Lattice iCE40 evaluation kits. On the board is a SPI flash memory chip labeled ST 25P10VP. Tested to work read/write/erase with "-p digilent_spi -c M25P10" or with a patch that resets the part beforehands (in which case it gets detected as a M25P10-A and is way faster due to paged writes). Change-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove unneeded white spacesElyes HAOUAS2018-06-2414-24/+24
| | | | | | | | | Change-Id: I90f171924790ced74a62ca344fee8607607aa480 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* linux_mtd: Bail out early if sysfs node doesn't existDavid Hendricks2018-06-241-0/+18
| | | | | | | | | | | | | | | | | | This checks that the MTD sysfs node we will use actually exists prior to calling setup code. Although the setup code will eventually catch such an error, we need to think about the use case before printing a possibly irrelevant/confusing error message to the terminal. This patch makes it so that we only print an error message if the user specifies a non-existent MTD device. Otherwise, the failure is considered benign and we only print a debug message prior to bailing out. Change-Id: I8dc965eecc68cd305a989016869c688fe1a3921f Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix mingw detection on Windows 7 (NT-6.1)Miklós Márton2018-06-232-8/+12
| | | | | | | | | | Hopefully also for other non-XP Windows build environments. Change-Id: I7f856dc4847c4ca9197b1935b7a9b9071b46c70a Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/23865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for AT25DF021ASteffen Mauch2018-06-062-0/+40
| | | | | | | | | | | This is the low-voltage version of the AT25DF021. Tested with FT2232H Mini Module Change-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57 Signed-off-by: Steffen Mauch <steffen.mauch@gmail.com> Reviewed-on: https://review.coreboot.org/26856 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Add PCI IDs for discrete Kaby Lake PCHsNico Huber2018-06-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their Skylake "100 Series" siblings. [1] Intel® 200 Series (including X299) and Intel® Z370 Series Chipset Families Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 003 Document Number 335192 [2] Intel® 200 Series (including X299) Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 003 Document Number 335193 Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add support for the AT25SF081Evan Jensen2018-06-042-1/+40
| | | | | | | | Change-Id: I1a3d900462ad9e7a3b34575d7c98acc7c2df0445 Signed-off-by: Evan Jensen <evan.p.jensen@gmail.com> Reviewed-on: https://review.coreboot.org/26779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Enable writes with active MENico Huber2018-05-292-54/+39
| | | | | | | | | | | | | Replace the `ich_spi_force` logic with more helpful warnings. These can be hidden later, in case the necessary switches are detected. Also, demote some warnings about settings that are the default nowadays (e.g. SPI configuration lock, inaccessible ME region). Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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