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* it87spi.c: Reorder functions with primitives at the topEdward O'Callaghan2020-11-221-172/+164
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:173477683 TEST=builds Change-Id: I94b169d19cb29336bb9cb4c16d0efee15b1e14c2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47661 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Boya Microelectronics BY25Q128ASJack Olsen2020-11-202-0/+42
| | | | | | | | | | | Tested on Buspirate. Signed-off-by: Jack Olsen <omegasec@tutanota.com> Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it85spi.c: Reorder functions with primitives at the topAnastasia Klimchuk2020-11-171-69/+64
| | | | | | | | | | | | | | | Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:172876667 TEST=builds Change-Id: Idf4241c92d90c28dd4f4ec3b7d66bda50801385a Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47657 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
| | | | | | | | | | | | | | | | Modified to be pch7 over pch6 as per-coreboot and review comments. BUG=none BRANCH=none TEST=none Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Disable ENE_LPC and MEC1308 on non-x86 archVictor Ding2020-11-121-0/+10
| | | | | | | | | | | | | Both requires PCI port I/O and hence works only on x86. TEST=builds on Ubuntu for Raspberry Pi Signed-off-by: Victor Ding <victording@google.com> Change-Id: I69e1fbd87819b0b6370f31e9ee4c474500fb3759 Reviewed-on: https://review.coreboot.org/c/flashrom/+/47394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer.h: Reorder MEC1308 and ENE_LPC enumeratorsEdward O'Callaghan2020-11-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Programmer enumerators and their corresponding programmer_table entries need to be aligned. This was not the case for MEC1308 and ENE_LPC. Their configs were not enabled by default until commit 26fde5b0b067 ("ene_lpc,mec1308: Fix entry-points to be explicit")/CL:2488823, allowing this issue to go unnoticed. The particular symptom of the mismatch was internal_init() trying to init linux_mtd instead of linux_spi. BUG=b:172668501 TEST=flashrom -p host on gale BRANCH=None Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52 Original-Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47353 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Victor Ding <victording@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* test_build.sh: Move build test procedure to repositoryPatrick Georgi2020-11-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* spi25.c: Use JEDEC consts in spi_simple_write_cmd() callsEdward O'Callaghan2020-10-311-10/+10
| | | | | | | | | | | | | | | | | | | | | | Make use of the JEDEC_CE_{60,62,C7} defined constants of the op-codes in each of the spi_simple_write_cmd() calls to assist in readability. V.2: Squash in JEDEC_BE_{52,C4,D7,D8,50,81} && JEDEC_SE. Both 'S'ector and 'B'lock 'E'rasers now use the consts in spi.h. BUG=none BRANCH=none TEST=builds same object. Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47005 Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Use define const in spi_simple_write_cmd() fnEdward O'Callaghan2020-10-311-1/+1
| | | | | | | | | | | | | | | | This uses the JEDEC_WREN_OUTSIZE define in the spi_simple_write_cmd() helper function to improve readability. BUG=none BRANCH=none TEST=builds same object Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* fmap.{c,h}: update copyright year and nameNikolai Artemiev2020-10-302-2/+2
| | | | | | | | | | | Looks like the year should be 2010 based on cros git history. Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I7c27e682bd09f7b1ba0398dc231b9360aed1c26b Reviewed-on: https://review.coreboot.org/c/flashrom/+/46440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: De-maze the pre-processor wraps a littleEdward O'Callaghan2020-10-281-5/+3
| | | | | | | | | | | | | | | This makes it again easier to parse internal.c by consolidating some processor wraps and labeling the ends of others. BUG=none BRANCH=none TEST=builds Change-Id: I32fb1a3fff7afa671f08fb2cc2ad406772f5e10f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Fix typo NEED_LIBUSB0 -> NEED_LIBUSB1Edward O'Callaghan2020-10-281-1/+1
| | | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I5a402d9530f73419d8317d94a8d6f745d09675ea Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: remove LSPCON and MST device dependency from libusbShiyu Sun2020-10-281-2/+0
| | | | | | | | | | | LSPCON and MST do not depend on libusb. Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: If6db3a318aca349fc1ccd343d3d6d47b809eac8e Reviewed-on: https://review.coreboot.org/c/flashrom/+/46870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher.c: Fix null par data and size param handlingNamyoon Woo2020-10-272-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a few bugs that two patches ( `3149822cd45cb2e5841e15d648783748ba1b2ec6` && `3b8fe0f8e907c0ba9f7c7935e950f3e1538d427f`) brought: * Check the presence of 'size' param only if the emulate is VARIABLE_SIZE. * Initialize 'flash->st->par.data' in dummy_init() so that it can probe the VARIABLE_SIZE emulator correct in probe_variable_size(). * Replace atoi() with strtol(). * Revise man page to describe how to use the VARIABLE_SIZE emulation target. TEST: $ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE,size=16777216 \ -w ${IMG} -V -f ... Verifying flash... VERIFIED. Writing dummy.bin $ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE -w ${IMG} -V -f ... dummy_init: the size parameter is not given. Unhandled programmer parameters (possibly due to another failure): image=dummy.bin, Error: Programmer initialization failed $ flashrom -p dummy:image=dummy.bin,emulate=SST25VF040.REMS -c SST25LF040A -w ${IMG} ... Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. $ man flashrom ... * Dummy vendor VARIABLE_SIZE SPI flash chip (configurable size, page write) Example: flashrom -p dummy:emulate=SST25VF040.REMS To use VARIABLE_SIZE chip, size must be specified to configure the size of the flash chip as a power of two. Example: flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin ... Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ie6481943a831b946a91b643b4d79e684c27e48b8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Mark ENE_LPC and MEC1308 as NEED_LIBPCIVictor Ding2020-10-271-0/+4
| | | | | | | | | | | | Both depend on functions from chipset_enable.c and board_enable.c, which require libpci. Signed-off-by: Victor Ding <victording@google.com> Change-Id: I9505d7f18f4781a264e29e9667b717c061ba33b8 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46812 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher.c: Do not print an error if probing failsAngel Pons2020-10-271-5/+1
| | | | | | | | | | | | | This line gets printed even when not using dummyflasher at all. Drop it. TEST=Check that no spurious error message appears with ft2232_spi. Change-Id: I1a81a735db391357d1b6ee6f3e9844255efd0e19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2020-10-271-0/+2
| | | | | | | | | | | Port from the ChromiumOS fork of flashrom. Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: Co-locate global variables to top of fileEdward O'Callaghan2020-10-271-8/+8
| | | | | | | | | | | | | | | This just makes internal.c at bit easier to parse and helps the read get a view of all the singleton state in one go. BUG=none BRANCH=none TEST=builds Change-Id: Id4109dfb17f63d80fb3fb3f2a1d0ab54d9eddc6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: Reshuffle functions to avoid forward declsEdward O'Callaghan2020-10-271-50/+36
| | | | | | | | | | | | | | | This just makes internal.c a little easier to parse and avoids some fn prototypes on the mental stack. BUG=none BRANCH=none TEST=builds Change-Id: I693e30068e6a53b5fc161d895af451540650a8fe Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Mark ENE_LPC and MEC1308 as NEED_RAW_ACCESSVictor Ding2020-10-271-0/+2
| | | | | | | | | | | | Both use INB/OUTB and hence should be marked as NEED_RAW_ACCESS in the makefile. Signed-off-by: Victor Ding <victording@google.com> Change-Id: I6fafd9f59d06f60e9491e3e059c1205d48d8232e Reviewed-on: https://review.coreboot.org/c/flashrom/+/46811 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashrom.c,flash.h: Kill dead fn shutdown_free()Edward O'Callaghan2020-10-242-7/+0
| | | | | | | | | | | | | | Seems to be dead code with no call sites. BUG=none BRANCH=none TEST=builds Change-Id: Ic9f33415b8a357916891cb2006612cbf5e6aa559 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Introduce ISP enter paramShiyu Sun2020-10-241-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to avoid attempt entering ISP mode multiple times. The ISP mode can only exit after a reset, so once the reset MCU parameter is set to 0, the device will not able to exit from ISP mode and hence shouldn't enter ISP again on the next operation. Without exit ISP mode, the device data, like firmware version, will not show the correct value, this param will also help to identify this situation. BUG=b:152558985,b:148745673 BRANCH=none TEST=build and run: $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=1 \ -l layout -i PARTITION1:fw -w $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=0 \ -l layout -i FLAG1:flag -w then either reset computer to allow update to take effect, or: $ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=1,enter-isp=0 \ --flash-size to trigger the update. Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I58931ac8b42ab55829f102d243aea6fcfd632e3e Reviewed-on: https://review.coreboot.org/c/flashrom/+/46623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add support for Fudan SPI flash chipsJakob Petersson2020-10-232-0/+282
| | | | | | | | | | | Signed-off-by: Jakob Petersson <github@jakobpetersson.se> Change-Id: I8045ecb8778fd6111fcccc075e69928f131a926a Reviewed-on: https://review.coreboot.org/c/flashrom/+/46513 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Trigger gpio 88 toggle down after writeShiyu Sun2020-10-231-2/+1
| | | | | | | | | | | | | BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I1407714e1bb4cf2472090bae8a613c7103a5938c Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46448 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it87spi.c: Prevent use-after-free bugAngel Pons2020-10-221-1/+2
| | | | | | | | | | | | The memory for the `param` string is aliased by `dualbiosindex_suffix`. Moreover, `errno` could have been modified by the call to `free()`. Therefore, only free the former when there are no more uses of either. Change-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25.c: Replace tab with space after '=' symbolEdward O'Callaghan2020-10-171-1/+1
| | | | | | | | | | Trivial, only noticed while diff'ing with ChromiumOS fork. Change-Id: I247d9cb1910a9afdb0e7bfe81515d51514da6550 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* pcidev.c: populate IDs with pci_fill_info()Daniel Verkamp2020-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With pciutils 3.7.0, flashrom is unable to match any PCI devices by vendor/device ID because the vendor_id and device_id fields of struct pci_dev are not filled in. Call pci_fill_info() to request these identifiers before trying to match them against the supported device list. The pciutils ChangeLog for 3.7.0 mentions that the documentation and back-end behavior for pci_fill_info() was updated; it seems that a call to pci_fill_info() was always intended to be required, but some backends (such as the sysfs one used on Linux) would fill the identifier fields even when not requested by the user. The pci_fill_info() function and the PCI_FILL_IDENT flag have been available for all versions of pciutils since at least 2.0 from 1999, so it should be safe to add without any version checks. With this change, reading/writing a nicintel_spi boot ROM is successful. Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Change-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef Reviewed-on: https://review.coreboot.org/c/flashrom/+/46310 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Update GPIO pin 88 toggle functionShiyu Sun2020-10-141-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Here we provide a helper function to allow indexing MCU configuration registers. The 0x9F port allows access to these MCU configuration registers followed by the high and then low bytes of the register address we wish to index written into 0xF5 or 0xF4 respectively, a read or write can then be made via 0xF5. For the configuration of GPIO pins on the chip, there are two relevant register address, 0x104F for pin direction (sink input or push-pull in-out) configuration and 0xFE3F for pin data values (1 to push-pull and 0 to sink). The reference design uses GPIO 88 to strap the write protection pin and so we provide a function that allows the call site to toggle this state and therefore de-assert hardware write protection of the external spi flash. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds && verified the write protection get disabled. Change-Id: I1aed0086f917e31bebb51857ad5cce138158fe82 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46089 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it87spi.c: Fix layering violation of default_spi_readEdward O'Callaghan2020-10-121-2/+2
| | | | | | | | | | | | default_spi_read() calls spi_read_chunked() with the correct max_read value of 3 set in the spi master struct. Change-Id: I199c81e1ba501e86dbfb7cf18e2d1556e30db62e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46233 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog.c: Fix layering violation of default_spi_readEdward O'Callaghan2020-10-121-3/+3
| | | | | | | | | | | | default_spi_read() calls spi_read_chunked() with the correct max_read value of 16 set in the spi master struct. Change-Id: Ic0897f74056e3d723a33c063ed0bd8cb6e88ba45 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46232 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Fixup get_params() err ctrl flowEdward O'Callaghan2020-10-021-5/+4
| | | | | | | | | | | | | Ensure that when bus number and reset params are specified at the same time are both correctly parsed by get_params(). Also renames the goto err cleanup path to make it clear. Change-Id: Icb45b1ab39181b0f1a2dec1cce549d30db984936 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Spotted-by: Shiyu Sun <sshiyu@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45944 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Introduce MCU reset paramEdward O'Callaghan2020-10-021-5/+26
| | | | | | | | | | | | Modify the spi master as to not automatically reset the MCU on tear-down unless explicitly stated by a param. Change-Id: Ib70bf7399e7541f30b6905cdb950a6fb7b74ae18 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45674 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove reset from init fnEdward O'Callaghan2020-10-021-5/+0
| | | | | | | | | | | | | | Remove MCU reset on init as this was only introduced when MCU fw requirements for correct flashing were unknown however it turns out no MCU fw is required to flash and so no MCU reset should occur upon initialization. Change-Id: Ia03f94effc4b720964638c032bbde5acfb13960d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45896 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add writeprotect support infrastructureEdward O'Callaghan2020-09-286-2/+602
| | | | | | | | | | | | | | | | The following just lays out the structure for write protect manipulation of SPI flash chips in Flashrom. We later follow up with adding support for each manufacturer group. BUG=b:153800563 BRANCH=none TEST=builds Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40325 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-245-2/+32
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* dummyflasher.c: Upstream ChromiumOS 'freq' param featureEdward O'Callaghan2020-09-221-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the dummyflasher to emulate a bus/chip frequency by passing a delay parameter. BUG=b:140394053 BRANCH=none TEST=builds and ran with freq passed, ``` └──╼ dd if=/dev/urandom of=/tmp/bar bs=2K count=1 1+0 records in 1+0 records out 2048 bytes (2.0 kB, 2.0 KiB) copied, 0.000583308 s, 3.5 MB/s └──╼ ./flashrom -p dummy:image=/tmp/foo,bus=spi,freq=100Hz,size=2048,emulate=VARIABLE_SIZE -w /tmp/bar flashrom v1.2-105-g702c58a-dirty on Linux 5.7.10-1rodete2-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Generic flash chip "Variable Size SPI chip" (2 kB, SPI) on dummy. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. ``` Change-Id: I1c2702b9e0cae860f5f03114e307707d4d3219af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* tests: Update licence headersNikolai Artemiev2020-09-177-4/+101
| | | | | | | | | | Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: Ia964279ace569b4b93f4e2919c1c228a9b621745 Reviewed-on: https://review.coreboot.org/c/flashrom/+/45438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests: Clear ID cache before trying to fetch chip ID a second timePatrick Georgi2020-09-161-0/+1
| | | | | | | | | | | | Without that, the code never calls into spi_send_command (because everything's known already) and so the expected return values are never returned. Change-Id: Iba6a56774ce5b51e0f7072b4600a9479cdabf8c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher.c: Factor out global stateLachlan Bishop2020-09-141-168/+204
| | | | | | | | | | | | Moves global state into spi_master data. BUGS=b:140394053 Change-Id: I972b085875f1277d9ff33326669d2676a3bcd3aa Signed-off-by: Lachlan Bishop <lxb@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/45230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURGJonathan Zhang2020-09-101-3/+11
| | | | | | | | | | | | | | | | | Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA. Fix guess_ich_chipset_from_content() accordingly. Print status info of read_ich_descriptors_from_dump() to facilitate debugging upon failure. TESTED=run flashrom successfully from OCP Yosemite V3 DeltaLake server. Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* support 4-byte address format for VARIABLE_SIZE dummy flash deviceNamyoon Woo2020-09-072-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a support of 4-byte address format for VARIABLE_SIZE dummy flash device, so that it can emulate an flash size larger than 16 MBytes. - assigned a feature bits FEATURE_4BA to VARIABLE_SIZE flash config. - added codes handling two commands, JEDEC_READ_4BA and JEDEC_BYTE_PROGRAM_4BA. - changed blockeraser to use Chip-Erase command so that it can be free from flash address byte format. TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=33554432, \ emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=8388608, \ emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44881 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher.c: Only write back emulated image if modifiedNamyoon Woo2020-09-071-1/+9
| | | | | | | | | | | When the image is not modified, there is no point in writing it back. In fact we may not have file permissions to do so. Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44907 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* support variable-size SPI chip for dummy programmerNamyoon Woo2020-09-073-0/+113
| | | | | | | | | | | | | | | | | | | This is designed for firmware updater to pack firmware image preserving some specific partitions in any size. BUG=none TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=auto, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iff266e151459561b126ecfd1c47420b385be1db2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
| | | | | | | | | | | Tested reading and writing internal flash on Dell Optiplex 9010 SFF. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4717959be1b79aa986f1276589d01ce7475bda8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
| | | | | | | | | | Add PCI IDs for C621A, C627A and C629A. Change-Id: I636becd9f08bdf604c6af81ce396049655353b04 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Allow cached ID bytes to be clearedEdward O'Callaghan2020-08-262-34/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does two things: 1. Removes the static variables from various ID functions and moves them to a single struct. 2. Adds a function to clear the struct. The idea of the original caching mechanism introduced years ago was simply to speed up probe_flash() by not issuing the same read ID commands dozens or hundreds of times for a single chip. That implementation assumed that we would only call probe_flash() once. However, there are cases when we want to call probe_flash() multiple times, for example, if using an external programmer and using different voltages (for probing the chip). This patch is extremely similar to the original works of: `commit 57b7524b1448189d3630d6c4735e60dbbdf14d51`. Author: David Hendricks <dhendrix@chromium.org> && `commit 7f7c711ee1a41649607f81f1533e5135fc1361fc`. Author: David Hendricks <dhendrix@chromium.org> BUG=b:15656443 BRANCH=none TEST=none Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* spi25.c: Factor out rdid_get_ids() and compare_id()Edward O'Callaghan2020-08-261-32/+30
| | | | | | | | | | | | | | | | | | This is in preparation for implementing a cache for the probe results of RDID and REMS (3&4-byte variant) commands. The intention is to make probing of SPI rom's slightly faster, a few 10's of ms dependant upon the spi master used. BUG=b:15656443 BRANCH=none TEST=builds Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chipset_enable.c: Add support for Intel C620 Series Chipset SPI ControllerLuka Kovacic2020-08-251-0/+1
| | | | | | | | | | | | | | | | | | Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform: - Intel Xeon D-2187NT Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Tested-by: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Makefile: Fix building on AArch64 NixOSPyry Kontio2020-08-241-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parsing of the output of archtest.c produced an unexpected value on AArch64 NixOS. For example, the make variable ARCH was set to: ``` bit outside of fd_set selected arm ``` This made the arch and OS checks fail. This commit simplifies the parsing, making it more robust. The C files archtest.c, endiantest.c and os.h used to set the TARGET_OS, ARCH and ENDIAN variables, respectively, output the result of the test as the final line, so just extracting the final line and removing double quoting is enough. This commit also fixes a bug with debug_shell lacking escaping single quotes, which prevented using the single quote in the debug_shell calls. It used to work by accident before this fix; the line in the call happened to contain a balanced pair of double quotes and lacked other characters that needed escaping, which didn't break the debug_shell, but this was accidental and very brittle. Signed-off-by: Pyry Kontio <pyry.kontio@drasa.eu> Change-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add MEC1308 EC programmerVictor Ding2020-08-206-0/+572
| | | | | | | | | | | | | Initial support of Microchip MEC1308 Embedded Controller. BUG=b:156144893 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 16:10:53 +0000