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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-06 18:44:32 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-06 18:44:32 +0200 |
| commit | 14b5cbdad8da4e0957f02dd94e3ff94d49772f18 (patch) | |
| tree | 996947d2de1759bbc111d978343087275a9f0de7 | |
| parent | 667e33c2029070b24681b4483c5384eab47cb3a8 (diff) | |
| download | ghdl-yosys-plugin-14b5cbdad8da4e0957f02dd94e3ff94d49772f18.tar.gz ghdl-yosys-plugin-14b5cbdad8da4e0957f02dd94e3ff94d49772f18.tar.bz2 ghdl-yosys-plugin-14b5cbdad8da4e0957f02dd94e3ff94d49772f18.zip | |
add shift functions (#54)
| -rw-r--r-- | src/ghdl.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index b027204..e44fa78 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -297,6 +297,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Not: case Id_Red_Or: case Id_Red_And: + case Id_Lsr: + case Id_Lsl: case Id_Assert: // No output case Id_Assume: // No output case Id_Cover: // No output @@ -424,6 +426,12 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Red_And: module->addReduceAnd(to_str(iname), IN(0), OUT(0)); break; + case Id_Lsl: + module->addShl(to_str(iname), IN(0), IN(1), OUT(0)); + break; + case Id_Lsr: + module->addShr(to_str(iname), IN(0), IN(1), OUT(0)); + break; case Id_Mux2: module->addMux(to_str(iname), IN(1), IN(2), IN(0), OUT(0)); break; |