Add a test for asynchronous reset dff.

3 files changed, 43 insertions, 0 deletions

diff --git a/testsuite/issues/issue101/counters_3.v b/testsuite/issues/issue101/counters_3.v
new file mode 100644
index 0000000..bf15520
--- /dev/null
+++ b/testsuite/issues/issue101/counters_3.v
@@ -0,0 +1,9 @@
+module counters_3 (input wire c, input wire aload, input wire [3:0]d,
+     output reg [3:0] q);
+  always @(posedge c, posedge aload) begin
+    if (aload)
+      q <= d;
+    else
+      q <= q + 1;
+  end
+endmodule
diff --git a/testsuite/issues/issue101/counters_3.vhdl b/testsuite/issues/issue101/counters_3.vhdl
new file mode 100644
index 0000000..d2205cb
--- /dev/null
+++ b/testsuite/issues/issue101/counters_3.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity counters_3 is
+    port(C, ALOAD : in std_logic;
+         D : in std_logic_vector(3 downto 0);
+         Q : out std_logic_vector(3 downto 0));
+end counters_3;
+
+architecture archi of counters_3 is
+    signal tmp: std_logic_vector(3 downto 0);
+begin
+    process (C, ALOAD, D)
+    begin
+        if (ALOAD='1') then
+            tmp <= D;
+        elsif (C'event and C='1') then
+            tmp <= tmp + 1;
+        end if;
+    end process;
+
+    Q <= tmp;
+
+end archi;
diff --git a/testsuite/issues/issue101/testsuite.sh b/testsuite/issues/issue101/testsuite.sh
new file mode 100755
index 0000000..d052280
--- /dev/null
+++ b/testsuite/issues/issue101/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import -fsynopsys counters_3.vhdl -e
+
+clean
+echo OK