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authorAimylios <20016942+aimylios@users.noreply.github.com>2020-04-19 14:20:37 +0200
committertgingold <tgingold@users.noreply.github.com>2020-04-19 16:08:35 +0200
commit8bb8453af7acd34705a449cac9cd8427d6db43ba (patch)
tree9243aaa5ec9c4f91abd7291af432dbba41772815 /examples/icestick/leds/rotate3.vhdl
parentd941c8f65bbbb90f97c17e26b5610624c2198b10 (diff)
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Improve examples for Lattice iCEstick
- move "leds" examples to subdirectory - add Makefile - add *.json files to .gitignore - adjust README.md and fix some typos
Diffstat (limited to 'examples/icestick/leds/rotate3.vhdl')
-rw-r--r--examples/icestick/leds/rotate3.vhdl38
1 files changed, 38 insertions, 0 deletions
diff --git a/examples/icestick/leds/rotate3.vhdl b/examples/icestick/leds/rotate3.vhdl
new file mode 100644
index 0000000..213512f
--- /dev/null
+++ b/examples/icestick/leds/rotate3.vhdl
@@ -0,0 +1,38 @@
+architecture rotate3 of leds is
+ signal clk_4hz: std_logic;
+begin
+ process (clk)
+ -- 3_000_000 is 0x2dc6c0
+ variable counter : unsigned (23 downto 0);
+ begin
+ if rising_edge(clk) then
+ if counter = 2_999_999 then
+ counter := x"000000";
+ clk_4hz <= '1';
+ else
+ counter := counter + 1;
+ clk_4hz <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ variable count : unsigned (1 downto 0);
+ begin
+ if rising_edge(clk) and clk_4hz = '1' then
+ case count is
+ when "00" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("10001");
+ when "01" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("01000");
+ when "10" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("00101");
+ when "11" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("00010");
+ when others =>
+ null;
+ end case;
+ count := count + 1;
+ end if;
+ end process;
+end rotate3;