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author | Aimylios <20016942+aimylios@users.noreply.github.com> | 2020-04-19 14:20:37 +0200 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2020-04-19 16:08:35 +0200 |
commit | 8bb8453af7acd34705a449cac9cd8427d6db43ba (patch) | |
tree | 9243aaa5ec9c4f91abd7291af432dbba41772815 /examples/icestick/leds | |
parent | d941c8f65bbbb90f97c17e26b5610624c2198b10 (diff) | |
download | ghdl-yosys-plugin-8bb8453af7acd34705a449cac9cd8427d6db43ba.tar.gz ghdl-yosys-plugin-8bb8453af7acd34705a449cac9cd8427d6db43ba.tar.bz2 ghdl-yosys-plugin-8bb8453af7acd34705a449cac9cd8427d6db43ba.zip |
Improve examples for Lattice iCEstick
- move "leds" examples to subdirectory
- add Makefile
- add *.json files to .gitignore
- adjust README.md and fix some typos
Diffstat (limited to 'examples/icestick/leds')
-rw-r--r-- | examples/icestick/leds/Makefile | 34 | ||||
-rw-r--r-- | examples/icestick/leds/blink.vhdl | 23 | ||||
-rw-r--r-- | examples/icestick/leds/fixed1.vhdl | 4 | ||||
-rw-r--r-- | examples/icestick/leds/leds.pcf | 6 | ||||
-rw-r--r-- | examples/icestick/leds/leds.vhdl | 16 | ||||
-rw-r--r-- | examples/icestick/leds/multi1.vhdl | 83 | ||||
-rw-r--r-- | examples/icestick/leds/multi2.vhdl | 41 | ||||
-rw-r--r-- | examples/icestick/leds/rotate1.vhdl | 51 | ||||
-rw-r--r-- | examples/icestick/leds/rotate2.vhdl | 35 | ||||
-rw-r--r-- | examples/icestick/leds/rotate3.vhdl | 38 | ||||
-rw-r--r-- | examples/icestick/leds/rotate4.vhdl | 41 | ||||
-rw-r--r-- | examples/icestick/leds/spin1.vhdl | 51 | ||||
-rw-r--r-- | examples/icestick/leds/spin2.vhdl | 51 |
13 files changed, 474 insertions, 0 deletions
diff --git a/examples/icestick/leds/Makefile b/examples/icestick/leds/Makefile new file mode 100644 index 0000000..77a610d --- /dev/null +++ b/examples/icestick/leds/Makefile @@ -0,0 +1,34 @@ +PROJ = blink +#PROJ = fixed1 +#PROJ = multi1 +#PROJ = multi2 +#PROJ = rotate1 +#PROJ = rotate2 +#PROJ = rotate3 +#PROJ = rotate4 +#PROJ = spin1 +#PROJ = spin2 + +PIN_DEF = leds.pcf +DEVICE = hx1k + +all: $(PROJ).bin + +%.json: leds.vhdl %.vhdl + yosys -m ghdl -p 'ghdl $^ -e leds; synth_ice40 -json $@' + +%.asc: %.json + nextpnr-ice40 --package $(DEVICE) --pcf $(PIN_DEF) --json $< --asc $@ + +%.bin: %.asc + icepack $< $@ + +prog: $(PROJ).bin + iceprog $< + +clean: + rm -f $(PROJ).json $(PROJ).asc $(PROJ).bin + +.SECONDARY: + +.PHONY: all prog clean diff --git a/examples/icestick/leds/blink.vhdl b/examples/icestick/leds/blink.vhdl new file mode 100644 index 0000000..d7e6dd4 --- /dev/null +++ b/examples/icestick/leds/blink.vhdl @@ -0,0 +1,23 @@ +architecture blink of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= not clk_4hz; + else + counter := counter + 1; + end if; + end if; + end process; + + led1 <= clk_4hz; + led2 <= clk_4hz; + led3 <= clk_4hz; + led4 <= clk_4hz; + led5 <= clk_4hz; +end blink; diff --git a/examples/icestick/leds/fixed1.vhdl b/examples/icestick/leds/fixed1.vhdl new file mode 100644 index 0000000..b1bbf4b --- /dev/null +++ b/examples/icestick/leds/fixed1.vhdl @@ -0,0 +1,4 @@ +architecture fixed1 of leds is +begin + (led1, led2, led3, led4, led5) <= std_logic_vector'("00101"); +end fixed1; diff --git a/examples/icestick/leds/leds.pcf b/examples/icestick/leds/leds.pcf new file mode 100644 index 0000000..397bdc4 --- /dev/null +++ b/examples/icestick/leds/leds.pcf @@ -0,0 +1,6 @@ +set_io led1 99
+set_io led2 98
+set_io led3 97
+set_io led4 96
+set_io led5 95
+set_io clk 21
diff --git a/examples/icestick/leds/leds.vhdl b/examples/icestick/leds/leds.vhdl new file mode 100644 index 0000000..95aa5cf --- /dev/null +++ b/examples/icestick/leds/leds.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Led positions +-- +-- I D3 +-- r +-- D D2 D5 D4 +-- A +-- D1 +-- +entity leds is + port (clk : in std_logic; + led1, led2, led3, led4, led5 : out std_logic); +end leds; diff --git a/examples/icestick/leds/multi1.vhdl b/examples/icestick/leds/multi1.vhdl new file mode 100644 index 0000000..a304765 --- /dev/null +++ b/examples/icestick/leds/multi1.vhdl @@ -0,0 +1,83 @@ +architecture multi1 of leds is + signal clk_4hz: std_logic; + signal clk_5sec : std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable counter5 : unsigned (4 downto 0); + begin + if rising_edge (clk) then + clk_5sec <= '0'; + if clk_4hz = '1' then + if counter5 = 19 then + clk_5sec <= '1'; + counter5 := "00000"; + else + counter5 := counter5 + 1; + end if; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + variable pat_count : unsigned (0 downto 0); + begin + if rising_edge(clk) then + if clk_4hz = '1' then + case pat_count is + when "0" => + case count is + when "00" => + leds <= "10001"; + when "01" => + leds <= "01000"; + when "10" => + leds <= "00101"; + when "11" => + leds <= "00010"; + when others => + null; + end case; + when "1" => + case count is + when "00" => + leds <= "10000"; + when "01" => + leds <= "01011"; + when "10" => + leds <= "00100"; + when "11" => + leds <= "01011"; + when others => + null; + end case; + when others => + null; + end case; + count := count + 1; + end if; + if clk_5sec = '1' then + pat_count := pat_count + 1; + count := "00"; + end if; + end if; + end process; +end multi1; diff --git a/examples/icestick/leds/multi2.vhdl b/examples/icestick/leds/multi2.vhdl new file mode 100644 index 0000000..78bf298 --- /dev/null +++ b/examples/icestick/leds/multi2.vhdl @@ -0,0 +1,41 @@ +architecture multi2 of leds is + signal clk_4hz: std_logic; + signal clk_5sec : std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable counter5 : unsigned (4 downto 0); + begin + if rising_edge (clk) then + clk_5sec <= '0'; + if clk_4hz = '1' then + if counter5 = 19 then + clk_5sec <= '1'; + counter5 := "00000"; + else + counter5 := counter5 + 1; + end if; + end if; + end if; + end process; + + led1 <= clk_5sec; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; +end multi2; diff --git a/examples/icestick/leds/rotate1.vhdl b/examples/icestick/leds/rotate1.vhdl new file mode 100644 index 0000000..34c7afd --- /dev/null +++ b/examples/icestick/leds/rotate1.vhdl @@ -0,0 +1,51 @@ +architecture rotate1 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + count := count + 1; + if count = 0 then + led1 <= '1'; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '1'; + elsif count = 1 then + led1 <= '0'; + led2 <= '1'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; + elsif count = 2 then + led1 <= '0'; + led2 <= '0'; + led3 <= '1'; + led4 <= '0'; + led5 <= '1'; + else + led1 <= '0'; + led2 <= '0'; + led3 <= '0'; + led4 <= '1'; + led5 <= '0'; + end if; + end if; + end process; +end rotate1; diff --git a/examples/icestick/leds/rotate2.vhdl b/examples/icestick/leds/rotate2.vhdl new file mode 100644 index 0000000..e51ec6c --- /dev/null +++ b/examples/icestick/leds/rotate2.vhdl @@ -0,0 +1,35 @@ +architecture rotate2 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + count := count + 1; + if count = 0 then + (led1, led2, led3, led4, led5) <= unsigned'("10001"); + elsif count = 1 then + (led1, led2, led3, led4, led5) <= unsigned'("01000"); + elsif count = 2 then + (led1, led2, led3, led4, led5) <= unsigned'("00101"); + else + (led1, led2, led3, led4, led5) <= unsigned'("00010"); + end if; + end if; + end process; +end rotate2; diff --git a/examples/icestick/leds/rotate3.vhdl b/examples/icestick/leds/rotate3.vhdl new file mode 100644 index 0000000..213512f --- /dev/null +++ b/examples/icestick/leds/rotate3.vhdl @@ -0,0 +1,38 @@ +architecture rotate3 of leds is + signal clk_4hz: std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + case count is + when "00" => + (led1, led2, led3, led4, led5) <= unsigned'("10001"); + when "01" => + (led1, led2, led3, led4, led5) <= unsigned'("01000"); + when "10" => + (led1, led2, led3, led4, led5) <= unsigned'("00101"); + when "11" => + (led1, led2, led3, led4, led5) <= unsigned'("00010"); + when others => + null; + end case; + count := count + 1; + end if; + end process; +end rotate3; diff --git a/examples/icestick/leds/rotate4.vhdl b/examples/icestick/leds/rotate4.vhdl new file mode 100644 index 0000000..e89aaa5 --- /dev/null +++ b/examples/icestick/leds/rotate4.vhdl @@ -0,0 +1,41 @@ +architecture rotate4 of leds is + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable count : unsigned (1 downto 0); + begin + if rising_edge(clk) and clk_4hz = '1' then + case count is + when "00" => + leds <= "10001"; + when "01" => + leds <= "01000"; + when "10" => + leds <= "00101"; + when "11" => + leds <= "00010"; + when others => + null; + end case; + count := count + 1; + end if; + end process; +end rotate4; diff --git a/examples/icestick/leds/spin1.vhdl b/examples/icestick/leds/spin1.vhdl new file mode 100644 index 0000000..79e305c --- /dev/null +++ b/examples/icestick/leds/spin1.vhdl @@ -0,0 +1,51 @@ +architecture spin1 of leds is + signal nrst : std_logic := '0'; + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + variable cnt : unsigned (1 downto 0) := "00"; + begin + if rising_edge (clk) then + if cnt = 3 then + nrst <= '1'; + else + cnt := cnt + 1; + end if; + end if; + end process; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if nrst = '0' then + counter := x"000000"; + else + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if nrst = '0' then + -- Initialize + leds <= "11000"; + elsif clk_4hz = '1' then + -- Rotate + leds <= (leds (4), leds (1), leds (2), leds (3), '0'); + end if; + end if; + end process; +end spin1; diff --git a/examples/icestick/leds/spin2.vhdl b/examples/icestick/leds/spin2.vhdl new file mode 100644 index 0000000..0f23964 --- /dev/null +++ b/examples/icestick/leds/spin2.vhdl @@ -0,0 +1,51 @@ +architecture spin1 of leds is + signal nrst : std_logic := '0'; + signal clk_4hz: std_logic; + signal leds : std_ulogic_vector (1 to 5); +begin + (led1, led2, led3, led4, led5) <= leds; + + process (clk) + variable cnt : unsigned (1 downto 0) := "00"; + begin + if rising_edge (clk) then + if cnt = 3 then + nrst <= '1'; + else + cnt := cnt + 1; + end if; + end if; + end process; + + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if nrst = '0' then + counter := x"000000"; + else + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if nrst = '0' then + -- Initialize + leds <= "11000"; + elsif clk_4hz = '1' then + -- Rotate + leds <= leds (4) & leds (1) & leds (2) & leds (3) & '0'; + end if; + end if; + end process; +end spin1; |