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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-16 05:43:03 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-16 05:43:03 +0200 |
| commit | 0b29a7cb792bd07b112671a264defcb1085ba402 (patch) | |
| tree | 3fc8c9486884676b7f55f6a95c57774c696e1442 /ice40hx8k | |
| parent | 96ceed2f296a44ca60fc8cd0f91c35edcc2d7b41 (diff) | |
| download | ghdl-yosys-plugin-0b29a7cb792bd07b112671a264defcb1085ba402.tar.gz ghdl-yosys-plugin-0b29a7cb792bd07b112671a264defcb1085ba402.tar.bz2 ghdl-yosys-plugin-0b29a7cb792bd07b112671a264defcb1085ba402.zip | |
Sign extend 32b literals (#61)
* sign extend 32b literals
* Fix undefined behavior
Right shift of a signed values is undefined but does
arithemetic shift in practice.
However, shifting by more than one int width
is also undefined but *wraps around*.
This caused bit/log to work because it'd shift mod 32.
But it actually cause the UL32 to be wrong
because it'd just repeat the value rather than extending.
* zero pad unsigned and add signed
* add testsuite
Diffstat (limited to 'ice40hx8k')
0 files changed, 0 insertions, 0 deletions