diff options
| -rw-r--r-- | src/ghdl.cc | 55 | ||||
| -rwxr-xr-x | testsuite/pr61/testsuite.sh | 12 | ||||
| -rw-r--r-- | testsuite/pr61/vector.vhdl | 15 |
3 files changed, 78 insertions, 4 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 8d6a287..d6c3cba 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -87,8 +87,7 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) RTLIL::SigSpec res = IN(0); return res.extract(0, get_width(n)); } - case Id_Const_Bit: - case Id_Const_UB32: + case Id_Const_Bit: // arbitrary width binary { const unsigned wd = get_width(n); std::vector<RTLIL::State> bits(wd); @@ -96,10 +95,31 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) for (unsigned i = 0; i < wd; i++) { if (i % 32 == 0) val = get_param_uns32(inst, i / 32); + bits[i] = (val >> (i%32)) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; + } + return RTLIL::SigSpec(RTLIL::Const(bits)); + } + case Id_Const_UB32: // zero padded binary + { + const unsigned wd = get_width(n); + std::vector<RTLIL::State> bits(wd); + unsigned int val = get_param_uns32(inst, 0); + for (unsigned i = 0; i < wd && i < 32; i++) { bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; } return RTLIL::SigSpec(RTLIL::Const(bits)); } + case Id_Const_SB32: // sign extended binary + { + const unsigned wd = get_width(n); + std::vector<RTLIL::State> bits(wd); + unsigned int val = get_param_uns32(inst, 0); + for (unsigned i = 0; i < wd; i++) { + unsigned idx = i < 32 ? i : 31; + bits[i] = (val >> idx) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; + } + return RTLIL::SigSpec(RTLIL::Const(bits)); + } case Id_Const_Z: { return SigSpec(RTLIL::State::Sz, get_width(n)); @@ -108,8 +128,7 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) { return SigSpec(RTLIL::State::Sx, get_width(n)); } - case Id_Const_Log: - case Id_Const_UL32: + case Id_Const_Log: // arbitrary lenght 01ZX { const unsigned wd = get_width(n); std::vector<RTLIL::State> bits(wd); @@ -120,6 +139,32 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) val01 = get_param_uns32(inst, 2*(i / 32)); valzx = get_param_uns32(inst, 2*(i / 32) + 1); } + switch(((val01 >> (i%32))&1)+((valzx >> (i%32))&1)*2) + { + case 0: + bits[i] = RTLIL::State::S0; + break; + case 1: + bits[i] = RTLIL::State::S1; + break; + case 2: + bits[i] = RTLIL::State::Sz; + break; + case 3: + bits[i] = RTLIL::State::Sx; + break; + } + + } + return RTLIL::SigSpec(RTLIL::Const(bits)); + } + case Id_Const_UL32: // zero padded 01ZX + { + const unsigned wd = get_width(n); + std::vector<RTLIL::State> bits(wd); + unsigned int val01 = get_param_uns32(inst, 0); + unsigned int valzx = get_param_uns32(inst, 0); + for (unsigned i = 0; i < wd && i < 32; i++) { switch(((val01 >> i)&1)+((valzx >> i)&1)*2) { case 0: @@ -328,6 +373,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Output: case Id_Port: case Id_Const_UB32: + case Id_Const_SB32: case Id_Const_UL32: case Id_Const_Bit: case Id_Const_Log: @@ -523,6 +569,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->addCover(to_str(iname), IN(0), State::S1); break; case Id_Const_UB32: + case Id_Const_SB32: case Id_Const_UL32: case Id_Const_Bit: case Id_Const_Log: diff --git a/testsuite/pr61/testsuite.sh b/testsuite/pr61/testsuite.sh new file mode 100755 index 0000000..3ff1a15 --- /dev/null +++ b/testsuite/pr61/testsuite.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +. ../testenv.sh + +run_yosys -p "ghdl vector.vhdl -e vector; dump -o vector.il" + +grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1 +grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1 +grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1 +grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1 + +clean diff --git a/testsuite/pr61/vector.vhdl b/testsuite/pr61/vector.vhdl new file mode 100644 index 0000000..61a0d67 --- /dev/null +++ b/testsuite/pr61/vector.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (v: out signed(63 downto 0); + u: out unsigned(63 downto 0)); +end vector; + +architecture synth of vector is + +begin + v <= signed'(x"0ffffffffffffff0")+(-1); + u <= unsigned'(x"00ffffffffffff00")+4294967290; +end synth; |