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authorTristan Gingold <tgingold@free.fr>2017-02-02 21:35:01 +0100
committerTristan Gingold <tgingold@free.fr>2017-02-02 21:35:01 +0100
commitbd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch)
tree194781d16b082ae259f17dd8dc12b84b04ec7105 /icestick/rotate3.vhdl
parentfa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff)
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Diffstat (limited to 'icestick/rotate3.vhdl')
-rw-r--r--icestick/rotate3.vhdl38
1 files changed, 38 insertions, 0 deletions
diff --git a/icestick/rotate3.vhdl b/icestick/rotate3.vhdl
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+architecture rotate3 of leds is
+ signal clk_4hz: std_logic;
+begin
+ process (clk)
+ -- 3_000_000 is 0x2dc6c0
+ variable counter : unsigned (23 downto 0);
+ begin
+ if rising_edge(clk) then
+ if counter = 2_999_999 then
+ counter := x"000000";
+ clk_4hz <= '1';
+ else
+ counter := counter + 1;
+ clk_4hz <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ variable count : unsigned (1 downto 0);
+ begin
+ if rising_edge(clk) and clk_4hz = '1' then
+ case count is
+ when "00" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("10001");
+ when "01" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("01000");
+ when "10" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("00101");
+ when "11" =>
+ (led1, led2, led3, led4, led5) <= unsigned'("00010");
+ when others =>
+ null;
+ end case;
+ count := count + 1;
+ end if;
+ end process;
+end rotate3;